{ "recorded_at": "2026-10-02T17:53:51.260432+00:00", "platform": "macOS-26.2-arm64-arm-64bit", "device": "Apple M5", "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "mlx_version": "0.32.0", "compiler_implementation_sha256": "81570d03d2db5ba7146d00acd5feb8e3ed9e0a0139d9018a1bf4c0b83703f9cf", "baseline_compiler_implementation_sha256": "d258683dcf0a92130bc92c14d306b75dfdb1194f300bbdc9aafe671cb6ffff65", "baseline_root": "/private/tmp/metile-register-baseline.XcgyHS", "current_root": "/Users/andreslavescu/Documents/projects/meTile", "benchmark_source_sha256": "3c6fb7144a3c48de6c74a2626eb7fd05b4c4d41918c7ac43d9dcc93165447c61", "baseline_method": "baseline subprocess exports verified MSL and ABI; frozen baseline, candidate and current control shaders are explicitly rebuilt with the same offline Metal path (-O2 -ffast-math), or uniformly checked runtime fallback, then alternated in the current Metal runtime", "specialization_caveat": "candidate specializes N at compile time and retains a 1024-element row as four registers per thread; both controls use runtime N and BLOCK=256, so gains cannot be attributed solely to register retention", "metrics": { "gpu": "Metal command-buffer timestamps; candidate and meTile controls only", "wall": "per-invocation synchronized wall latency; compile/setup excluded; includes MLX allocation and graph evaluation" }, "precision_comparison": { "class": "same_storage_precision", "same_weight_representation": true, "bitwise_exact": false, "primary_policy": "identical FP16/FP32 storage, FP32 sum-of-squares and normalization, FP32 weight multiply, one final output cast", "primary_mlx_comparator": "mx.compile explicit FP32 normalization/weight multiplication before final output cast", "mlx_fast_caveat": "mx.fast.rms_norm v0.32.0 rounds normalized input to storage dtype before multiplying weights; FP16 comparison is separately labeled and not identical rounding policy", "mlx_fast_source": "https://github.com/ml-explore/mlx/blob/v0.32.0/mlx/backend/metal/kernels/rms_norm.metal", "reference": "seeded NumPy FP32 reduction; meTile/matched-MLX and fast-MLX each checked against their own rounding-boundary reference" }, "configuration": { "seed": 619, "layout": "identity", "rounds": 3, "warmup_ms": 100.0, "rep_ms": 250.0 }, "cases": [ { "name": "float16_1x1009", "dtype": "float16", "batches": 1, "width": 1009, "input_sha256": "cb6dd90eb0a5bc181128b665f829e53cb4946745126205c9d191260c99b2feae", "epsilon": 1e-05, "candidate_layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "elements_per_thread": 4 }, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "frozen_baseline": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "current_control": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "mlx_matched": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "mlx_fast": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002, "max_difference_from_matched_policy": 0.001953125 } }, "validated_before_timing": true, "shaders": { "candidate": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "current_control": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant int& N [[buffer(3)]],\n constant float& eps [[buffer(4)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v1 = v0 * N;\n float _acc_0 = 0.0f;\n const int _ew_end_0 = (N / 1024) * 1024;\n for (int v9 = 0; v9 < _ew_end_0; v9 += 1024) {\n int lane_v10 = static_cast(lid) * 4;\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n half4 v18 = *(device const half4*)(X + _off_v17);\n float4 v19 = float4(v18);\n float4 v20 = v19 * v19;\n float v22 = _acc_0 + (v20.x + v20.y + v20.z + v20.w);\n _acc_0 = v22;\n }\n for (int v9 = _ew_end_0; v9 < N; v9 += 256) {\n int lane_v10 = static_cast(lid);\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n half v18 = v16 ? X[_off_v17] : static_cast(0);\n float v19 = static_cast(v18);\n float v20 = v19 * v19;\n float v22 = _acc_0 + v20;\n _acc_0 = v22;\n }\n threadgroup float shared_reduce_0[8];\n float v23;\n {\n float _simd_val = simd_sum(_acc_0);\n if (slid == 0u) shared_reduce_0[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (lid < 8u) ? shared_reduce_0[lid] : 0.0f;\n float _result = simd_sum(_partial);\n if (lid == 0u) shared_reduce_0[0] = _result;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n v23 = shared_reduce_0[0];\n }\n float cast_v24 = static_cast(N);\n float v24 = v23 / cast_v24;\n float v25 = v24 + eps;\n float v26 = sqrt(v25);\n float v28 = 1.0f / v26;\n const int _ew_end_1 = (N / 1024) * 1024;\n for (int v30 = 0; v30 < _ew_end_1; v30 += 1024) {\n int lane_v31 = static_cast(lid) * 4;\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n half4 v39 = *(device const half4*)(X + _off_v38);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n half4 v46 = *(device const half4*)(W + v32);\n float4 v47 = float4(v39);\n float4 v48 = v47 * v28;\n float4 v49 = float4(v46);\n float4 v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n *(device half4*)(Out + _off_v55) = half4(v50);\n }\n for (int v30 = _ew_end_1; v30 < N; v30 += 256) {\n int lane_v31 = static_cast(lid);\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n half v39 = v37 ? X[_off_v38] : static_cast(0);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n half v46 = v44 ? W[v32] : static_cast(0);\n float v47 = static_cast(v39);\n float v48 = v47 * v28;\n float v49 = static_cast(v46);\n float v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n if (v54) { Out[_off_v55] = v50; }\n }\n}", "source_sha256": "a144da61ff8c1bf3999ad29ca977b4c3ff2631afbcbacba9ed05d825c967d448", "function_name": "mtile_rmsnorm", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3, 4 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 256 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "scalar lanes", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [ { "induction_variable": "v9", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v9", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 }, { "induction_variable": "v30", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v30", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 } ], "allocations": [ { "name": "shared_reduce_0", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [], "layout_conversions": [], "pipelines": [], "register_reductions": [], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "frozen_baseline": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant int& N [[buffer(3)]],\n constant float& eps [[buffer(4)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v1 = v0 * N;\n float _acc_0 = 0.0f;\n const int _ew_end_0 = (N / 1024) * 1024;\n for (int v9 = 0; v9 < _ew_end_0; v9 += 1024) {\n int lane_v10 = static_cast(lid) * 4;\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n half4 v18 = *(device const half4*)(X + _off_v17);\n float4 v19 = float4(v18);\n float4 v20 = v19 * v19;\n float v22 = _acc_0 + (v20.x + v20.y + v20.z + v20.w);\n _acc_0 = v22;\n }\n for (int v9 = _ew_end_0; v9 < N; v9 += 256) {\n int lane_v10 = static_cast(lid);\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n half v18 = v16 ? X[_off_v17] : static_cast(0);\n float v19 = static_cast(v18);\n float v20 = v19 * v19;\n float v22 = _acc_0 + v20;\n _acc_0 = v22;\n }\n threadgroup float shared_reduce_0[8];\n float v23;\n {\n float _simd_val = simd_sum(_acc_0);\n if (slid == 0u) shared_reduce_0[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (lid < 8u) ? shared_reduce_0[lid] : 0.0f;\n float _result = simd_sum(_partial);\n if (lid == 0u) shared_reduce_0[0] = _result;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n v23 = shared_reduce_0[0];\n }\n float cast_v24 = static_cast(N);\n float v24 = v23 / cast_v24;\n float v25 = v24 + eps;\n float v26 = sqrt(v25);\n float v28 = 1.0f / v26;\n const int _ew_end_1 = (N / 1024) * 1024;\n for (int v30 = 0; v30 < _ew_end_1; v30 += 1024) {\n int lane_v31 = static_cast(lid) * 4;\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n half4 v39 = *(device const half4*)(X + _off_v38);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n half4 v46 = *(device const half4*)(W + v32);\n float4 v47 = float4(v39);\n float4 v48 = v47 * v28;\n float4 v49 = float4(v46);\n float4 v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n *(device half4*)(Out + _off_v55) = half4(v50);\n }\n for (int v30 = _ew_end_1; v30 < N; v30 += 256) {\n int lane_v31 = static_cast(lid);\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n half v39 = v37 ? X[_off_v38] : static_cast(0);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n half v46 = v44 ? W[v32] : static_cast(0);\n float v47 = static_cast(v39);\n float v48 = v47 * v28;\n float v49 = static_cast(v46);\n float v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n if (v54) { Out[_off_v55] = v50; }\n }\n}", "source_sha256": "a144da61ff8c1bf3999ad29ca977b4c3ff2631afbcbacba9ed05d825c967d448", "function_name": "mtile_rmsnorm", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3, 4 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 256 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "scalar lanes", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [ { "induction_variable": "v9", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v9", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 }, { "induction_variable": "v30", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v30", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 } ], "allocations": [ { "name": "shared_reduce_0", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [], "layout_conversions": [], "pipelines": [] } } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "current_control": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_baseline": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "rounds": [ { "frozen_baseline": { "pairs": 607, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 205.958, "control": 206.584, "speedup": 1.003039454646093 }, "gpu_us": { "candidate": 1.5833647921681404, "control": 2.7500209398567677, "speedup": 1.7368208219983825 } }, "current_control": { "pairs": 605, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 203.125, "control": 202.916, "speedup": 0.998971076923077 }, "gpu_us": { "candidate": 1.5833647921681404, "control": 2.7500209398567677, "speedup": 1.7368208219983825 } }, "mlx_matched": { "pairs": 434, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.16649999999998, "control": 206.937, "speedup": 1.013569806995761 } }, "mlx_fast": { "pairs": 508, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 206.9795, "control": 202.10399999999998, "speedup": 0.9764445271150041 } } }, { "current_control": { "pairs": 610, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.6045, "control": 199.27100000000002, "speedup": 1.0033559159032148 }, "gpu_us": { "candidate": 1.5833647921681404, "control": 2.7500209398567677, "speedup": 1.7368208219983825 } }, "mlx_matched": { "pairs": 593, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.333, "control": 203.625, "speedup": 1.0164326396549745 } }, "mlx_fast": { "pairs": 580, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 203.9375, "control": 200.0, "speedup": 0.9806926141587496 } }, "frozen_baseline": { "pairs": 613, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.25, "control": 198.917, "speedup": 1.0033644388398486 }, "gpu_us": { "candidate": 1.5833647921681404, "control": 2.7500209398567677, "speedup": 1.7368208219983825 } } }, { "mlx_matched": { "pairs": 594, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.875, "control": 202.834, "speedup": 1.0097523335407592 } }, "mlx_fast": { "pairs": 610, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.542, "control": 196.792, "speedup": 0.9764317115043019 } }, "frozen_baseline": { "pairs": 600, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.2705, "control": 196.792, "speedup": 0.9875621328796786 }, "gpu_us": { "candidate": 1.6249832697212696, "control": 2.7500209398567677, "speedup": 1.6923380019343053 } }, "current_control": { "pairs": 601, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.083, "control": 197.833, "speedup": 1.0038055032651219 }, "gpu_us": { "candidate": 1.6249832697212696, "control": 2.7500209398567677, "speedup": 1.6923380019343053 } } } ], "summary": { "current_control": { "gpu_us": { "speedup": 1.7218647963946618, "round_speedups": [ 1.7368208219983825, 1.7368208219983825, 1.6923380019343053 ], "candidate": 1.5971178141366953, "control": 2.750020939856767 }, "wall_us": { "speedup": 1.002041790039614, "round_speedups": [ 0.998971076923077, 1.0033559159032148, 1.0038055032651219 ], "candidate": 199.58774701335938, "control": 199.99526328724028 } }, "frozen_baseline": { "gpu_us": { "speedup": 1.7218647963946618, "round_speedups": [ 1.7368208219983825, 1.7368208219983825, 1.6923380019343053 ], "candidate": 1.5971178141366953, "control": 2.750020939856767 }, "wall_us": { "speedup": 0.9979613381683544, "round_speedups": [ 1.003039454646093, 1.0033644388398486, 0.9875621328796786 ], "candidate": 201.13066558899246, "control": 200.72062817788276 } }, "mlx_fast": { "wall_us": { "speedup": 0.9778542294939652, "round_speedups": [ 0.9764445271150041, 0.9806926141587496, 0.9764317115043019 ], "candidate": 204.14088640254886, "control": 199.62002918137964 } }, "mlx_matched": { "wall_us": { "speedup": 1.0132478970121022, "round_speedups": [ 1.013569806995761, 1.0164326396549745, 1.0097523335407592 ], "candidate": 201.78441623991748, "control": 204.45763540491103 } } } }, { "name": "float16_32x1009", "dtype": "float16", "batches": 32, "width": 1009, "input_sha256": "014d6f63aaa0f6df36a02e5886f8360dab7051acc3349829679366e37844867f", "epsilon": 1e-05, "candidate_layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "elements_per_thread": 4 }, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "frozen_baseline": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "current_control": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "mlx_matched": { "passed": true, "max_absolute_error": 0.000244140625, "rtol": 0.001, "atol": 0.002 }, "mlx_fast": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002, "max_difference_from_matched_policy": 0.00390625 } }, "validated_before_timing": true, "shaders": { "candidate": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "current_control": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant int& N [[buffer(3)]],\n constant float& eps [[buffer(4)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v1 = v0 * N;\n float _acc_0 = 0.0f;\n const int _ew_end_0 = (N / 1024) * 1024;\n for (int v9 = 0; v9 < _ew_end_0; v9 += 1024) {\n int lane_v10 = static_cast(lid) * 4;\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n half4 v18 = *(device const half4*)(X + _off_v17);\n float4 v19 = float4(v18);\n float4 v20 = v19 * v19;\n float v22 = _acc_0 + (v20.x + v20.y + v20.z + v20.w);\n _acc_0 = v22;\n }\n for (int v9 = _ew_end_0; v9 < N; v9 += 256) {\n int lane_v10 = static_cast(lid);\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n half v18 = v16 ? X[_off_v17] : static_cast(0);\n float v19 = static_cast(v18);\n float v20 = v19 * v19;\n float v22 = _acc_0 + v20;\n _acc_0 = v22;\n }\n threadgroup float shared_reduce_0[8];\n float v23;\n {\n float _simd_val = simd_sum(_acc_0);\n if (slid == 0u) shared_reduce_0[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (lid < 8u) ? shared_reduce_0[lid] : 0.0f;\n float _result = simd_sum(_partial);\n if (lid == 0u) shared_reduce_0[0] = _result;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n v23 = shared_reduce_0[0];\n }\n float cast_v24 = static_cast(N);\n float v24 = v23 / cast_v24;\n float v25 = v24 + eps;\n float v26 = sqrt(v25);\n float v28 = 1.0f / v26;\n const int _ew_end_1 = (N / 1024) * 1024;\n for (int v30 = 0; v30 < _ew_end_1; v30 += 1024) {\n int lane_v31 = static_cast(lid) * 4;\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n half4 v39 = *(device const half4*)(X + _off_v38);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n half4 v46 = *(device const half4*)(W + v32);\n float4 v47 = float4(v39);\n float4 v48 = v47 * v28;\n float4 v49 = float4(v46);\n float4 v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n *(device half4*)(Out + _off_v55) = half4(v50);\n }\n for (int v30 = _ew_end_1; v30 < N; v30 += 256) {\n int lane_v31 = static_cast(lid);\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n half v39 = v37 ? X[_off_v38] : static_cast(0);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n half v46 = v44 ? W[v32] : static_cast(0);\n float v47 = static_cast(v39);\n float v48 = v47 * v28;\n float v49 = static_cast(v46);\n float v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n if (v54) { Out[_off_v55] = v50; }\n }\n}", "source_sha256": "a144da61ff8c1bf3999ad29ca977b4c3ff2631afbcbacba9ed05d825c967d448", "function_name": "mtile_rmsnorm", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3, 4 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 256 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "scalar lanes", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [ { "induction_variable": "v9", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v9", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 }, { "induction_variable": "v30", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v30", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 } ], "allocations": [ { "name": "shared_reduce_0", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [], "layout_conversions": [], "pipelines": [], "register_reductions": [], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "frozen_baseline": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant int& N [[buffer(3)]],\n constant float& eps [[buffer(4)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v1 = v0 * N;\n float _acc_0 = 0.0f;\n const int _ew_end_0 = (N / 1024) * 1024;\n for (int v9 = 0; v9 < _ew_end_0; v9 += 1024) {\n int lane_v10 = static_cast(lid) * 4;\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n half4 v18 = *(device const half4*)(X + _off_v17);\n float4 v19 = float4(v18);\n float4 v20 = v19 * v19;\n float v22 = _acc_0 + (v20.x + v20.y + v20.z + v20.w);\n _acc_0 = v22;\n }\n for (int v9 = _ew_end_0; v9 < N; v9 += 256) {\n int lane_v10 = static_cast(lid);\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n half v18 = v16 ? X[_off_v17] : static_cast(0);\n float v19 = static_cast(v18);\n float v20 = v19 * v19;\n float v22 = _acc_0 + v20;\n _acc_0 = v22;\n }\n threadgroup float shared_reduce_0[8];\n float v23;\n {\n float _simd_val = simd_sum(_acc_0);\n if (slid == 0u) shared_reduce_0[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (lid < 8u) ? shared_reduce_0[lid] : 0.0f;\n float _result = simd_sum(_partial);\n if (lid == 0u) shared_reduce_0[0] = _result;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n v23 = shared_reduce_0[0];\n }\n float cast_v24 = static_cast(N);\n float v24 = v23 / cast_v24;\n float v25 = v24 + eps;\n float v26 = sqrt(v25);\n float v28 = 1.0f / v26;\n const int _ew_end_1 = (N / 1024) * 1024;\n for (int v30 = 0; v30 < _ew_end_1; v30 += 1024) {\n int lane_v31 = static_cast(lid) * 4;\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n half4 v39 = *(device const half4*)(X + _off_v38);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n half4 v46 = *(device const half4*)(W + v32);\n float4 v47 = float4(v39);\n float4 v48 = v47 * v28;\n float4 v49 = float4(v46);\n float4 v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n *(device half4*)(Out + _off_v55) = half4(v50);\n }\n for (int v30 = _ew_end_1; v30 < N; v30 += 256) {\n int lane_v31 = static_cast(lid);\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n half v39 = v37 ? X[_off_v38] : static_cast(0);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n half v46 = v44 ? W[v32] : static_cast(0);\n float v47 = static_cast(v39);\n float v48 = v47 * v28;\n float v49 = static_cast(v46);\n float v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n if (v54) { Out[_off_v55] = v50; }\n }\n}", "source_sha256": "a144da61ff8c1bf3999ad29ca977b4c3ff2631afbcbacba9ed05d825c967d448", "function_name": "mtile_rmsnorm", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3, 4 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 256 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "scalar lanes", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [ { "induction_variable": "v9", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v9", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 }, { "induction_variable": "v30", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v30", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 } ], "allocations": [ { "name": "shared_reduce_0", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [], "layout_conversions": [], "pipelines": [] } } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "current_control": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_baseline": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "rounds": [ { "frozen_baseline": { "pairs": 605, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.125, "control": 200.042, "speedup": 1.0096757097791798 }, "gpu_us": { "candidate": 2.00001522898674, "control": 2.874992787837982, "speedup": 1.4374854481955763 } }, "current_control": { "pairs": 598, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.1045, "control": 199.25, "speedup": 1.0057823017649776 }, "gpu_us": { "candidate": 2.00001522898674, "control": 2.874992787837982, "speedup": 1.4374854481955763 } }, "mlx_matched": { "pairs": 578, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.95850000000002, "control": 208.08350000000002, "speedup": 1.03032801293335 } }, "mlx_fast": { "pairs": 599, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.166, "control": 200.417, "speedup": 1.0012539592138525 } } }, { "current_control": { "pairs": 597, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.5, "control": 198.291, "speedup": 0.9939398496240601 }, "gpu_us": { "candidate": 2.0416337065398693, "control": 2.874992787837982, "speedup": 1.4081824661439772 } }, "mlx_matched": { "pairs": 568, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.70850000000002, "control": 209.7285, "speedup": 1.0346310095531266 } }, "mlx_fast": { "pairs": 600, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.6045, "control": 200.3545, "speedup": 0.9937997415732288 } }, "frozen_baseline": { "pairs": 605, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.708, "control": 198.625, "speedup": 0.9995823016687804 }, "gpu_us": { "candidate": 2.0416337065398693, "control": 2.874992787837982, "speedup": 1.4081824661439772 } } }, { "mlx_matched": { "pairs": 555, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 203.375, "control": 212.667, "speedup": 1.0456889981561155 } }, "mlx_fast": { "pairs": 606, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.5625, "control": 197.52100000000002, "speedup": 0.9897701221421861 } }, "frozen_baseline": { "pairs": 614, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.0625, "control": 198.64600000000002, "speedup": 0.9979076923076924 }, "gpu_us": { "candidate": 2.00001522898674, "control": 2.833374310284853, "speedup": 1.416676367869616 } }, "current_control": { "pairs": 551, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.583, "control": 197.959, "speedup": 0.9968577370671206 }, "gpu_us": { "candidate": 2.0416919142007828, "control": 2.874992787837982, "speedup": 1.4081423195347247 } } } ], "summary": { "current_control": { "gpu_us": { "speedup": 1.4178696728487559, "round_speedups": [ 1.4374854481955763, 1.4081824661439772, 1.4081423195347247 ], "candidate": 2.0276848026953025, "control": 2.874992787837982 }, "wall_us": { "speedup": 0.9988472817583213, "round_speedups": [ 1.0057823017649776, 0.9939398496240601, 0.9968577370671206 ], "candidate": 198.72832376647503, "control": 198.49924600253115 } }, "frozen_baseline": { "gpu_us": { "speedup": 1.4207282394777656, "round_speedups": [ 1.4374854481955763, 1.4081824661439772, 1.416676367869616 ], "candidate": 2.0137929251620275, "control": 2.8610524772382266 }, "wall_us": { "speedup": 1.0023751210257277, "round_speedups": [ 1.0096757097791798, 0.9995823016687804, 0.9979076923076924 ], "candidate": 198.631457157129, "control": 199.10323090739408 } }, "mlx_fast": { "wall_us": { "speedup": 0.9949299135437845, "round_speedups": [ 1.0012539592138525, 0.9937997415732288, 0.9897701221421861 ], "candidate": 200.4425055066802, "control": 199.4262446742609 } }, "mlx_matched": { "wall_us": { "speedup": 1.0368625271572616, "round_speedups": [ 1.03032801293335, 1.0346310095531266, 1.0456889981561155 ], "candidate": 202.67984062177328, "control": 210.15113175092293 } } } }, { "name": "float16_256x1009", "dtype": "float16", "batches": 256, "width": 1009, "input_sha256": "e64349f97c4a70f4c2180203b9e570a49c161d83253225e4064d07dd8bdf3f20", "epsilon": 1e-05, "candidate_layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "elements_per_thread": 4 }, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 }, "frozen_baseline": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 }, "current_control": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 }, "mlx_matched": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 }, "mlx_fast": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002, "max_difference_from_matched_policy": 0.00390625 } }, "validated_before_timing": true, "shaders": { "candidate": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "current_control": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant int& N [[buffer(3)]],\n constant float& eps [[buffer(4)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v1 = v0 * N;\n float _acc_0 = 0.0f;\n const int _ew_end_0 = (N / 1024) * 1024;\n for (int v9 = 0; v9 < _ew_end_0; v9 += 1024) {\n int lane_v10 = static_cast(lid) * 4;\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n half4 v18 = *(device const half4*)(X + _off_v17);\n float4 v19 = float4(v18);\n float4 v20 = v19 * v19;\n float v22 = _acc_0 + (v20.x + v20.y + v20.z + v20.w);\n _acc_0 = v22;\n }\n for (int v9 = _ew_end_0; v9 < N; v9 += 256) {\n int lane_v10 = static_cast(lid);\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n half v18 = v16 ? X[_off_v17] : static_cast(0);\n float v19 = static_cast(v18);\n float v20 = v19 * v19;\n float v22 = _acc_0 + v20;\n _acc_0 = v22;\n }\n threadgroup float shared_reduce_0[8];\n float v23;\n {\n float _simd_val = simd_sum(_acc_0);\n if (slid == 0u) shared_reduce_0[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (lid < 8u) ? shared_reduce_0[lid] : 0.0f;\n float _result = simd_sum(_partial);\n if (lid == 0u) shared_reduce_0[0] = _result;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n v23 = shared_reduce_0[0];\n }\n float cast_v24 = static_cast(N);\n float v24 = v23 / cast_v24;\n float v25 = v24 + eps;\n float v26 = sqrt(v25);\n float v28 = 1.0f / v26;\n const int _ew_end_1 = (N / 1024) * 1024;\n for (int v30 = 0; v30 < _ew_end_1; v30 += 1024) {\n int lane_v31 = static_cast(lid) * 4;\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n half4 v39 = *(device const half4*)(X + _off_v38);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n half4 v46 = *(device const half4*)(W + v32);\n float4 v47 = float4(v39);\n float4 v48 = v47 * v28;\n float4 v49 = float4(v46);\n float4 v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n *(device half4*)(Out + _off_v55) = half4(v50);\n }\n for (int v30 = _ew_end_1; v30 < N; v30 += 256) {\n int lane_v31 = static_cast(lid);\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n half v39 = v37 ? X[_off_v38] : static_cast(0);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n half v46 = v44 ? W[v32] : static_cast(0);\n float v47 = static_cast(v39);\n float v48 = v47 * v28;\n float v49 = static_cast(v46);\n float v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n if (v54) { Out[_off_v55] = v50; }\n }\n}", "source_sha256": "a144da61ff8c1bf3999ad29ca977b4c3ff2631afbcbacba9ed05d825c967d448", "function_name": "mtile_rmsnorm", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3, 4 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 256 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "scalar lanes", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [ { "induction_variable": "v9", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v9", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 }, { "induction_variable": "v30", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v30", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 } ], "allocations": [ { "name": "shared_reduce_0", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [], "layout_conversions": [], "pipelines": [], "register_reductions": [], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "frozen_baseline": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant int& N [[buffer(3)]],\n constant float& eps [[buffer(4)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v1 = v0 * N;\n float _acc_0 = 0.0f;\n const int _ew_end_0 = (N / 1024) * 1024;\n for (int v9 = 0; v9 < _ew_end_0; v9 += 1024) {\n int lane_v10 = static_cast(lid) * 4;\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n half4 v18 = *(device const half4*)(X + _off_v17);\n float4 v19 = float4(v18);\n float4 v20 = v19 * v19;\n float v22 = _acc_0 + (v20.x + v20.y + v20.z + v20.w);\n _acc_0 = v22;\n }\n for (int v9 = _ew_end_0; v9 < N; v9 += 256) {\n int lane_v10 = static_cast(lid);\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n half v18 = v16 ? X[_off_v17] : static_cast(0);\n float v19 = static_cast(v18);\n float v20 = v19 * v19;\n float v22 = _acc_0 + v20;\n _acc_0 = v22;\n }\n threadgroup float shared_reduce_0[8];\n float v23;\n {\n float _simd_val = simd_sum(_acc_0);\n if (slid == 0u) shared_reduce_0[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (lid < 8u) ? shared_reduce_0[lid] : 0.0f;\n float _result = simd_sum(_partial);\n if (lid == 0u) shared_reduce_0[0] = _result;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n v23 = shared_reduce_0[0];\n }\n float cast_v24 = static_cast(N);\n float v24 = v23 / cast_v24;\n float v25 = v24 + eps;\n float v26 = sqrt(v25);\n float v28 = 1.0f / v26;\n const int _ew_end_1 = (N / 1024) * 1024;\n for (int v30 = 0; v30 < _ew_end_1; v30 += 1024) {\n int lane_v31 = static_cast(lid) * 4;\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n half4 v39 = *(device const half4*)(X + _off_v38);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n half4 v46 = *(device const half4*)(W + v32);\n float4 v47 = float4(v39);\n float4 v48 = v47 * v28;\n float4 v49 = float4(v46);\n float4 v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n *(device half4*)(Out + _off_v55) = half4(v50);\n }\n for (int v30 = _ew_end_1; v30 < N; v30 += 256) {\n int lane_v31 = static_cast(lid);\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n half v39 = v37 ? X[_off_v38] : static_cast(0);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n half v46 = v44 ? W[v32] : static_cast(0);\n float v47 = static_cast(v39);\n float v48 = v47 * v28;\n float v49 = static_cast(v46);\n float v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n if (v54) { Out[_off_v55] = v50; }\n }\n}", "source_sha256": "a144da61ff8c1bf3999ad29ca977b4c3ff2631afbcbacba9ed05d825c967d448", "function_name": "mtile_rmsnorm", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3, 4 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 256 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "scalar lanes", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [ { "induction_variable": "v9", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v9", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 }, { "induction_variable": "v30", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v30", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 } ], "allocations": [ { "name": "shared_reduce_0", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [], "layout_conversions": [], "pipelines": [] } } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "current_control": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_baseline": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "rounds": [ { "frozen_baseline": { "pairs": 573, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 208.292, "control": 212.417, "speedup": 1.0198039290995333 }, "gpu_us": { "candidate": 5.541718564927578, "control": 8.791685104370117, "speedup": 1.5864546352120665 } }, "current_control": { "pairs": 578, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 209.167, "control": 211.97899999999998, "speedup": 1.0134438032768074 }, "gpu_us": { "candidate": 5.5416603572666645, "control": 8.833303581923246, "speedup": 1.5939814085394675 } }, "mlx_matched": { "pairs": 527, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 209.916, "control": 234.958, "speedup": 1.119295337182492 } }, "mlx_fast": { "pairs": 551, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 210.208, "control": 211.667, "speedup": 1.0069407444055412 } } }, { "current_control": { "pairs": 583, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.875, "control": 209.875, "speedup": 1.024405125076266 }, "gpu_us": { "candidate": 5.5416603572666645, "control": 8.791685104370117, "speedup": 1.5864712987763248 } }, "mlx_matched": { "pairs": 555, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 208.375, "control": 229.709, "speedup": 1.102382723455309 } }, "mlx_fast": { "pairs": 579, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 208.917, "control": 206.792, "speedup": 0.9898284964842498 } }, "frozen_baseline": { "pairs": 503, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 206.916, "control": 211.834, "speedup": 1.023768099132015 }, "gpu_us": { "candidate": 5.583337042480707, "control": 8.83336178958416, "speedup": 1.5820935978565696 } } }, { "mlx_matched": { "pairs": 520, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 211.9785, "control": 234.66649999999998, "speedup": 1.1070297223539178 } }, "mlx_fast": { "pairs": 503, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 214.5, "control": 216.5, "speedup": 1.0093240093240092 } }, "frozen_baseline": { "pairs": 545, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 209.583, "control": 216.333, "speedup": 1.0322068106668958 }, "gpu_us": { "candidate": 5.5416603572666645, "control": 8.791685104370117, "speedup": 1.5864712987763248 } }, "current_control": { "pairs": 566, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 210.938, "control": 215.39600000000002, "speedup": 1.021134172126407 }, "gpu_us": { "candidate": 5.5416603572666645, "control": 8.791685104370117, "speedup": 1.5864712987763248 } } } ], "summary": { "current_control": { "gpu_us": { "speedup": 1.5889707288646795, "round_speedups": [ 1.5939814085394675, 1.5864712987763248, 1.5864712987763248 ], "candidate": 5.5416603572666645, "control": 8.805536097006513 }, "wall_us": { "speedup": 1.019650667897521, "round_speedups": [ 1.0134438032768074, 1.024405125076266, 1.021134172126407 ], "candidate": 208.3110554450753, "control": 212.40450681500866 } }, "frozen_baseline": { "gpu_us": { "speedup": 1.585005171447266, "round_speedups": [ 1.5864546352120665, 1.5820935978565696, 1.5864712987763248 ], "candidate": 5.555537355430462, "control": 8.80555543852575 }, "wall_us": { "speedup": 1.0252465848191117, "round_speedups": [ 1.0198039290995333, 1.023768099132015, 1.0322068106668958 ], "candidate": 208.26081916958412, "control": 213.51869360524663 } }, "mlx_fast": { "wall_us": { "speedup": 1.0019933142333568, "round_speedups": [ 1.0069407444055412, 0.9898284964842498, 1.0093240093240092 ], "candidate": 211.1949061626564, "control": 211.61588397512287 } }, "mlx_matched": { "wall_us": { "speedup": 1.1095463729374806, "round_speedups": [ 1.119295337182492, 1.102382723455309, 1.1070297223539178 ], "candidate": 210.0846508402258, "control": 233.09866234960953 } } } }, { "name": "float16_1x1024", "dtype": "float16", "batches": 1, "width": 1024, "input_sha256": "2683d33d5488a5a041b96bad34b12812090a3bdd2790e18d2ab72e5cdeabab46", "epsilon": 1e-05, "candidate_layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "elements_per_thread": 4 }, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "frozen_baseline": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "current_control": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "mlx_matched": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "mlx_fast": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002, "max_difference_from_matched_policy": 0.001953125 } }, "validated_before_timing": true, "shaders": { "candidate": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "current_control": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant int& N [[buffer(3)]],\n constant float& eps [[buffer(4)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v1 = v0 * N;\n float _acc_0 = 0.0f;\n const int _ew_end_0 = (N / 1024) * 1024;\n for (int v9 = 0; v9 < _ew_end_0; v9 += 1024) {\n int lane_v10 = static_cast(lid) * 4;\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n half4 v18 = *(device const half4*)(X + _off_v17);\n float4 v19 = float4(v18);\n float4 v20 = v19 * v19;\n float v22 = _acc_0 + (v20.x + v20.y + v20.z + v20.w);\n _acc_0 = v22;\n }\n for (int v9 = _ew_end_0; v9 < N; v9 += 256) {\n int lane_v10 = static_cast(lid);\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n half v18 = v16 ? X[_off_v17] : static_cast(0);\n float v19 = static_cast(v18);\n float v20 = v19 * v19;\n float v22 = _acc_0 + v20;\n _acc_0 = v22;\n }\n threadgroup float shared_reduce_0[8];\n float v23;\n {\n float _simd_val = simd_sum(_acc_0);\n if (slid == 0u) shared_reduce_0[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (lid < 8u) ? shared_reduce_0[lid] : 0.0f;\n float _result = simd_sum(_partial);\n if (lid == 0u) shared_reduce_0[0] = _result;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n v23 = shared_reduce_0[0];\n }\n float cast_v24 = static_cast(N);\n float v24 = v23 / cast_v24;\n float v25 = v24 + eps;\n float v26 = sqrt(v25);\n float v28 = 1.0f / v26;\n const int _ew_end_1 = (N / 1024) * 1024;\n for (int v30 = 0; v30 < _ew_end_1; v30 += 1024) {\n int lane_v31 = static_cast(lid) * 4;\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n half4 v39 = *(device const half4*)(X + _off_v38);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n half4 v46 = *(device const half4*)(W + v32);\n float4 v47 = float4(v39);\n float4 v48 = v47 * v28;\n float4 v49 = float4(v46);\n float4 v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n *(device half4*)(Out + _off_v55) = half4(v50);\n }\n for (int v30 = _ew_end_1; v30 < N; v30 += 256) {\n int lane_v31 = static_cast(lid);\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n half v39 = v37 ? X[_off_v38] : static_cast(0);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n half v46 = v44 ? W[v32] : static_cast(0);\n float v47 = static_cast(v39);\n float v48 = v47 * v28;\n float v49 = static_cast(v46);\n float v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n if (v54) { Out[_off_v55] = v50; }\n }\n}", "source_sha256": "a144da61ff8c1bf3999ad29ca977b4c3ff2631afbcbacba9ed05d825c967d448", "function_name": "mtile_rmsnorm", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3, 4 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 256 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "scalar lanes", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [ { "induction_variable": "v9", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v9", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 }, { "induction_variable": "v30", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v30", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 } ], "allocations": [ { "name": "shared_reduce_0", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [], "layout_conversions": [], "pipelines": [], "register_reductions": [], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "frozen_baseline": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant int& N [[buffer(3)]],\n constant float& eps [[buffer(4)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v1 = v0 * N;\n float _acc_0 = 0.0f;\n const int _ew_end_0 = (N / 1024) * 1024;\n for (int v9 = 0; v9 < _ew_end_0; v9 += 1024) {\n int lane_v10 = static_cast(lid) * 4;\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n half4 v18 = *(device const half4*)(X + _off_v17);\n float4 v19 = float4(v18);\n float4 v20 = v19 * v19;\n float v22 = _acc_0 + (v20.x + v20.y + v20.z + v20.w);\n _acc_0 = v22;\n }\n for (int v9 = _ew_end_0; v9 < N; v9 += 256) {\n int lane_v10 = static_cast(lid);\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n half v18 = v16 ? X[_off_v17] : static_cast(0);\n float v19 = static_cast(v18);\n float v20 = v19 * v19;\n float v22 = _acc_0 + v20;\n _acc_0 = v22;\n }\n threadgroup float shared_reduce_0[8];\n float v23;\n {\n float _simd_val = simd_sum(_acc_0);\n if (slid == 0u) shared_reduce_0[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (lid < 8u) ? shared_reduce_0[lid] : 0.0f;\n float _result = simd_sum(_partial);\n if (lid == 0u) shared_reduce_0[0] = _result;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n v23 = shared_reduce_0[0];\n }\n float cast_v24 = static_cast(N);\n float v24 = v23 / cast_v24;\n float v25 = v24 + eps;\n float v26 = sqrt(v25);\n float v28 = 1.0f / v26;\n const int _ew_end_1 = (N / 1024) * 1024;\n for (int v30 = 0; v30 < _ew_end_1; v30 += 1024) {\n int lane_v31 = static_cast(lid) * 4;\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n half4 v39 = *(device const half4*)(X + _off_v38);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n half4 v46 = *(device const half4*)(W + v32);\n float4 v47 = float4(v39);\n float4 v48 = v47 * v28;\n float4 v49 = float4(v46);\n float4 v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n *(device half4*)(Out + _off_v55) = half4(v50);\n }\n for (int v30 = _ew_end_1; v30 < N; v30 += 256) {\n int lane_v31 = static_cast(lid);\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n half v39 = v37 ? X[_off_v38] : static_cast(0);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n half v46 = v44 ? W[v32] : static_cast(0);\n float v47 = static_cast(v39);\n float v48 = v47 * v28;\n float v49 = static_cast(v46);\n float v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n if (v54) { Out[_off_v55] = v50; }\n }\n}", "source_sha256": "a144da61ff8c1bf3999ad29ca977b4c3ff2631afbcbacba9ed05d825c967d448", "function_name": "mtile_rmsnorm", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3, 4 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 256 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "scalar lanes", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [ { "induction_variable": "v9", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v9", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 }, { "induction_variable": "v30", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v30", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 } ], "allocations": [ { "name": "shared_reduce_0", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [], "layout_conversions": [], "pipelines": [] } } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "current_control": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_baseline": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "rounds": [ { "frozen_baseline": { "pairs": 598, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.792, "control": 198.79149999999998, "speedup": 0.9949922919836629 }, "gpu_us": { "candidate": 1.6249832697212696, "control": 1.8749851733446121, "speedup": 1.153848909266755 } }, "current_control": { "pairs": 612, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.66649999999998, "control": 197.70850000000002, "speedup": 0.9951778483035641 }, "gpu_us": { "candidate": 1.6249832697212696, "control": 1.8749851733446121, "speedup": 1.153848909266755 } }, "mlx_matched": { "pairs": 597, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.125, "control": 204.083, "speedup": 1.009687074829932 } }, "mlx_fast": { "pairs": 611, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.708, "control": 198.125, "speedup": 0.9920734272037174 } } }, { "current_control": { "pairs": 619, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.167, "control": 197.75, "speedup": 1.0029568842656225 }, "gpu_us": { "candidate": 1.625041477382183, "control": 1.8749851733446121, "speedup": 1.1538075793394942 } }, "mlx_matched": { "pairs": 597, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.208, "control": 203.834, "speedup": 1.0181111643890355 } }, "mlx_fast": { "pairs": 611, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.833, "control": 197.042, "speedup": 0.9811236201221911 } }, "frozen_baseline": { "pairs": 614, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.958, "control": 199.333, "speedup": 1.0069459178209519 }, "gpu_us": { "candidate": 1.625041477382183, "control": 1.8749851733446121, "speedup": 1.1538075793394942 } } }, { "mlx_matched": { "pairs": 540, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.91649999999998, "control": 206.167, "speedup": 1.0210507808921014 } }, "mlx_fast": { "pairs": 609, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.458, "control": 199.834, "speedup": 0.9870392871607939 } }, "frozen_baseline": { "pairs": 615, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.417, "control": 198.75, "speedup": 0.9966552500539071 }, "gpu_us": { "candidate": 1.5416881069540977, "control": 1.8749851733446121, "speedup": 1.2161896851166654 } }, "current_control": { "pairs": 612, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.58350000000002, "control": 199.2295, "speedup": 0.9982263062828339 }, "gpu_us": { "candidate": 1.5416881069540977, "control": 1.8749851733446121, "speedup": 1.2161896851166654 } } } ], "summary": { "current_control": { "gpu_us": { "speedup": 1.1742517489156958, "round_speedups": [ 1.153848909266755, 1.1538075793394942, 1.2161896851166654 ], "candidate": 1.596748887175151, "control": 1.8749851733446121 }, "wall_us": { "speedup": 0.998781888142966, "round_speedups": [ 0.9951778483035641, 1.0029568842656225, 0.9982263062828339 ], "candidate": 198.46983158861266, "control": 198.22807313349116 } }, "frozen_baseline": { "gpu_us": { "speedup": 1.1742517489156958, "round_speedups": [ 1.153848909266755, 1.1538075793394942, 1.2161896851166654 ], "candidate": 1.596748887175151, "control": 1.8749851733446121 }, "wall_us": { "speedup": 0.9995172036932036, "round_speedups": [ 0.9949922919836629, 1.0069459178209519, 0.9966552500539071 ], "candidate": 199.0540920904855, "control": 198.95798950997147 } }, "mlx_fast": { "wall_us": { "speedup": 0.9867352941004913, "round_speedups": [ 0.9920734272037174, 0.9811236201221911, 0.9870392871607939 ], "candidate": 200.99649928744506, "control": 198.3303398375662 } }, "mlx_matched": { "wall_us": { "speedup": 1.0162715771325503, "round_speedups": [ 1.009687074829932, 1.0181111643890355, 1.0210507808921014 ], "candidate": 201.41466572815466, "control": 204.6919999971772 } } } }, { "name": "float16_32x1024", "dtype": "float16", "batches": 32, "width": 1024, "input_sha256": "fa99fe5ecc0aae3dd09318ede3a8af87372981bfcb0382b49ef6ac785c03f160", "epsilon": 1e-05, "candidate_layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "elements_per_thread": 4 }, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 }, "frozen_baseline": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 }, "current_control": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 }, "mlx_matched": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 }, "mlx_fast": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002, "max_difference_from_matched_policy": 0.00390625 } }, "validated_before_timing": true, "shaders": { "candidate": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "current_control": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant int& N [[buffer(3)]],\n constant float& eps [[buffer(4)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v1 = v0 * N;\n float _acc_0 = 0.0f;\n const int _ew_end_0 = (N / 1024) * 1024;\n for (int v9 = 0; v9 < _ew_end_0; v9 += 1024) {\n int lane_v10 = static_cast(lid) * 4;\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n half4 v18 = *(device const half4*)(X + _off_v17);\n float4 v19 = float4(v18);\n float4 v20 = v19 * v19;\n float v22 = _acc_0 + (v20.x + v20.y + v20.z + v20.w);\n _acc_0 = v22;\n }\n for (int v9 = _ew_end_0; v9 < N; v9 += 256) {\n int lane_v10 = static_cast(lid);\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n half v18 = v16 ? X[_off_v17] : static_cast(0);\n float v19 = static_cast(v18);\n float v20 = v19 * v19;\n float v22 = _acc_0 + v20;\n _acc_0 = v22;\n }\n threadgroup float shared_reduce_0[8];\n float v23;\n {\n float _simd_val = simd_sum(_acc_0);\n if (slid == 0u) shared_reduce_0[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (lid < 8u) ? shared_reduce_0[lid] : 0.0f;\n float _result = simd_sum(_partial);\n if (lid == 0u) shared_reduce_0[0] = _result;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n v23 = shared_reduce_0[0];\n }\n float cast_v24 = static_cast(N);\n float v24 = v23 / cast_v24;\n float v25 = v24 + eps;\n float v26 = sqrt(v25);\n float v28 = 1.0f / v26;\n const int _ew_end_1 = (N / 1024) * 1024;\n for (int v30 = 0; v30 < _ew_end_1; v30 += 1024) {\n int lane_v31 = static_cast(lid) * 4;\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n half4 v39 = *(device const half4*)(X + _off_v38);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n half4 v46 = *(device const half4*)(W + v32);\n float4 v47 = float4(v39);\n float4 v48 = v47 * v28;\n float4 v49 = float4(v46);\n float4 v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n *(device half4*)(Out + _off_v55) = half4(v50);\n }\n for (int v30 = _ew_end_1; v30 < N; v30 += 256) {\n int lane_v31 = static_cast(lid);\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n half v39 = v37 ? X[_off_v38] : static_cast(0);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n half v46 = v44 ? W[v32] : static_cast(0);\n float v47 = static_cast(v39);\n float v48 = v47 * v28;\n float v49 = static_cast(v46);\n float v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n if (v54) { Out[_off_v55] = v50; }\n }\n}", "source_sha256": "a144da61ff8c1bf3999ad29ca977b4c3ff2631afbcbacba9ed05d825c967d448", "function_name": "mtile_rmsnorm", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3, 4 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 256 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "scalar lanes", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [ { "induction_variable": "v9", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v9", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 }, { "induction_variable": "v30", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v30", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 } ], "allocations": [ { "name": "shared_reduce_0", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [], "layout_conversions": [], "pipelines": [], "register_reductions": [], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "frozen_baseline": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant int& N [[buffer(3)]],\n constant float& eps [[buffer(4)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v1 = v0 * N;\n float _acc_0 = 0.0f;\n const int _ew_end_0 = (N / 1024) * 1024;\n for (int v9 = 0; v9 < _ew_end_0; v9 += 1024) {\n int lane_v10 = static_cast(lid) * 4;\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n half4 v18 = *(device const half4*)(X + _off_v17);\n float4 v19 = float4(v18);\n float4 v20 = v19 * v19;\n float v22 = _acc_0 + (v20.x + v20.y + v20.z + v20.w);\n _acc_0 = v22;\n }\n for (int v9 = _ew_end_0; v9 < N; v9 += 256) {\n int lane_v10 = static_cast(lid);\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n half v18 = v16 ? X[_off_v17] : static_cast(0);\n float v19 = static_cast(v18);\n float v20 = v19 * v19;\n float v22 = _acc_0 + v20;\n _acc_0 = v22;\n }\n threadgroup float shared_reduce_0[8];\n float v23;\n {\n float _simd_val = simd_sum(_acc_0);\n if (slid == 0u) shared_reduce_0[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (lid < 8u) ? shared_reduce_0[lid] : 0.0f;\n float _result = simd_sum(_partial);\n if (lid == 0u) shared_reduce_0[0] = _result;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n v23 = shared_reduce_0[0];\n }\n float cast_v24 = static_cast(N);\n float v24 = v23 / cast_v24;\n float v25 = v24 + eps;\n float v26 = sqrt(v25);\n float v28 = 1.0f / v26;\n const int _ew_end_1 = (N / 1024) * 1024;\n for (int v30 = 0; v30 < _ew_end_1; v30 += 1024) {\n int lane_v31 = static_cast(lid) * 4;\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n half4 v39 = *(device const half4*)(X + _off_v38);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n half4 v46 = *(device const half4*)(W + v32);\n float4 v47 = float4(v39);\n float4 v48 = v47 * v28;\n float4 v49 = float4(v46);\n float4 v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n *(device half4*)(Out + _off_v55) = half4(v50);\n }\n for (int v30 = _ew_end_1; v30 < N; v30 += 256) {\n int lane_v31 = static_cast(lid);\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n half v39 = v37 ? X[_off_v38] : static_cast(0);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n half v46 = v44 ? W[v32] : static_cast(0);\n float v47 = static_cast(v39);\n float v48 = v47 * v28;\n float v49 = static_cast(v46);\n float v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n if (v54) { Out[_off_v55] = v50; }\n }\n}", "source_sha256": "a144da61ff8c1bf3999ad29ca977b4c3ff2631afbcbacba9ed05d825c967d448", "function_name": "mtile_rmsnorm", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3, 4 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 256 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "scalar lanes", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [ { "induction_variable": "v9", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v9", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 }, { "induction_variable": "v30", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v30", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 } ], "allocations": [ { "name": "shared_reduce_0", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [], "layout_conversions": [], "pipelines": [] } } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "current_control": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_baseline": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "rounds": [ { "frozen_baseline": { "pairs": 599, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.042, "control": 197.875, "speedup": 0.9891672748722768 }, "gpu_us": { "candidate": 1.8750433810055256, "control": 2.1249870769679546, "speedup": 1.13330022040791 } }, "current_control": { "pairs": 524, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.3545, "control": 202.0, "speedup": 1.0082129425593136 }, "gpu_us": { "candidate": 1.8750433810055256, "control": 2.1249870769679546, "speedup": 1.13330022040791 } }, "mlx_matched": { "pairs": 589, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.209, "control": 207.666, "speedup": 1.037246077848648 } }, "mlx_fast": { "pairs": 559, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 203.792, "control": 200.625, "speedup": 0.9844596451283661 } } }, { "current_control": { "pairs": 595, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.333, "control": 198.25, "speedup": 0.994566880546623 }, "gpu_us": { "candidate": 1.8750433810055256, "control": 2.1249870769679546, "speedup": 1.13330022040791 } }, "mlx_matched": { "pairs": 578, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 203.458, "control": 206.70850000000002, "speedup": 1.0159762702867423 } }, "mlx_fast": { "pairs": 534, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.688, "control": 203.063, "speedup": 0.992061088095052 } }, "frozen_baseline": { "pairs": 602, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.708, "control": 199.25, "speedup": 1.0027276204279647 }, "gpu_us": { "candidate": 1.8750433810055256, "control": 2.1249870769679546, "speedup": 1.13330022040791 } } }, { "mlx_matched": { "pairs": 577, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.375, "control": 211.625, "speedup": 1.0509000620732465 } }, "mlx_fast": { "pairs": 592, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.08350000000002, "control": 200.22899999999998, "speedup": 0.9957505215495054 } }, "frozen_baseline": { "pairs": 605, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.042, "control": 198.167, "speedup": 1.0006311792448066 }, "gpu_us": { "candidate": 1.8750433810055256, "control": 2.1249870769679546, "speedup": 1.13330022040791 } }, "current_control": { "pairs": 583, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.0, "control": 198.375, "speedup": 0.991875 }, "gpu_us": { "candidate": 1.8750433810055256, "control": 2.1249870769679546, "speedup": 1.13330022040791 } } } ], "summary": { "current_control": { "gpu_us": { "speedup": 1.13330022040791, "round_speedups": [ 1.13330022040791, 1.13330022040791, 1.13330022040791 ], "candidate": 1.8750433810055256, "control": 2.1249870769679546 }, "wall_us": { "speedup": 0.9981927283027123, "round_speedups": [ 1.0082129425593136, 0.994566880546623, 0.991875 ], "candidate": 199.8953845350639, "control": 199.53411926417513 } }, "frozen_baseline": { "gpu_us": { "speedup": 1.13330022040791, "round_speedups": [ 1.13330022040791, 1.13330022040791, 1.13330022040791 ], "candidate": 1.8750433810055256, "control": 2.1249870769679546 }, "wall_us": { "speedup": 0.9974908402360803, "round_speedups": [ 0.9891672748722768, 1.0027276204279647, 1.0006311792448066 ], "candidate": 198.92893056944757, "control": 198.42978610098314 } }, "mlx_fast": { "wall_us": { "speedup": 0.9907459190346456, "round_speedups": [ 0.9844596451283661, 0.992061088095052, 0.9957505215495054 ], "candidate": 203.18204008050338, "control": 201.30177703089268 } }, "mlx_matched": { "wall_us": { "speedup": 1.0346074336230724, "round_speedups": [ 1.037246077848648, 1.0159762702867423, 1.0509000620732465 ], "candidate": 201.6761956216096, "control": 208.6556911749382 } } } }, { "name": "float16_256x1024", "dtype": "float16", "batches": 256, "width": 1024, "input_sha256": "53342c1f866f09f04f991c436154e5a5f8a0df92d7cda7a5a874d5a4f101df4e", "epsilon": 1e-05, "candidate_layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "elements_per_thread": 4 }, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 }, "frozen_baseline": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 }, "current_control": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 }, "mlx_matched": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "mlx_fast": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002, "max_difference_from_matched_policy": 0.00390625 } }, "validated_before_timing": true, "shaders": { "candidate": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "current_control": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant int& N [[buffer(3)]],\n constant float& eps [[buffer(4)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v1 = v0 * N;\n float _acc_0 = 0.0f;\n const int _ew_end_0 = (N / 1024) * 1024;\n for (int v9 = 0; v9 < _ew_end_0; v9 += 1024) {\n int lane_v10 = static_cast(lid) * 4;\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n half4 v18 = *(device const half4*)(X + _off_v17);\n float4 v19 = float4(v18);\n float4 v20 = v19 * v19;\n float v22 = _acc_0 + (v20.x + v20.y + v20.z + v20.w);\n _acc_0 = v22;\n }\n for (int v9 = _ew_end_0; v9 < N; v9 += 256) {\n int lane_v10 = static_cast(lid);\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n half v18 = v16 ? X[_off_v17] : static_cast(0);\n float v19 = static_cast(v18);\n float v20 = v19 * v19;\n float v22 = _acc_0 + v20;\n _acc_0 = v22;\n }\n threadgroup float shared_reduce_0[8];\n float v23;\n {\n float _simd_val = simd_sum(_acc_0);\n if (slid == 0u) shared_reduce_0[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (lid < 8u) ? shared_reduce_0[lid] : 0.0f;\n float _result = simd_sum(_partial);\n if (lid == 0u) shared_reduce_0[0] = _result;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n v23 = shared_reduce_0[0];\n }\n float cast_v24 = static_cast(N);\n float v24 = v23 / cast_v24;\n float v25 = v24 + eps;\n float v26 = sqrt(v25);\n float v28 = 1.0f / v26;\n const int _ew_end_1 = (N / 1024) * 1024;\n for (int v30 = 0; v30 < _ew_end_1; v30 += 1024) {\n int lane_v31 = static_cast(lid) * 4;\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n half4 v39 = *(device const half4*)(X + _off_v38);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n half4 v46 = *(device const half4*)(W + v32);\n float4 v47 = float4(v39);\n float4 v48 = v47 * v28;\n float4 v49 = float4(v46);\n float4 v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n *(device half4*)(Out + _off_v55) = half4(v50);\n }\n for (int v30 = _ew_end_1; v30 < N; v30 += 256) {\n int lane_v31 = static_cast(lid);\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n half v39 = v37 ? X[_off_v38] : static_cast(0);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n half v46 = v44 ? W[v32] : static_cast(0);\n float v47 = static_cast(v39);\n float v48 = v47 * v28;\n float v49 = static_cast(v46);\n float v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n if (v54) { Out[_off_v55] = v50; }\n }\n}", "source_sha256": "a144da61ff8c1bf3999ad29ca977b4c3ff2631afbcbacba9ed05d825c967d448", "function_name": "mtile_rmsnorm", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3, 4 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 256 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "scalar lanes", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [ { "induction_variable": "v9", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v9", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 }, { "induction_variable": "v30", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v30", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 } ], "allocations": [ { "name": "shared_reduce_0", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [], "layout_conversions": [], "pipelines": [], "register_reductions": [], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "frozen_baseline": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant int& N [[buffer(3)]],\n constant float& eps [[buffer(4)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v1 = v0 * N;\n float _acc_0 = 0.0f;\n const int _ew_end_0 = (N / 1024) * 1024;\n for (int v9 = 0; v9 < _ew_end_0; v9 += 1024) {\n int lane_v10 = static_cast(lid) * 4;\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n half4 v18 = *(device const half4*)(X + _off_v17);\n float4 v19 = float4(v18);\n float4 v20 = v19 * v19;\n float v22 = _acc_0 + (v20.x + v20.y + v20.z + v20.w);\n _acc_0 = v22;\n }\n for (int v9 = _ew_end_0; v9 < N; v9 += 256) {\n int lane_v10 = static_cast(lid);\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n half v18 = v16 ? X[_off_v17] : static_cast(0);\n float v19 = static_cast(v18);\n float v20 = v19 * v19;\n float v22 = _acc_0 + v20;\n _acc_0 = v22;\n }\n threadgroup float shared_reduce_0[8];\n float v23;\n {\n float _simd_val = simd_sum(_acc_0);\n if (slid == 0u) shared_reduce_0[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (lid < 8u) ? shared_reduce_0[lid] : 0.0f;\n float _result = simd_sum(_partial);\n if (lid == 0u) shared_reduce_0[0] = _result;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n v23 = shared_reduce_0[0];\n }\n float cast_v24 = static_cast(N);\n float v24 = v23 / cast_v24;\n float v25 = v24 + eps;\n float v26 = sqrt(v25);\n float v28 = 1.0f / v26;\n const int _ew_end_1 = (N / 1024) * 1024;\n for (int v30 = 0; v30 < _ew_end_1; v30 += 1024) {\n int lane_v31 = static_cast(lid) * 4;\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n half4 v39 = *(device const half4*)(X + _off_v38);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n half4 v46 = *(device const half4*)(W + v32);\n float4 v47 = float4(v39);\n float4 v48 = v47 * v28;\n float4 v49 = float4(v46);\n float4 v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n *(device half4*)(Out + _off_v55) = half4(v50);\n }\n for (int v30 = _ew_end_1; v30 < N; v30 += 256) {\n int lane_v31 = static_cast(lid);\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n half v39 = v37 ? X[_off_v38] : static_cast(0);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n half v46 = v44 ? W[v32] : static_cast(0);\n float v47 = static_cast(v39);\n float v48 = v47 * v28;\n float v49 = static_cast(v46);\n float v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n if (v54) { Out[_off_v55] = v50; }\n }\n}", "source_sha256": "a144da61ff8c1bf3999ad29ca977b4c3ff2631afbcbacba9ed05d825c967d448", "function_name": "mtile_rmsnorm", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3, 4 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 256 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "scalar lanes", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [ { "induction_variable": "v9", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v9", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 }, { "induction_variable": "v30", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v30", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 } ], "allocations": [ { "name": "shared_reduce_0", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [], "layout_conversions": [], "pipelines": [] } } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "current_control": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_baseline": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "rounds": [ { "frozen_baseline": { "pairs": 595, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 203.958, "control": 203.834, "speedup": 0.9993920316927996 }, "gpu_us": { "candidate": 4.916684702038765, "control": 5.125009920448065, "speedup": 1.0423710754368518 } }, "current_control": { "pairs": 587, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 205.625, "control": 207.208, "speedup": 1.007698480243161 }, "gpu_us": { "candidate": 4.916684702038765, "control": 5.125009920448065, "speedup": 1.0423710754368518 } }, "mlx_matched": { "pairs": 546, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 209.04149999999998, "control": 232.083, "speedup": 1.1102245247953157 } }, "mlx_fast": { "pairs": 581, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 207.291, "control": 209.041, "speedup": 1.0084422382061933 } } }, { "current_control": { "pairs": 500, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 208.625, "control": 207.27100000000002, "speedup": 0.993509886159377 }, "gpu_us": { "candidate": 4.916684702038765, "control": 5.125009920448065, "speedup": 1.0423710754368518 } }, "mlx_matched": { "pairs": 530, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 208.3955, "control": 232.292, "speedup": 1.1146689827755398 } }, "mlx_fast": { "pairs": 569, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 209.209, "control": 209.417, "speedup": 1.0009942210899148 } }, "frozen_baseline": { "pairs": 584, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.95850000000002, "control": 205.41649999999998, "speedup": 1.0022345987114463 }, "gpu_us": { "candidate": 4.916684702038765, "control": 5.125009920448065, "speedup": 1.0423710754368518 } } }, { "mlx_matched": { "pairs": 553, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 210.0, "control": 229.292, "speedup": 1.0918666666666668 } }, "mlx_fast": { "pairs": 560, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 207.333, "control": 212.27100000000002, "speedup": 1.0238167585478435 } }, "frozen_baseline": { "pairs": 583, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 205.5, "control": 205.917, "speedup": 1.002029197080292 }, "gpu_us": { "candidate": 4.9166264943778515, "control": 5.125009920448065, "speedup": 1.0423834160086187 } }, "current_control": { "pairs": 463, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 221.333, "control": 224.416, "speedup": 1.0139292378452378 }, "gpu_us": { "candidate": 5.583337042480707, "control": 5.62501372769475, "speedup": 1.007464475975021 } } } ], "summary": { "current_control": { "gpu_us": { "speedup": 1.03060318823405, "round_speedups": [ 1.0423710754368518, 1.0423710754368518, 1.007464475975021 ], "candidate": 5.129552993027588, "control": 5.286533668829746 }, "wall_us": { "speedup": 1.0050094554185764, "round_speedups": [ 1.007698480243161, 0.993509886159377, 1.0139292378452378 ], "candidate": 211.75295447577255, "control": 212.81372146097075 } }, "frozen_baseline": { "gpu_us": { "speedup": 1.042375188944541, "round_speedups": [ 1.0423710754368518, 1.0423710754368518, 1.0423834160086187 ], "candidate": 4.916665299408559, "control": 5.125009920448065 }, "wall_us": { "speedup": 1.0012177720679554, "round_speedups": [ 0.9993920316927996, 1.0022345987114463, 1.002029197080292 ], "candidate": 204.80450321616343, "control": 205.05390841957157 } }, "mlx_fast": { "wall_us": { "speedup": 1.011039858703613, "round_speedups": [ 1.0084422382061933, 1.0009942210899148, 1.0238167585478435 ], "candidate": 207.94241365401462, "control": 210.23806851924317 } }, "mlx_matched": { "wall_us": { "speedup": 1.1055425108522734, "round_speedups": [ 1.1102245247953157, 1.1146689827755398, 1.0918666666666668 ], "candidate": 209.14462843156804, "control": 231.21827764750174 } } } }, { "name": "float32_1x1009", "dtype": "float32", "batches": 1, "width": 1009, "input_sha256": "860c5a452325a90578a2d2387dc453c128cc75b81884397cab9fbd0260086958", "epsilon": 1e-05, "candidate_layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "elements_per_thread": 4 }, "correctness": { "candidate": { "passed": true, "max_absolute_error": 4.76837158203125e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_baseline": { "passed": true, "max_absolute_error": 4.76837158203125e-07, "rtol": 3e-05, "atol": 2e-05 }, "current_control": { "passed": true, "max_absolute_error": 4.76837158203125e-07, "rtol": 3e-05, "atol": 2e-05 }, "mlx_matched": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 }, "mlx_fast": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05, "max_difference_from_matched_policy": 0.0 } }, "validated_before_timing": true, "shaders": { "candidate": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "current_control": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant int& N [[buffer(3)]],\n constant float& eps [[buffer(4)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v1 = v0 * N;\n float _acc_0 = 0.0f;\n const int _ew_end_0 = (N / 1024) * 1024;\n for (int v9 = 0; v9 < _ew_end_0; v9 += 1024) {\n int lane_v10 = static_cast(lid) * 4;\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n float4 v18 = *(device const float4*)(X + _off_v17);\n float4 v19 = float4(v18);\n float4 v20 = v19 * v19;\n float v22 = _acc_0 + (v20.x + v20.y + v20.z + v20.w);\n _acc_0 = v22;\n }\n for (int v9 = _ew_end_0; v9 < N; v9 += 256) {\n int lane_v10 = static_cast(lid);\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n float v18 = v16 ? X[_off_v17] : static_cast(0);\n float v19 = static_cast(v18);\n float v20 = v19 * v19;\n float v22 = _acc_0 + v20;\n _acc_0 = v22;\n }\n threadgroup float shared_reduce_0[8];\n float v23;\n {\n float _simd_val = simd_sum(_acc_0);\n if (slid == 0u) shared_reduce_0[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (lid < 8u) ? shared_reduce_0[lid] : 0.0f;\n float _result = simd_sum(_partial);\n if (lid == 0u) shared_reduce_0[0] = _result;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n v23 = shared_reduce_0[0];\n }\n float cast_v24 = static_cast(N);\n float v24 = v23 / cast_v24;\n float v25 = v24 + eps;\n float v26 = sqrt(v25);\n float v28 = 1.0f / v26;\n const int _ew_end_1 = (N / 1024) * 1024;\n for (int v30 = 0; v30 < _ew_end_1; v30 += 1024) {\n int lane_v31 = static_cast(lid) * 4;\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n float4 v39 = *(device const float4*)(X + _off_v38);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n float4 v46 = *(device const float4*)(W + v32);\n float4 v47 = float4(v39);\n float4 v48 = v47 * v28;\n float4 v49 = float4(v46);\n float4 v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n *(device float4*)(Out + _off_v55) = v50;\n }\n for (int v30 = _ew_end_1; v30 < N; v30 += 256) {\n int lane_v31 = static_cast(lid);\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n float v39 = v37 ? X[_off_v38] : static_cast(0);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n float v46 = v44 ? W[v32] : static_cast(0);\n float v47 = static_cast(v39);\n float v48 = v47 * v28;\n float v49 = static_cast(v46);\n float v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n if (v54) { Out[_off_v55] = v50; }\n }\n}", "source_sha256": "c299dc56d7502bee63f4ff70bc00ff24f55197b77b602d0dbea32682813a09b6", "function_name": "mtile_rmsnorm", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3, 4 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 256 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "scalar lanes", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [ { "induction_variable": "v9", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v9", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 }, { "induction_variable": "v30", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v30", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 } ], "allocations": [ { "name": "shared_reduce_0", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [], "layout_conversions": [], "pipelines": [], "register_reductions": [], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "frozen_baseline": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant int& N [[buffer(3)]],\n constant float& eps [[buffer(4)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v1 = v0 * N;\n float _acc_0 = 0.0f;\n const int _ew_end_0 = (N / 1024) * 1024;\n for (int v9 = 0; v9 < _ew_end_0; v9 += 1024) {\n int lane_v10 = static_cast(lid) * 4;\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n float4 v18 = *(device const float4*)(X + _off_v17);\n float4 v19 = float4(v18);\n float4 v20 = v19 * v19;\n float v22 = _acc_0 + (v20.x + v20.y + v20.z + v20.w);\n _acc_0 = v22;\n }\n for (int v9 = _ew_end_0; v9 < N; v9 += 256) {\n int lane_v10 = static_cast(lid);\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n float v18 = v16 ? X[_off_v17] : static_cast(0);\n float v19 = static_cast(v18);\n float v20 = v19 * v19;\n float v22 = _acc_0 + v20;\n _acc_0 = v22;\n }\n threadgroup float shared_reduce_0[8];\n float v23;\n {\n float _simd_val = simd_sum(_acc_0);\n if (slid == 0u) shared_reduce_0[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (lid < 8u) ? shared_reduce_0[lid] : 0.0f;\n float _result = simd_sum(_partial);\n if (lid == 0u) shared_reduce_0[0] = _result;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n v23 = shared_reduce_0[0];\n }\n float cast_v24 = static_cast(N);\n float v24 = v23 / cast_v24;\n float v25 = v24 + eps;\n float v26 = sqrt(v25);\n float v28 = 1.0f / v26;\n const int _ew_end_1 = (N / 1024) * 1024;\n for (int v30 = 0; v30 < _ew_end_1; v30 += 1024) {\n int lane_v31 = static_cast(lid) * 4;\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n float4 v39 = *(device const float4*)(X + _off_v38);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n float4 v46 = *(device const float4*)(W + v32);\n float4 v47 = float4(v39);\n float4 v48 = v47 * v28;\n float4 v49 = float4(v46);\n float4 v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n *(device float4*)(Out + _off_v55) = v50;\n }\n for (int v30 = _ew_end_1; v30 < N; v30 += 256) {\n int lane_v31 = static_cast(lid);\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n float v39 = v37 ? X[_off_v38] : static_cast(0);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n float v46 = v44 ? W[v32] : static_cast(0);\n float v47 = static_cast(v39);\n float v48 = v47 * v28;\n float v49 = static_cast(v46);\n float v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n if (v54) { Out[_off_v55] = v50; }\n }\n}", "source_sha256": "c299dc56d7502bee63f4ff70bc00ff24f55197b77b602d0dbea32682813a09b6", "function_name": "mtile_rmsnorm", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3, 4 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 256 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "scalar lanes", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [ { "induction_variable": "v9", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v9", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 }, { "induction_variable": "v30", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v30", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 } ], "allocations": [ { "name": "shared_reduce_0", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [], "layout_conversions": [], "pipelines": [] } } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "current_control": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_baseline": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "rounds": [ { "frozen_baseline": { "pairs": 615, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.75, "control": 197.375, "speedup": 0.9930817610062893 }, "gpu_us": { "candidate": 1.625041477382183, "control": 2.833374310284853, "speedup": 1.7435704563364138 } }, "current_control": { "pairs": 614, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.625, "control": 198.625, "speedup": 1.0 }, "gpu_us": { "candidate": 1.625041477382183, "control": 2.8333161026239395, "speedup": 1.7435346371516585 } }, "mlx_matched": { "pairs": 610, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.75, "control": 199.27100000000002, "speedup": 0.9926326276463263 } }, "mlx_fast": { "pairs": 614, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.5, "control": 198.708, "speedup": 0.9910623441396509 } } }, { "current_control": { "pairs": 572, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.72899999999998, "control": 201.77100000000002, "speedup": 1.0102238533212504 }, "gpu_us": { "candidate": 1.6666599549353123, "control": 2.8333161026239395, "speedup": 1.6999965075262808 } }, "mlx_matched": { "pairs": 560, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.45850000000002, "control": 205.02100000000002, "speedup": 1.0027511695527453 } }, "mlx_fast": { "pairs": 524, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 206.95850000000002, "control": 208.52100000000002, "speedup": 1.0075498227905595 } }, "frozen_baseline": { "pairs": 587, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.917, "control": 198.25, "speedup": 0.9966468426529658 }, "gpu_us": { "candidate": 1.6666599549353123, "control": 2.8333161026239395, "speedup": 1.6999965075262808 } } }, { "mlx_matched": { "pairs": 603, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.042, "control": 199.125, "speedup": 0.9904646790222938 } }, "mlx_fast": { "pairs": 603, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.333, "control": 200.5, "speedup": 1.0058545248403425 } }, "frozen_baseline": { "pairs": 516, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.70850000000002, "control": 201.9995, "speedup": 0.9965023666989791 }, "gpu_us": { "candidate": 1.6666599549353123, "control": 2.8333161026239395, "speedup": 1.6999965075262808 } }, "current_control": { "pairs": 614, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.75, "control": 197.541, "speedup": 0.9939169811320755 }, "gpu_us": { "candidate": 1.625041477382183, "control": 2.7916976250708103, "speedup": 1.7179239200515797 } } } ], "summary": { "current_control": { "gpu_us": { "speedup": 1.7203923859999646, "round_speedups": [ 1.7435346371516585, 1.6999965075262808, 1.7179239200515797 ], "candidate": 1.6387975290438086, "control": 2.8193747911625238 }, "wall_us": { "speedup": 1.0013577033276528, "round_speedups": [ 1.0, 1.0102238533212504, 0.9939169811320755 ], "candidate": 199.03405525788222, "control": 199.30428445702208 } }, "frozen_baseline": { "gpu_us": { "speedup": 1.7143987970482535, "round_speedups": [ 1.7435704563364138, 1.6999965075262808, 1.6999965075262808 ], "candidate": 1.6526700263223313, "control": 2.83333550504471 }, "wall_us": { "speedup": 0.9954089588446203, "round_speedups": [ 0.9930817610062893, 0.9966468426529658, 0.9965023666989791 ], "candidate": 200.1168536339434, "control": 199.19810892302485 } }, "mlx_fast": { "wall_us": { "speedup": 1.00146142782146, "round_speedups": [ 0.9910623441396509, 1.0075498227905595, 1.0058545248403425 ], "candidate": 202.23622468536277, "control": 202.53177833062497 } }, "mlx_matched": { "wall_us": { "speedup": 0.9952684536371108, "round_speedups": [ 0.9926326276463263, 1.0027511695527453, 0.9904646790222938 ], "candidate": 202.0765134346353, "control": 201.1203790424684 } } } }, { "name": "float32_32x1009", "dtype": "float32", "batches": 32, "width": 1009, "input_sha256": "6b1cd45f16e5a7cc4cf4dcb5e0daa0de047f07f86ca551d45f32adbfa601952f", "epsilon": 1e-05, "candidate_layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "elements_per_thread": 4 }, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_baseline": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "current_control": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "mlx_matched": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "mlx_fast": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05, "max_difference_from_matched_policy": 9.5367431640625e-07 } }, "validated_before_timing": true, "shaders": { "candidate": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "current_control": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant int& N [[buffer(3)]],\n constant float& eps [[buffer(4)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v1 = v0 * N;\n float _acc_0 = 0.0f;\n const int _ew_end_0 = (N / 1024) * 1024;\n for (int v9 = 0; v9 < _ew_end_0; v9 += 1024) {\n int lane_v10 = static_cast(lid) * 4;\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n float4 v18 = *(device const float4*)(X + _off_v17);\n float4 v19 = float4(v18);\n float4 v20 = v19 * v19;\n float v22 = _acc_0 + (v20.x + v20.y + v20.z + v20.w);\n _acc_0 = v22;\n }\n for (int v9 = _ew_end_0; v9 < N; v9 += 256) {\n int lane_v10 = static_cast(lid);\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n float v18 = v16 ? X[_off_v17] : static_cast(0);\n float v19 = static_cast(v18);\n float v20 = v19 * v19;\n float v22 = _acc_0 + v20;\n _acc_0 = v22;\n }\n threadgroup float shared_reduce_0[8];\n float v23;\n {\n float _simd_val = simd_sum(_acc_0);\n if (slid == 0u) shared_reduce_0[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (lid < 8u) ? shared_reduce_0[lid] : 0.0f;\n float _result = simd_sum(_partial);\n if (lid == 0u) shared_reduce_0[0] = _result;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n v23 = shared_reduce_0[0];\n }\n float cast_v24 = static_cast(N);\n float v24 = v23 / cast_v24;\n float v25 = v24 + eps;\n float v26 = sqrt(v25);\n float v28 = 1.0f / v26;\n const int _ew_end_1 = (N / 1024) * 1024;\n for (int v30 = 0; v30 < _ew_end_1; v30 += 1024) {\n int lane_v31 = static_cast(lid) * 4;\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n float4 v39 = *(device const float4*)(X + _off_v38);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n float4 v46 = *(device const float4*)(W + v32);\n float4 v47 = float4(v39);\n float4 v48 = v47 * v28;\n float4 v49 = float4(v46);\n float4 v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n *(device float4*)(Out + _off_v55) = v50;\n }\n for (int v30 = _ew_end_1; v30 < N; v30 += 256) {\n int lane_v31 = static_cast(lid);\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n float v39 = v37 ? X[_off_v38] : static_cast(0);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n float v46 = v44 ? W[v32] : static_cast(0);\n float v47 = static_cast(v39);\n float v48 = v47 * v28;\n float v49 = static_cast(v46);\n float v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n if (v54) { Out[_off_v55] = v50; }\n }\n}", "source_sha256": "c299dc56d7502bee63f4ff70bc00ff24f55197b77b602d0dbea32682813a09b6", "function_name": "mtile_rmsnorm", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3, 4 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 256 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "scalar lanes", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [ { "induction_variable": "v9", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v9", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 }, { "induction_variable": "v30", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v30", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 } ], "allocations": [ { "name": "shared_reduce_0", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [], "layout_conversions": [], "pipelines": [], "register_reductions": [], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "frozen_baseline": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant int& N [[buffer(3)]],\n constant float& eps [[buffer(4)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v1 = v0 * N;\n float _acc_0 = 0.0f;\n const int _ew_end_0 = (N / 1024) * 1024;\n for (int v9 = 0; v9 < _ew_end_0; v9 += 1024) {\n int lane_v10 = static_cast(lid) * 4;\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n float4 v18 = *(device const float4*)(X + _off_v17);\n float4 v19 = float4(v18);\n float4 v20 = v19 * v19;\n float v22 = _acc_0 + (v20.x + v20.y + v20.z + v20.w);\n _acc_0 = v22;\n }\n for (int v9 = _ew_end_0; v9 < N; v9 += 256) {\n int lane_v10 = static_cast(lid);\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n float v18 = v16 ? X[_off_v17] : static_cast(0);\n float v19 = static_cast(v18);\n float v20 = v19 * v19;\n float v22 = _acc_0 + v20;\n _acc_0 = v22;\n }\n threadgroup float shared_reduce_0[8];\n float v23;\n {\n float _simd_val = simd_sum(_acc_0);\n if (slid == 0u) shared_reduce_0[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (lid < 8u) ? shared_reduce_0[lid] : 0.0f;\n float _result = simd_sum(_partial);\n if (lid == 0u) shared_reduce_0[0] = _result;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n v23 = shared_reduce_0[0];\n }\n float cast_v24 = static_cast(N);\n float v24 = v23 / cast_v24;\n float v25 = v24 + eps;\n float v26 = sqrt(v25);\n float v28 = 1.0f / v26;\n const int _ew_end_1 = (N / 1024) * 1024;\n for (int v30 = 0; v30 < _ew_end_1; v30 += 1024) {\n int lane_v31 = static_cast(lid) * 4;\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n float4 v39 = *(device const float4*)(X + _off_v38);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n float4 v46 = *(device const float4*)(W + v32);\n float4 v47 = float4(v39);\n float4 v48 = v47 * v28;\n float4 v49 = float4(v46);\n float4 v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n *(device float4*)(Out + _off_v55) = v50;\n }\n for (int v30 = _ew_end_1; v30 < N; v30 += 256) {\n int lane_v31 = static_cast(lid);\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n float v39 = v37 ? X[_off_v38] : static_cast(0);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n float v46 = v44 ? W[v32] : static_cast(0);\n float v47 = static_cast(v39);\n float v48 = v47 * v28;\n float v49 = static_cast(v46);\n float v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n if (v54) { Out[_off_v55] = v50; }\n }\n}", "source_sha256": "c299dc56d7502bee63f4ff70bc00ff24f55197b77b602d0dbea32682813a09b6", "function_name": "mtile_rmsnorm", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3, 4 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 256 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "scalar lanes", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [ { "induction_variable": "v9", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v9", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 }, { "induction_variable": "v30", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v30", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 } ], "allocations": [ { "name": "shared_reduce_0", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [], "layout_conversions": [], "pipelines": [] } } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "current_control": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_baseline": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "rounds": [ { "frozen_baseline": { "pairs": 605, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.542, "control": 198.417, "speedup": 0.9993704102910216 }, "gpu_us": { "candidate": 2.41666566580534, "control": 3.0833762139081955, "speedup": 1.275880341056891 } }, "current_control": { "pairs": 610, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.54149999999998, "control": 198.14600000000002, "speedup": 0.9980079731441539 }, "gpu_us": { "candidate": 2.41666566580534, "control": 3.1249946914613247, "speedup": 1.2931017871766464 } }, "mlx_matched": { "pairs": 591, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.792, "control": 209.541, "speedup": 1.03328040553868 } }, "mlx_fast": { "pairs": 611, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.084, "control": 197.667, "speedup": 0.9781427525187546 } } }, { "current_control": { "pairs": 613, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.458, "control": 197.292, "speedup": 0.9891405709472672 }, "gpu_us": { "candidate": 2.41666566580534, "control": 3.0833762139081955, "speedup": 1.275880341056891 } }, "mlx_matched": { "pairs": 595, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.917, "control": 206.959, "speedup": 1.019919474464929 } }, "mlx_fast": { "pairs": 558, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.70850000000002, "control": 202.8545, "speedup": 1.0056814660760454 } }, "frozen_baseline": { "pairs": 482, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 208.27100000000002, "control": 207.5, "speedup": 0.9962980923892428 }, "gpu_us": { "candidate": 2.749962732195854, "control": 3.4999684430658817, "speedup": 1.272733045466091 } } }, { "mlx_matched": { "pairs": 473, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 216.917, "control": 238.166, "speedup": 1.0979591272237768 } }, "mlx_fast": { "pairs": 527, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 208.666, "control": 207.25, "speedup": 0.9932140358275905 } }, "frozen_baseline": { "pairs": 582, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.792, "control": 201.667, "speedup": 1.014462352609763 }, "gpu_us": { "candidate": 2.41666566580534, "control": 3.0833762139081955, "speedup": 1.275880341056891 } }, "current_control": { "pairs": 601, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.375, "control": 201.0, "speedup": 1.0081504702194357 }, "gpu_us": { "candidate": 2.41666566580534, "control": 3.0833762139081955, "speedup": 1.275880341056891 } } } ], "summary": { "current_control": { "gpu_us": { "speedup": 1.2815951872840667, "round_speedups": [ 1.2931017871766464, 1.275880341056891, 1.275880341056891 ], "candidate": 2.41666566580534, "control": 3.0971870865707682 }, "wall_us": { "speedup": 0.9984028095039119, "round_speedups": [ 0.9980079731441539, 0.9891405709472672, 1.0081504702194357 ], "candidate": 199.12440282398984, "control": 198.80636322026027 } }, "frozen_baseline": { "gpu_us": { "speedup": 1.2748303787163788, "round_speedups": [ 1.275880341056891, 1.272733045466091, 1.275880341056891 ], "candidate": 2.5230158804669958, "control": 3.2164172904031787 }, "wall_us": { "speedup": 1.0033456528037663, "round_speedups": [ 0.9993704102910216, 0.9962980923892428, 1.014462352609763 ], "candidate": 201.8180625239544, "control": 202.4932756906884 } }, "mlx_fast": { "wall_us": { "speedup": 0.9922821494123328, "round_speedups": [ 0.9781427525187546, 1.0056814660760454, 0.9932140358275905 ], "candidate": 204.1280123684055, "control": 202.5525828681886 } }, "mlx_matched": { "wall_us": { "speedup": 1.0498407284029017, "round_speedups": [ 1.03328040553868, 1.019919474464929, 1.0979591272237768 ], "candidate": 207.43766422821244, "control": 217.77650851154283 } } } }, { "name": "float32_256x1009", "dtype": "float32", "batches": 256, "width": 1009, "input_sha256": "0551977199314ba641c1f1aa1b38f2bb6e9d365a3e72d53d8169010513d127b9", "epsilon": 1e-05, "candidate_layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "elements_per_thread": 4 }, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_baseline": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "current_control": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "mlx_matched": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "mlx_fast": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05, "max_difference_from_matched_policy": 9.5367431640625e-07 } }, "validated_before_timing": true, "shaders": { "candidate": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "current_control": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant int& N [[buffer(3)]],\n constant float& eps [[buffer(4)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v1 = v0 * N;\n float _acc_0 = 0.0f;\n const int _ew_end_0 = (N / 1024) * 1024;\n for (int v9 = 0; v9 < _ew_end_0; v9 += 1024) {\n int lane_v10 = static_cast(lid) * 4;\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n float4 v18 = *(device const float4*)(X + _off_v17);\n float4 v19 = float4(v18);\n float4 v20 = v19 * v19;\n float v22 = _acc_0 + (v20.x + v20.y + v20.z + v20.w);\n _acc_0 = v22;\n }\n for (int v9 = _ew_end_0; v9 < N; v9 += 256) {\n int lane_v10 = static_cast(lid);\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n float v18 = v16 ? X[_off_v17] : static_cast(0);\n float v19 = static_cast(v18);\n float v20 = v19 * v19;\n float v22 = _acc_0 + v20;\n _acc_0 = v22;\n }\n threadgroup float shared_reduce_0[8];\n float v23;\n {\n float _simd_val = simd_sum(_acc_0);\n if (slid == 0u) shared_reduce_0[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (lid < 8u) ? shared_reduce_0[lid] : 0.0f;\n float _result = simd_sum(_partial);\n if (lid == 0u) shared_reduce_0[0] = _result;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n v23 = shared_reduce_0[0];\n }\n float cast_v24 = static_cast(N);\n float v24 = v23 / cast_v24;\n float v25 = v24 + eps;\n float v26 = sqrt(v25);\n float v28 = 1.0f / v26;\n const int _ew_end_1 = (N / 1024) * 1024;\n for (int v30 = 0; v30 < _ew_end_1; v30 += 1024) {\n int lane_v31 = static_cast(lid) * 4;\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n float4 v39 = *(device const float4*)(X + _off_v38);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n float4 v46 = *(device const float4*)(W + v32);\n float4 v47 = float4(v39);\n float4 v48 = v47 * v28;\n float4 v49 = float4(v46);\n float4 v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n *(device float4*)(Out + _off_v55) = v50;\n }\n for (int v30 = _ew_end_1; v30 < N; v30 += 256) {\n int lane_v31 = static_cast(lid);\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n float v39 = v37 ? X[_off_v38] : static_cast(0);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n float v46 = v44 ? W[v32] : static_cast(0);\n float v47 = static_cast(v39);\n float v48 = v47 * v28;\n float v49 = static_cast(v46);\n float v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n if (v54) { Out[_off_v55] = v50; }\n }\n}", "source_sha256": "c299dc56d7502bee63f4ff70bc00ff24f55197b77b602d0dbea32682813a09b6", "function_name": "mtile_rmsnorm", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3, 4 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 256 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "scalar lanes", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [ { "induction_variable": "v9", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v9", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 }, { "induction_variable": "v30", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v30", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 } ], "allocations": [ { "name": "shared_reduce_0", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [], "layout_conversions": [], "pipelines": [], "register_reductions": [], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "frozen_baseline": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant int& N [[buffer(3)]],\n constant float& eps [[buffer(4)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v1 = v0 * N;\n float _acc_0 = 0.0f;\n const int _ew_end_0 = (N / 1024) * 1024;\n for (int v9 = 0; v9 < _ew_end_0; v9 += 1024) {\n int lane_v10 = static_cast(lid) * 4;\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n float4 v18 = *(device const float4*)(X + _off_v17);\n float4 v19 = float4(v18);\n float4 v20 = v19 * v19;\n float v22 = _acc_0 + (v20.x + v20.y + v20.z + v20.w);\n _acc_0 = v22;\n }\n for (int v9 = _ew_end_0; v9 < N; v9 += 256) {\n int lane_v10 = static_cast(lid);\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n float v18 = v16 ? X[_off_v17] : static_cast(0);\n float v19 = static_cast(v18);\n float v20 = v19 * v19;\n float v22 = _acc_0 + v20;\n _acc_0 = v22;\n }\n threadgroup float shared_reduce_0[8];\n float v23;\n {\n float _simd_val = simd_sum(_acc_0);\n if (slid == 0u) shared_reduce_0[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (lid < 8u) ? shared_reduce_0[lid] : 0.0f;\n float _result = simd_sum(_partial);\n if (lid == 0u) shared_reduce_0[0] = _result;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n v23 = shared_reduce_0[0];\n }\n float cast_v24 = static_cast(N);\n float v24 = v23 / cast_v24;\n float v25 = v24 + eps;\n float v26 = sqrt(v25);\n float v28 = 1.0f / v26;\n const int _ew_end_1 = (N / 1024) * 1024;\n for (int v30 = 0; v30 < _ew_end_1; v30 += 1024) {\n int lane_v31 = static_cast(lid) * 4;\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n float4 v39 = *(device const float4*)(X + _off_v38);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n float4 v46 = *(device const float4*)(W + v32);\n float4 v47 = float4(v39);\n float4 v48 = v47 * v28;\n float4 v49 = float4(v46);\n float4 v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n *(device float4*)(Out + _off_v55) = v50;\n }\n for (int v30 = _ew_end_1; v30 < N; v30 += 256) {\n int lane_v31 = static_cast(lid);\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n float v39 = v37 ? X[_off_v38] : static_cast(0);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n float v46 = v44 ? W[v32] : static_cast(0);\n float v47 = static_cast(v39);\n float v48 = v47 * v28;\n float v49 = static_cast(v46);\n float v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n if (v54) { Out[_off_v55] = v50; }\n }\n}", "source_sha256": "c299dc56d7502bee63f4ff70bc00ff24f55197b77b602d0dbea32682813a09b6", "function_name": "mtile_rmsnorm", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3, 4 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 256 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "scalar lanes", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [ { "induction_variable": "v9", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v9", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 }, { "induction_variable": "v30", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v30", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 } ], "allocations": [ { "name": "shared_reduce_0", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [], "layout_conversions": [], "pipelines": [] } } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "current_control": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_baseline": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "rounds": [ { "frozen_baseline": { "pairs": 561, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 218.041, "control": 219.625, "speedup": 1.0072646887511982 }, "gpu_us": { "candidate": 8.375034667551517, "control": 10.750023648142815, "speedup": 1.283579599949959 } }, "current_control": { "pairs": 561, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 217.792, "control": 219.292, "speedup": 1.0068873053188363 }, "gpu_us": { "candidate": 8.374976459890604, "control": 10.750023648142815, "speedup": 1.2835885210694948 } }, "mlx_matched": { "pairs": 542, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 218.667, "control": 228.4795, "speedup": 1.044874169399132 } }, "mlx_fast": { "pairs": 558, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 216.833, "control": 217.8125, "speedup": 1.0045173013332842 } } }, { "current_control": { "pairs": 566, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 217.22899999999998, "control": 219.64600000000002, "speedup": 1.0111265070501638 }, "gpu_us": { "candidate": 8.374976459890604, "control": 10.750023648142815, "speedup": 1.2835885210694948 } }, "mlx_matched": { "pairs": 525, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 218.041, "control": 232.959, "speedup": 1.0684183249939232 } }, "mlx_fast": { "pairs": 527, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 221.417, "control": 221.959, "speedup": 1.0024478698564248 } }, "frozen_baseline": { "pairs": 492, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 220.3955, "control": 222.9375, "speedup": 1.011533810808297 }, "gpu_us": { "candidate": 8.375034667551517, "control": 10.791642125695944, "speedup": 1.2885489498338916 } } }, { "mlx_matched": { "pairs": 528, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 220.33350000000002, "control": 232.5205, "speedup": 1.0553116071773017 } }, "mlx_fast": { "pairs": 522, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 222.625, "control": 221.667, "speedup": 0.9956967995508141 } }, "frozen_baseline": { "pairs": 568, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 217.1045, "control": 219.063, "speedup": 1.0090210014071563 }, "gpu_us": { "candidate": 8.374976459890604, "control": 10.750023648142815, "speedup": 1.2835885210694948 } }, "current_control": { "pairs": 562, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 218.1455, "control": 220.3125, "speedup": 1.0099337368866192 }, "gpu_us": { "candidate": 8.374976459890604, "control": 10.750023648142815, "speedup": 1.2835885210694948 } } } ], "summary": { "current_control": { "gpu_us": { "speedup": 1.2835885210694948, "round_speedups": [ 1.2835885210694948, 1.2835885210694948, 1.2835885210694948 ], "candidate": 8.374976459890606, "control": 10.750023648142815 }, "wall_us": { "speedup": 1.009314270548287, "round_speedups": [ 1.0068873053188363, 1.0111265070501638, 1.0099337368866192 ], "candidate": 217.7218394639278, "control": 219.74975958096562 } }, "frozen_baseline": { "gpu_us": { "speedup": 1.285236894392929, "round_speedups": [ 1.283579599949959, 1.2885489498338916, 1.2835885210694948 ], "candidate": 8.375015264952932, "control": 10.763878609621475 }, "wall_us": { "speedup": 1.0092716467813878, "round_speedups": [ 1.0072646887511982, 1.011533810808297, 1.0090210014071563 ], "candidate": 218.50928928687594, "control": 220.53523023559617 } }, "mlx_fast": { "wall_us": { "speedup": 1.0008802277699773, "round_speedups": [ 1.0045173013332842, 1.0024478698564248, 0.9956967995508141 ], "candidate": 220.2774757421781, "control": 220.47137009342663 } }, "mlx_matched": { "wall_us": { "speedup": 1.0561574788507555, "round_speedups": [ 1.044874169399132, 1.0684183249939232, 1.0553116071773017 ], "candidate": 219.01169938947112, "control": 231.31084426600333 } } } }, { "name": "float32_1x1024", "dtype": "float32", "batches": 1, "width": 1024, "input_sha256": "b8cfb574853a3e5848ec61834c2c552b049faa07bf8f4ce7db9e0ef2922ecbc9", "epsilon": 1e-05, "candidate_layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "elements_per_thread": 4 }, "correctness": { "candidate": { "passed": true, "max_absolute_error": 4.76837158203125e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_baseline": { "passed": true, "max_absolute_error": 4.76837158203125e-07, "rtol": 3e-05, "atol": 2e-05 }, "current_control": { "passed": true, "max_absolute_error": 4.76837158203125e-07, "rtol": 3e-05, "atol": 2e-05 }, "mlx_matched": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 }, "mlx_fast": { "passed": true, "max_absolute_error": 4.76837158203125e-07, "rtol": 3e-05, "atol": 2e-05, "max_difference_from_matched_policy": 4.76837158203125e-07 } }, "validated_before_timing": true, "shaders": { "candidate": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "current_control": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant int& N [[buffer(3)]],\n constant float& eps [[buffer(4)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v1 = v0 * N;\n float _acc_0 = 0.0f;\n const int _ew_end_0 = (N / 1024) * 1024;\n for (int v9 = 0; v9 < _ew_end_0; v9 += 1024) {\n int lane_v10 = static_cast(lid) * 4;\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n float4 v18 = *(device const float4*)(X + _off_v17);\n float4 v19 = float4(v18);\n float4 v20 = v19 * v19;\n float v22 = _acc_0 + (v20.x + v20.y + v20.z + v20.w);\n _acc_0 = v22;\n }\n for (int v9 = _ew_end_0; v9 < N; v9 += 256) {\n int lane_v10 = static_cast(lid);\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n float v18 = v16 ? X[_off_v17] : static_cast(0);\n float v19 = static_cast(v18);\n float v20 = v19 * v19;\n float v22 = _acc_0 + v20;\n _acc_0 = v22;\n }\n threadgroup float shared_reduce_0[8];\n float v23;\n {\n float _simd_val = simd_sum(_acc_0);\n if (slid == 0u) shared_reduce_0[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (lid < 8u) ? shared_reduce_0[lid] : 0.0f;\n float _result = simd_sum(_partial);\n if (lid == 0u) shared_reduce_0[0] = _result;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n v23 = shared_reduce_0[0];\n }\n float cast_v24 = static_cast(N);\n float v24 = v23 / cast_v24;\n float v25 = v24 + eps;\n float v26 = sqrt(v25);\n float v28 = 1.0f / v26;\n const int _ew_end_1 = (N / 1024) * 1024;\n for (int v30 = 0; v30 < _ew_end_1; v30 += 1024) {\n int lane_v31 = static_cast(lid) * 4;\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n float4 v39 = *(device const float4*)(X + _off_v38);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n float4 v46 = *(device const float4*)(W + v32);\n float4 v47 = float4(v39);\n float4 v48 = v47 * v28;\n float4 v49 = float4(v46);\n float4 v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n *(device float4*)(Out + _off_v55) = v50;\n }\n for (int v30 = _ew_end_1; v30 < N; v30 += 256) {\n int lane_v31 = static_cast(lid);\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n float v39 = v37 ? X[_off_v38] : static_cast(0);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n float v46 = v44 ? W[v32] : static_cast(0);\n float v47 = static_cast(v39);\n float v48 = v47 * v28;\n float v49 = static_cast(v46);\n float v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n if (v54) { Out[_off_v55] = v50; }\n }\n}", "source_sha256": "c299dc56d7502bee63f4ff70bc00ff24f55197b77b602d0dbea32682813a09b6", "function_name": "mtile_rmsnorm", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3, 4 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 256 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "scalar lanes", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [ { "induction_variable": "v9", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v9", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 }, { "induction_variable": "v30", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v30", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 } ], "allocations": [ { "name": "shared_reduce_0", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [], "layout_conversions": [], "pipelines": [], "register_reductions": [], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "frozen_baseline": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant int& N [[buffer(3)]],\n constant float& eps [[buffer(4)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v1 = v0 * N;\n float _acc_0 = 0.0f;\n const int _ew_end_0 = (N / 1024) * 1024;\n for (int v9 = 0; v9 < _ew_end_0; v9 += 1024) {\n int lane_v10 = static_cast(lid) * 4;\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n float4 v18 = *(device const float4*)(X + _off_v17);\n float4 v19 = float4(v18);\n float4 v20 = v19 * v19;\n float v22 = _acc_0 + (v20.x + v20.y + v20.z + v20.w);\n _acc_0 = v22;\n }\n for (int v9 = _ew_end_0; v9 < N; v9 += 256) {\n int lane_v10 = static_cast(lid);\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n float v18 = v16 ? X[_off_v17] : static_cast(0);\n float v19 = static_cast(v18);\n float v20 = v19 * v19;\n float v22 = _acc_0 + v20;\n _acc_0 = v22;\n }\n threadgroup float shared_reduce_0[8];\n float v23;\n {\n float _simd_val = simd_sum(_acc_0);\n if (slid == 0u) shared_reduce_0[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (lid < 8u) ? shared_reduce_0[lid] : 0.0f;\n float _result = simd_sum(_partial);\n if (lid == 0u) shared_reduce_0[0] = _result;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n v23 = shared_reduce_0[0];\n }\n float cast_v24 = static_cast(N);\n float v24 = v23 / cast_v24;\n float v25 = v24 + eps;\n float v26 = sqrt(v25);\n float v28 = 1.0f / v26;\n const int _ew_end_1 = (N / 1024) * 1024;\n for (int v30 = 0; v30 < _ew_end_1; v30 += 1024) {\n int lane_v31 = static_cast(lid) * 4;\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n float4 v39 = *(device const float4*)(X + _off_v38);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n float4 v46 = *(device const float4*)(W + v32);\n float4 v47 = float4(v39);\n float4 v48 = v47 * v28;\n float4 v49 = float4(v46);\n float4 v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n *(device float4*)(Out + _off_v55) = v50;\n }\n for (int v30 = _ew_end_1; v30 < N; v30 += 256) {\n int lane_v31 = static_cast(lid);\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n float v39 = v37 ? X[_off_v38] : static_cast(0);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n float v46 = v44 ? W[v32] : static_cast(0);\n float v47 = static_cast(v39);\n float v48 = v47 * v28;\n float v49 = static_cast(v46);\n float v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n if (v54) { Out[_off_v55] = v50; }\n }\n}", "source_sha256": "c299dc56d7502bee63f4ff70bc00ff24f55197b77b602d0dbea32682813a09b6", "function_name": "mtile_rmsnorm", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3, 4 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 256 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "scalar lanes", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [ { "induction_variable": "v9", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v9", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 }, { "induction_variable": "v30", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v30", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 } ], "allocations": [ { "name": "shared_reduce_0", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [], "layout_conversions": [], "pipelines": [] } } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "current_control": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_baseline": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "rounds": [ { "frozen_baseline": { "pairs": 439, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 295.375, "control": 298.208, "speedup": 1.0095911976301313 }, "gpu_us": { "candidate": 6.958318408578634, "control": 8.000002708286047, "speedup": 1.1497034539872681 } }, "current_control": { "pairs": 437, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 299.875, "control": 299.29200000000003, "speedup": 0.9980558566069196 }, "gpu_us": { "candidate": 6.958376616239548, "control": 8.000002708286047, "speedup": 1.1496938365790002 } }, "mlx_matched": { "pairs": 485, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 248.084, "control": 259.5, "speedup": 1.0460166717724642 } }, "mlx_fast": { "pairs": 616, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.1875, "control": 198.02100000000002, "speedup": 0.9842609506057782 } } }, { "current_control": { "pairs": 572, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.9375, "control": 198.54149999999998, "speedup": 1.0030514682664982 }, "gpu_us": { "candidate": 1.6666599549353123, "control": 1.8750433810055256, "speedup": 1.1250305591450425 } }, "mlx_matched": { "pairs": 596, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.6255, "control": 200.14600000000002, "speedup": 0.9926621384695885 } }, "mlx_fast": { "pairs": 568, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 205.125, "control": 203.54149999999998, "speedup": 0.9922803168799512 } }, "frozen_baseline": { "pairs": 616, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.958, "control": 197.1875, "speedup": 0.9961077602319685 }, "gpu_us": { "candidate": 1.6249832697212696, "control": 1.8750433810055256, "speedup": 1.1538847297345702 } } }, { "mlx_matched": { "pairs": 591, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.166, "control": 202.375, "speedup": 1.0110358402525903 } }, "mlx_fast": { "pairs": 611, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.833, "control": 196.792, "speedup": 0.9750239059024045 } }, "frozen_baseline": { "pairs": 617, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.792, "control": 198.625, "speedup": 1.0042114949037373 }, "gpu_us": { "candidate": 1.6249832697212696, "control": 1.8750433810055256, "speedup": 1.1538847297345702 } }, "current_control": { "pairs": 610, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.08350000000002, "control": 198.4375, "speedup": 1.001787125126525 }, "gpu_us": { "candidate": 1.6249832697212696, "control": 1.8750433810055256, "speedup": 1.1538847297345702 } } } ], "summary": { "current_control": { "gpu_us": { "speedup": 1.1427984679767245, "round_speedups": [ 1.1496938365790002, 1.1250305591450425, 1.1538847297345702 ], "candidate": 2.661141341218416, "control": 3.0411482478139322 }, "wall_us": { "speedup": 1.0009625684427317, "round_speedups": [ 0.9980558566069196, 1.0030514682664982, 1.001787125126525 ], "candidate": 227.3904464049198, "control": 227.60932527280772 } }, "frozen_baseline": { "gpu_us": { "speedup": 1.1524892842565055, "round_speedups": [ 1.1497034539872681, 1.1538847297345702, 1.1538847297345702 ], "candidate": 2.6387648799492647, "control": 3.0411482478139322 }, "wall_us": { "speedup": 1.0032881646018637, "round_speedups": [ 1.0095911976301313, 0.9961077602319685, 1.0042114949037373 ], "candidate": 226.14405295087982, "control": 226.8876518207149 } }, "mlx_fast": { "wall_us": { "speedup": 0.9838297823575011, "round_speedups": [ 0.9842609506057782, 0.9922803168799512, 0.9750239059024045 ], "candidate": 202.70785956726843, "control": 199.4300293602207 } }, "mlx_matched": { "wall_us": { "speedup": 1.0163318561759274, "round_speedups": [ 1.0460166717724642, 0.9926621384695885, 1.0110358402525903 ], "candidate": 215.53187541372287, "control": 219.05191100430778 } } } }, { "name": "float32_32x1024", "dtype": "float32", "batches": 32, "width": 1024, "input_sha256": "499a25f7fd35c55afd4b7a3976c93143922f55c10bc7606063d0e319074555b6", "epsilon": 1e-05, "candidate_layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "elements_per_thread": 4 }, "correctness": { "candidate": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_baseline": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "current_control": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "mlx_matched": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "mlx_fast": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05, "max_difference_from_matched_policy": 7.152557373046875e-07 } }, "validated_before_timing": true, "shaders": { "candidate": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "current_control": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant int& N [[buffer(3)]],\n constant float& eps [[buffer(4)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v1 = v0 * N;\n float _acc_0 = 0.0f;\n const int _ew_end_0 = (N / 1024) * 1024;\n for (int v9 = 0; v9 < _ew_end_0; v9 += 1024) {\n int lane_v10 = static_cast(lid) * 4;\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n float4 v18 = *(device const float4*)(X + _off_v17);\n float4 v19 = float4(v18);\n float4 v20 = v19 * v19;\n float v22 = _acc_0 + (v20.x + v20.y + v20.z + v20.w);\n _acc_0 = v22;\n }\n for (int v9 = _ew_end_0; v9 < N; v9 += 256) {\n int lane_v10 = static_cast(lid);\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n float v18 = v16 ? X[_off_v17] : static_cast(0);\n float v19 = static_cast(v18);\n float v20 = v19 * v19;\n float v22 = _acc_0 + v20;\n _acc_0 = v22;\n }\n threadgroup float shared_reduce_0[8];\n float v23;\n {\n float _simd_val = simd_sum(_acc_0);\n if (slid == 0u) shared_reduce_0[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (lid < 8u) ? shared_reduce_0[lid] : 0.0f;\n float _result = simd_sum(_partial);\n if (lid == 0u) shared_reduce_0[0] = _result;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n v23 = shared_reduce_0[0];\n }\n float cast_v24 = static_cast(N);\n float v24 = v23 / cast_v24;\n float v25 = v24 + eps;\n float v26 = sqrt(v25);\n float v28 = 1.0f / v26;\n const int _ew_end_1 = (N / 1024) * 1024;\n for (int v30 = 0; v30 < _ew_end_1; v30 += 1024) {\n int lane_v31 = static_cast(lid) * 4;\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n float4 v39 = *(device const float4*)(X + _off_v38);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n float4 v46 = *(device const float4*)(W + v32);\n float4 v47 = float4(v39);\n float4 v48 = v47 * v28;\n float4 v49 = float4(v46);\n float4 v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n *(device float4*)(Out + _off_v55) = v50;\n }\n for (int v30 = _ew_end_1; v30 < N; v30 += 256) {\n int lane_v31 = static_cast(lid);\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n float v39 = v37 ? X[_off_v38] : static_cast(0);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n float v46 = v44 ? W[v32] : static_cast(0);\n float v47 = static_cast(v39);\n float v48 = v47 * v28;\n float v49 = static_cast(v46);\n float v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n if (v54) { Out[_off_v55] = v50; }\n }\n}", "source_sha256": "c299dc56d7502bee63f4ff70bc00ff24f55197b77b602d0dbea32682813a09b6", "function_name": "mtile_rmsnorm", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3, 4 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 256 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "scalar lanes", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [ { "induction_variable": "v9", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v9", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 }, { "induction_variable": "v30", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v30", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 } ], "allocations": [ { "name": "shared_reduce_0", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [], "layout_conversions": [], "pipelines": [], "register_reductions": [], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "frozen_baseline": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant int& N [[buffer(3)]],\n constant float& eps [[buffer(4)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v1 = v0 * N;\n float _acc_0 = 0.0f;\n const int _ew_end_0 = (N / 1024) * 1024;\n for (int v9 = 0; v9 < _ew_end_0; v9 += 1024) {\n int lane_v10 = static_cast(lid) * 4;\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n float4 v18 = *(device const float4*)(X + _off_v17);\n float4 v19 = float4(v18);\n float4 v20 = v19 * v19;\n float v22 = _acc_0 + (v20.x + v20.y + v20.z + v20.w);\n _acc_0 = v22;\n }\n for (int v9 = _ew_end_0; v9 < N; v9 += 256) {\n int lane_v10 = static_cast(lid);\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n float v18 = v16 ? X[_off_v17] : static_cast(0);\n float v19 = static_cast(v18);\n float v20 = v19 * v19;\n float v22 = _acc_0 + v20;\n _acc_0 = v22;\n }\n threadgroup float shared_reduce_0[8];\n float v23;\n {\n float _simd_val = simd_sum(_acc_0);\n if (slid == 0u) shared_reduce_0[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (lid < 8u) ? shared_reduce_0[lid] : 0.0f;\n float _result = simd_sum(_partial);\n if (lid == 0u) shared_reduce_0[0] = _result;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n v23 = shared_reduce_0[0];\n }\n float cast_v24 = static_cast(N);\n float v24 = v23 / cast_v24;\n float v25 = v24 + eps;\n float v26 = sqrt(v25);\n float v28 = 1.0f / v26;\n const int _ew_end_1 = (N / 1024) * 1024;\n for (int v30 = 0; v30 < _ew_end_1; v30 += 1024) {\n int lane_v31 = static_cast(lid) * 4;\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n float4 v39 = *(device const float4*)(X + _off_v38);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n float4 v46 = *(device const float4*)(W + v32);\n float4 v47 = float4(v39);\n float4 v48 = v47 * v28;\n float4 v49 = float4(v46);\n float4 v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n *(device float4*)(Out + _off_v55) = v50;\n }\n for (int v30 = _ew_end_1; v30 < N; v30 += 256) {\n int lane_v31 = static_cast(lid);\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n float v39 = v37 ? X[_off_v38] : static_cast(0);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n float v46 = v44 ? W[v32] : static_cast(0);\n float v47 = static_cast(v39);\n float v48 = v47 * v28;\n float v49 = static_cast(v46);\n float v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n if (v54) { Out[_off_v55] = v50; }\n }\n}", "source_sha256": "c299dc56d7502bee63f4ff70bc00ff24f55197b77b602d0dbea32682813a09b6", "function_name": "mtile_rmsnorm", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3, 4 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 256 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "scalar lanes", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [ { "induction_variable": "v9", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v9", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 }, { "induction_variable": "v30", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v30", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 } ], "allocations": [ { "name": "shared_reduce_0", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [], "layout_conversions": [], "pipelines": [] } } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "current_control": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_baseline": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "rounds": [ { "frozen_baseline": { "pairs": 611, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.291, "control": 199.666, "speedup": 1.0018816705220004 }, "gpu_us": { "candidate": 2.333370503038168, "control": 2.500019036233425, "speedup": 1.0714196622346397 } }, "current_control": { "pairs": 614, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.6455, "control": 199.52100000000002, "speedup": 0.9943955882389588 }, "gpu_us": { "candidate": 2.333370503038168, "control": 2.500019036233425, "speedup": 1.0714196622346397 } }, "mlx_matched": { "pairs": 595, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.917, "control": 206.375, "speedup": 1.0220783787397791 } }, "mlx_fast": { "pairs": 539, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 203.334, "control": 205.666, "speedup": 1.0114688148563447 } } }, { "current_control": { "pairs": 611, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.834, "control": 199.208, "speedup": 0.9968673999419518 }, "gpu_us": { "candidate": 2.3333122953772545, "control": 2.500019036233425, "speedup": 1.071446390260939 } }, "mlx_matched": { "pairs": 513, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 209.625, "control": 221.375, "speedup": 1.0560524746571258 } }, "mlx_fast": { "pairs": 579, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.125, "control": 199.084, "speedup": 0.975304347826087 } }, "frozen_baseline": { "pairs": 615, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.625, "control": 198.583, "speedup": 0.994780212899186 }, "gpu_us": { "candidate": 2.333370503038168, "control": 2.500019036233425, "speedup": 1.0714196622346397 } } }, { "mlx_matched": { "pairs": 580, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.0, "control": 209.54149999999998, "speedup": 1.0271642156862744 } }, "mlx_fast": { "pairs": 599, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.833, "control": 198.667, "speedup": 0.9794609358437729 } }, "frozen_baseline": { "pairs": 613, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.041, "control": 199.25, "speedup": 1.0010500349174292 }, "gpu_us": { "candidate": 2.333370503038168, "control": 2.500019036233425, "speedup": 1.0714196622346397 } }, "current_control": { "pairs": 587, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.458, "control": 202.292, "speedup": 1.0041398207070455 }, "gpu_us": { "candidate": 2.333370503038168, "control": 2.500019036233425, "speedup": 1.0714196622346397 } } } ], "summary": { "current_control": { "gpu_us": { "speedup": 1.0714285715026552, "round_speedups": [ 1.0714196622346397, 1.071446390260939, 1.0714196622346397 ], "candidate": 2.333351100323191, "control": 2.500019036233425 }, "wall_us": { "speedup": 0.998459049453218, "round_speedups": [ 0.9943955882389588, 0.9968673999419518, 1.0041398207070455 ], "candidate": 200.6447379594989, "control": 200.3355543408313 } }, "frozen_baseline": { "gpu_us": { "speedup": 1.0714196622346397, "round_speedups": [ 1.0714196622346397, 1.0714196622346397, 1.0714196622346397 ], "candidate": 2.333370503038168, "control": 2.500019036233425 }, "wall_us": { "speedup": 0.9992322710653755, "round_speedups": [ 1.0018816705220004, 0.994780212899186, 1.0010500349174292 ], "candidate": 199.31885644434027, "control": 199.16583359103169 } }, "mlx_fast": { "wall_us": { "speedup": 0.9886136268524593, "round_speedups": [ 1.0114688148563447, 0.975304347826087, 0.9794609358437729 ], "candidate": 203.42997170656378, "control": 201.11364213931924 } }, "mlx_matched": { "wall_us": { "speedup": 1.0349908895448596, "round_speedups": [ 1.0220783787397791, 1.0560524746571258, 1.0271642156862744 ], "candidate": 205.15497010590548, "control": 212.33352500446045 } } } }, { "name": "float32_256x1024", "dtype": "float32", "batches": 256, "width": 1024, "input_sha256": "f61c4e8f726835a1e764268c9c4c3dff8764ce393b77d1885758b130e4e61cd2", "epsilon": 1e-05, "candidate_layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "elements_per_thread": 4 }, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_baseline": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "current_control": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "mlx_matched": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "mlx_fast": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05, "max_difference_from_matched_policy": 9.5367431640625e-07 } }, "validated_before_timing": true, "shaders": { "candidate": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "current_control": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant int& N [[buffer(3)]],\n constant float& eps [[buffer(4)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v1 = v0 * N;\n float _acc_0 = 0.0f;\n const int _ew_end_0 = (N / 1024) * 1024;\n for (int v9 = 0; v9 < _ew_end_0; v9 += 1024) {\n int lane_v10 = static_cast(lid) * 4;\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n float4 v18 = *(device const float4*)(X + _off_v17);\n float4 v19 = float4(v18);\n float4 v20 = v19 * v19;\n float v22 = _acc_0 + (v20.x + v20.y + v20.z + v20.w);\n _acc_0 = v22;\n }\n for (int v9 = _ew_end_0; v9 < N; v9 += 256) {\n int lane_v10 = static_cast(lid);\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n float v18 = v16 ? X[_off_v17] : static_cast(0);\n float v19 = static_cast(v18);\n float v20 = v19 * v19;\n float v22 = _acc_0 + v20;\n _acc_0 = v22;\n }\n threadgroup float shared_reduce_0[8];\n float v23;\n {\n float _simd_val = simd_sum(_acc_0);\n if (slid == 0u) shared_reduce_0[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (lid < 8u) ? shared_reduce_0[lid] : 0.0f;\n float _result = simd_sum(_partial);\n if (lid == 0u) shared_reduce_0[0] = _result;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n v23 = shared_reduce_0[0];\n }\n float cast_v24 = static_cast(N);\n float v24 = v23 / cast_v24;\n float v25 = v24 + eps;\n float v26 = sqrt(v25);\n float v28 = 1.0f / v26;\n const int _ew_end_1 = (N / 1024) * 1024;\n for (int v30 = 0; v30 < _ew_end_1; v30 += 1024) {\n int lane_v31 = static_cast(lid) * 4;\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n float4 v39 = *(device const float4*)(X + _off_v38);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n float4 v46 = *(device const float4*)(W + v32);\n float4 v47 = float4(v39);\n float4 v48 = v47 * v28;\n float4 v49 = float4(v46);\n float4 v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n *(device float4*)(Out + _off_v55) = v50;\n }\n for (int v30 = _ew_end_1; v30 < N; v30 += 256) {\n int lane_v31 = static_cast(lid);\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n float v39 = v37 ? X[_off_v38] : static_cast(0);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n float v46 = v44 ? W[v32] : static_cast(0);\n float v47 = static_cast(v39);\n float v48 = v47 * v28;\n float v49 = static_cast(v46);\n float v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n if (v54) { Out[_off_v55] = v50; }\n }\n}", "source_sha256": "c299dc56d7502bee63f4ff70bc00ff24f55197b77b602d0dbea32682813a09b6", "function_name": "mtile_rmsnorm", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3, 4 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 256 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "scalar lanes", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [ { "induction_variable": "v9", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v9", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 }, { "induction_variable": "v30", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v30", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 } ], "allocations": [ { "name": "shared_reduce_0", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [], "layout_conversions": [], "pipelines": [], "register_reductions": [], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "frozen_baseline": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant int& N [[buffer(3)]],\n constant float& eps [[buffer(4)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v1 = v0 * N;\n float _acc_0 = 0.0f;\n const int _ew_end_0 = (N / 1024) * 1024;\n for (int v9 = 0; v9 < _ew_end_0; v9 += 1024) {\n int lane_v10 = static_cast(lid) * 4;\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n float4 v18 = *(device const float4*)(X + _off_v17);\n float4 v19 = float4(v18);\n float4 v20 = v19 * v19;\n float v22 = _acc_0 + (v20.x + v20.y + v20.z + v20.w);\n _acc_0 = v22;\n }\n for (int v9 = _ew_end_0; v9 < N; v9 += 256) {\n int lane_v10 = static_cast(lid);\n int v11 = v9 + lane_v10;\n bool v14 = v11 >= 0;\n bool v15 = v11 < N;\n bool v16 = v14 & v15;\n int _off_v17 = v1 + v11;\n float v18 = v16 ? X[_off_v17] : static_cast(0);\n float v19 = static_cast(v18);\n float v20 = v19 * v19;\n float v22 = _acc_0 + v20;\n _acc_0 = v22;\n }\n threadgroup float shared_reduce_0[8];\n float v23;\n {\n float _simd_val = simd_sum(_acc_0);\n if (slid == 0u) shared_reduce_0[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (lid < 8u) ? shared_reduce_0[lid] : 0.0f;\n float _result = simd_sum(_partial);\n if (lid == 0u) shared_reduce_0[0] = _result;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n v23 = shared_reduce_0[0];\n }\n float cast_v24 = static_cast(N);\n float v24 = v23 / cast_v24;\n float v25 = v24 + eps;\n float v26 = sqrt(v25);\n float v28 = 1.0f / v26;\n const int _ew_end_1 = (N / 1024) * 1024;\n for (int v30 = 0; v30 < _ew_end_1; v30 += 1024) {\n int lane_v31 = static_cast(lid) * 4;\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n float4 v39 = *(device const float4*)(X + _off_v38);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n float4 v46 = *(device const float4*)(W + v32);\n float4 v47 = float4(v39);\n float4 v48 = v47 * v28;\n float4 v49 = float4(v46);\n float4 v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n *(device float4*)(Out + _off_v55) = v50;\n }\n for (int v30 = _ew_end_1; v30 < N; v30 += 256) {\n int lane_v31 = static_cast(lid);\n int v32 = v30 + lane_v31;\n bool v35 = v32 >= 0;\n bool v36 = v32 < N;\n bool v37 = v35 & v36;\n int _off_v38 = v1 + v32;\n float v39 = v37 ? X[_off_v38] : static_cast(0);\n bool v42 = v32 >= 0;\n bool v43 = v32 < N;\n bool v44 = v42 & v43;\n float v46 = v44 ? W[v32] : static_cast(0);\n float v47 = static_cast(v39);\n float v48 = v47 * v28;\n float v49 = static_cast(v46);\n float v50 = v48 * v49;\n bool v52 = v32 >= 0;\n bool v53 = v32 < N;\n bool v54 = v52 & v53;\n int _off_v55 = v1 + v32;\n if (v54) { Out[_off_v55] = v50; }\n }\n}", "source_sha256": "c299dc56d7502bee63f4ff70bc00ff24f55197b77b602d0dbea32682813a09b6", "function_name": "mtile_rmsnorm", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3, 4 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 256 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "scalar lanes", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [ { "induction_variable": "v9", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v9", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 }, { "induction_variable": "v30", "kind": "aligned_interior", "lanes": 256, "elements_per_lane": 4, "iteration_step": 1024 }, { "induction_variable": "v30", "kind": "masked_tail", "lanes": 256, "elements_per_lane": 1, "iteration_step": 256 } ], "allocations": [ { "name": "shared_reduce_0", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [], "layout_conversions": [], "pipelines": [] } } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "current_control": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_baseline": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "rounds": [ { "frozen_baseline": { "pairs": 561, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 217.208, "control": 217.917, "speedup": 1.0032641523332475 }, "gpu_us": { "candidate": 8.083356078714132, "control": 8.374976459890604, "speedup": 1.0360766466720914 } }, "current_control": { "pairs": 522, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 220.833, "control": 219.02100000000002, "speedup": 0.9917947045957806 }, "gpu_us": { "candidate": 8.124974556267262, "control": 8.333357982337475, "speedup": 1.0256472712163112 } }, "mlx_matched": { "pairs": 550, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 216.83350000000002, "control": 227.875, "speedup": 1.0509215596298542 } }, "mlx_fast": { "pairs": 564, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 218.042, "control": 216.688, "speedup": 0.993790187211638 } } }, { "current_control": { "pairs": 570, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 215.812, "control": 216.0, "speedup": 1.0008711285748706 }, "gpu_us": { "candidate": 8.124974556267262, "control": 8.333299774676561, "speedup": 1.025640107174072 } }, "mlx_matched": { "pairs": 528, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 220.7705, "control": 227.7295, "speedup": 1.03152142156674 } }, "mlx_fast": { "pairs": 531, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 218.959, "control": 217.875, "speedup": 0.995049301467398 } }, "frozen_baseline": { "pairs": 569, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 216.708, "control": 217.709, "speedup": 1.004619118814257 }, "gpu_us": { "candidate": 8.083356078714132, "control": 8.333299774676561, "speedup": 1.0309207825967985 } } }, { "mlx_matched": { "pairs": 549, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 218.958, "control": 228.959, "speedup": 1.0456754263374712 } }, "mlx_fast": { "pairs": 569, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 218.125, "control": 216.958, "speedup": 0.9946498567335244 } }, "frozen_baseline": { "pairs": 571, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 217.0, "control": 217.833, "speedup": 1.0038387096774193 }, "gpu_us": { "candidate": 8.083356078714132, "control": 8.333299774676561, "speedup": 1.0309207825967985 } }, "current_control": { "pairs": 570, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 215.9995, "control": 217.125, "speedup": 1.0052106602098616 }, "gpu_us": { "candidate": 8.083356078714132, "control": 8.291681297123432, "speedup": 1.025772119448985 } } } ], "summary": { "current_control": { "gpu_us": { "speedup": 1.0256864974888624, "round_speedups": [ 1.0256472712163112, 1.025640107174072, 1.025772119448985 ], "candidate": 8.111077975899041, "control": 8.31942315995894 }, "wall_us": { "speedup": 0.9992765074904383, "round_speedups": [ 0.9917947045957806, 1.0008711285748706, 1.0052106602098616 ], "candidate": 217.53581500198717, "control": 217.37842946927154 } }, "frozen_baseline": { "gpu_us": { "speedup": 1.0326365468200642, "round_speedups": [ 1.0360766466720914, 1.0309207825967985, 1.0309207825967985 ], "candidate": 8.083356078714132, "control": 8.347168907840336 }, "wall_us": { "speedup": 1.0039071733804659, "round_speedups": [ 1.0032641523332475, 1.004619118814257, 1.0038387096774193 ], "candidate": 216.97190306572818, "control": 217.81964990969556 } }, "mlx_fast": { "wall_us": { "speedup": 0.9944963096893834, "round_speedups": [ 0.993790187211638, 0.995049301467398, 0.9946498567335244 ], "candidate": 218.3749410427399, "control": 217.1730729956415 } }, "mlx_matched": { "wall_us": { "speedup": 1.0426738580881887, "round_speedups": [ 1.0509215596298542, 1.03152142156674, 1.0456754263374712 ], "candidate": 218.84808273794005, "control": 228.1871747635712 } } } } ], "promotion_gate": { "passed": false, "policy": "all batch32/256 cases must improve GPU throughput >=10%; every case must avoid >3% wall regression, against both frozen baseline and current control", "gpu_speedup_minimum": 1.1, "wall_latency_ratio_maximum": 1.03, "comparisons": { "frozen_baseline": { "passed": false, "failed_gpu_cases": [ "float16_256x1024", "float32_32x1024", "float32_256x1024" ], "failed_wall_cases": [] }, "current_control": { "passed": false, "failed_gpu_cases": [ "float16_256x1024", "float32_32x1024", "float32_256x1024" ], "failed_wall_cases": [] } } } }