{ "kind": "register_tiling_validate", "recorded_at": "2026-10-02T18:46:10.503217+00:00", "process_id": 81857, "platform": "macOS-26.2-arm64-arm-64bit", "device": "Apple M5", "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "mlx_version": "0.32.0", "compiler_implementation_sha256": "f255b038cc297ff6ba053b68cc787f7e16d855c0b665ab82b8d5ea33c463f8be", "benchmark_source_sha256": "47a379ae8881b98ece7df1f415afed0c5f2b189f9459bf34a14198a22d112675", "benchmark_sources": { "rmsnorm_tiling.py": "01f23e4595e5a7f978945c8dde559b64415deea275c407dbb3de692b15605536", "register_rmsnorm.py": "3c6fb7144a3c48de6c74a2626eb7fd05b4c4d41918c7ac43d9dcc93165447c61" }, "baseline_export_sha256": "ddda22c512e09d77a855c6cbbd49b6f1bac26d5db71197d8c05b0e4f0ff257f9", "frozen_baseline": { "kind": "frozen_static_width_register4_baseline", "recorded_at": "2026-10-02T18:25:32.133814+00:00", "root": "/private/tmp/metile-tiling-baseline.AKA1sY", "compiler_implementation_sha256": "81570d03d2db5ba7146d00acd5feb8e3ed9e0a0139d9018a1bf4c0b83703f9cf", "device": "Apple M5", "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "seed": 1741, "epsilon": 1e-05, "gate_policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "cases": [ { "name": "float16_1x1009", "dtype": "float16", "batches": 1, "width": 1009, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "20ffd5db614652b191eacaaeaec1d5949ec0b2eac97fa1cb02c0c6d776e088b5", "correctness": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 376, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 307.896, "control": 307.021, "speedup": 0.9971581313170681 }, "gpu_us": { "candidate": 6.958318408578634, "control": 6.958318408578634, "speedup": 1.0 } } }, { "name": "float16_32x1009", "dtype": "float16", "batches": 32, "width": 1009, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "e6d696cff86bdf9ec8254c3438c13725f24b2b1f6073b44660a256dcea0488a8", "correctness": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 510, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 220.542, "control": 223.35399999999998, "speedup": 1.0127504058183927 }, "gpu_us": { "candidate": 3.1041563488543034, "control": 3.249995643272996, "speedup": 1.0469819422828104 } } }, { "name": "float16_256x1009", "dtype": "float16", "batches": 256, "width": 1009, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "3fe4b7685e23d624bcb19d6442cc8d72636943e6c185f3b0049a2ac1e0b63d81", "correctness": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 564, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 211.60399999999998, "control": 210.562, "speedup": 0.9950757074535455 }, "gpu_us": { "candidate": 5.62501372769475, "control": 5.62501372769475, "speedup": 1.0 } } }, { "name": "float16_1x1024", "dtype": "float16", "batches": 1, "width": 1024, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "3cc059cb43f2d2ee6f0120b1b81a1fb6efa6af199ab539eb734dc561564c6ebe", "correctness": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 617, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.125, "control": 199.125, "speedup": 1.0050473186119875 }, "gpu_us": { "candidate": 1.6666599549353123, "control": 1.6666599549353123, "speedup": 1.0 } } }, { "name": "float16_32x1024", "dtype": "float16", "batches": 32, "width": 1024, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "6e821d0e3f7ad3cc0206f556836dd56fc15c5cc3181cc0547765f5bce1880ac4", "correctness": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 615, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.875, "control": 198.209, "speedup": 0.9966511627906977 }, "gpu_us": { "candidate": 2.083310391753912, "control": 2.083310391753912, "speedup": 1.0 } } }, { "name": "float16_256x1024", "dtype": "float16", "batches": 256, "width": 1024, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "fcaf7de00cd83d1d1e75063d1ab252906b9f1076e1f1c8a88d773ec19ed2a30c", "correctness": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 597, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.375, "control": 204.25, "speedup": 0.999388379204893 }, "gpu_us": { "candidate": 4.958303179591894, "control": 4.958361387252808, "speedup": 1.0000117394315766 } } }, { "name": "float32_1x1009", "dtype": "float32", "batches": 1, "width": 1009, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "72c4fd9244d1e3fe8e922e59cd98ff745af158f79bcd15c587482eb6749d4442", "correctness": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 553, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.042, "control": 201.167, "speedup": 1.010676138704394 }, "gpu_us": { "candidate": 1.7500133253633976, "control": 1.7500133253633976, "speedup": 1.0 } } }, { "name": "float32_32x1009", "dtype": "float32", "batches": 32, "width": 1009, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "41fd264c427e4e182eaad0b6751f90d1477b7e8f193b298a4dc8ccbfebb45ec3", "correctness": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 614, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.20850000000002, "control": 197.2295, "speedup": 0.9950607567283946 }, "gpu_us": { "candidate": 2.41666566580534, "control": 2.41666566580534, "speedup": 1.0 } } }, { "name": "float32_256x1009", "dtype": "float32", "batches": 256, "width": 1009, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "7bf6ce415ddd84786a2d450acbead1c0e25e5540b52b07d28c1e7796b91c7626", "correctness": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 559, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 217.792, "control": 216.334, "speedup": 0.9933055392300911 }, "gpu_us": { "candidate": 8.375034667551517, "control": 8.375034667551517, "speedup": 1.0 } } }, { "name": "float32_1x1024", "dtype": "float32", "batches": 1, "width": 1024, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "ddb1751346f69e81810fa3e5e4fc2fa3d8214ffaace8e689775a59ca252f7042", "correctness": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 615, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.166, "control": 197.292, "speedup": 0.9955895562306349 }, "gpu_us": { "candidate": 1.708336640149355, "control": 1.708336640149355, "speedup": 1.0 } } }, { "name": "float32_32x1024", "dtype": "float32", "batches": 32, "width": 1024, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "0fc05dcd6172e2eebffb6471582bea984c5a888fc3b3a095d91b296908e6567b", "correctness": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 605, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.334, "control": 197.875, "speedup": 0.992680626486199 }, "gpu_us": { "candidate": 2.374988980591297, "control": 2.374988980591297, "speedup": 1.0 } } }, { "name": "float32_256x1024", "dtype": "float32", "batches": 256, "width": 1024, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "d91bbc8e56d1e705bcdef1e433ae3b5ce1d9e73a225cd6afc919bf59342546a9", "correctness": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 570, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 215.97899999999998, "control": 214.54149999999998, "speedup": 0.9933442603216054 }, "gpu_us": { "candidate": 8.04167939350009, "control": 8.083297871053219, "speedup": 1.0051753465310702 } } } ] }, "gate_policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "precision_comparison": { "class": "same_storage_precision", "same_weight_representation": true, "bitwise_exact": false, "primary_policy": "identical storage dtype, FP32 sum/normalization/weight multiply, final output cast", "primary_mlx_comparator": "mx.compile explicit full-FP32 graph then final output cast", "mlx_fast_caveat": "secondary only: FP16 normalization rounds to storage before weight multiply; checked against its own rounding reference", "mlx_fast_source": "https://github.com/ml-explore/mlx/blob/v0.32.0/mlx/backend/metal/kernels/rms_norm.metal", "relaxed_precision": false }, "configuration": { "seed": 9473, "rounds": 3, "warmup_ms": 100.0, "rep_ms": 250.0 }, "precision": { "primary": "identical storage dtype, FP32 sum/normalization/weight multiply, final output cast; not bitwise exact", "mlx_matched": "mx.compile explicit full-FP32 graph then final output cast; primary matched-policy wall comparison", "mlx_fast": "secondary only: FP16 normalization rounds to storage before weight multiply, checked against its own rounding reference", "mlx_fast_source": "https://github.com/ml-explore/mlx/blob/v0.32.0/mlx/backend/metal/kernels/rms_norm.metal", "relaxed_precision": false }, "measurement": { "gpu": "paired Metal command-buffer timestamps for candidate and exact frozen register4 shader", "wall": "paired per-invocation synchronized wall latency, compile/setup excluded; MLX includes allocation/evaluation", "compilation": "all meTile shaders rebuilt offline with identical -O2 -ffast-math compiler and default Metal language version", "specialization": "both frozen and current kernels use static N and BLOCK=1024; only compiler/ownership changes vary", "ordering": "AB/BA dispatch pairs; variant order rotates across cases; comparator order rotates across rounds" }, "cases": [ { "name": "float16_1x1009", "dtype": "float16", "batches": 1, "width": 1009, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "d6f8c293ba5a765e28fbac2321aa6a0ed3b614a04d397c0083520a5e600ef512", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "mlx_matched": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "mlx_fast": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "ca8204464d79c2fc321323a988388e3cf7608e7f4edfce8846896960ec8dd552", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 614, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 205.166, "control": 205.66649999999998, "speedup": 1.0024394880243315 }, "gpu_us": { "candidate": 1.5416298992931843, "control": 1.5833647921681404, "speedup": 1.0270719275061355 } }, "mlx_matched": { "pairs": 602, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.2505, "control": 208.375, "speedup": 1.030281754556849 } }, "mlx_fast": { "pairs": 619, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.0, "control": 197.125, "speedup": 0.9807213930348259 } } }, { "mlx_matched": { "pairs": 530, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.45850000000002, "control": 204.66649999999998, "speedup": 1.0010173213635039 } }, "mlx_fast": { "pairs": 467, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 235.083, "control": 235.125, "speedup": 1.0001786603029568 } }, "frozen_register4": { "pairs": 621, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.875, "control": 198.958, "speedup": 1.0004173475801383 }, "gpu_us": { "candidate": 1.5416881069540977, "control": 1.6249832697212696, "speedup": 1.054028543381409 } } }, { "mlx_fast": { "pairs": 615, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.958, "control": 198.375, "speedup": 0.9970697333105479 } }, "frozen_register4": { "pairs": 559, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.5, "control": 202.25, "speedup": 0.9987654320987654 }, "gpu_us": { "candidate": 1.5416881069540977, "control": 1.6249832697212696, "speedup": 1.054028543381409 } }, "mlx_matched": { "pairs": 603, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.542, "control": 202.791, "speedup": 1.0112146084112057 } } } ], "summary": { "frozen_register4": { "gpu_us": { "speedup": 1.0449652962247598, "round_speedups": [ 1.0270719275061355, 1.054028543381409, 1.054028543381409 ], "candidate": 1.5416687041562684, "control": 1.6109902941190966 }, "wall_us": { "speedup": 1.0005396279503593, "round_speedups": [ 1.0024394880243315, 1.0004173475801383, 0.9987654320987654 ], "candidate": 202.163867460565, "control": 202.2729607339996 } }, "mlx_fast": { "wall_us": { "speedup": 0.9926197730302699, "round_speedups": [ 0.9807213930348259, 1.0001786603029568, 0.9970697333105479 ], "candidate": 211.05366398801397, "control": 209.49604004498931 } }, "mlx_matched": { "wall_us": { "speedup": 1.0140989011212227, "round_speedups": [ 1.030281754556849, 1.0010173213635039, 1.0112146084112057 ], "candidate": 202.41065582454135, "control": 205.2644236468935 } } } }, { "name": "float16_32x1009", "dtype": "float16", "batches": 32, "width": 1009, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "5554a685ddab4162e5b9163d96de7079c0ff02cbf1ec96a83174161b0218b361", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "mlx_matched": { "passed": true, "max_absolute_error": 0.000244140625, "rtol": 0.001, "atol": 0.002 }, "mlx_fast": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "ca8204464d79c2fc321323a988388e3cf7608e7f4edfce8846896960ec8dd552", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 622, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.813, "control": 198.54149999999998, "speedup": 1.0036827711020004 }, "gpu_us": { "candidate": 1.9999570213258266, "control": 2.00001522898674, "speedup": 1.0000291044558922 } }, "mlx_matched": { "pairs": 597, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.667, "control": 207.084, "speedup": 1.0268611126262601 } }, "mlx_fast": { "pairs": 613, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.417, "control": 199.375, "speedup": 0.9948008402480827 } } }, { "mlx_matched": { "pairs": 597, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.459, "control": 207.625, "speedup": 1.0357479584353908 } }, "mlx_fast": { "pairs": 610, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.16649999999998, "control": 200.4795, "speedup": 0.9916553929558063 } }, "frozen_register4": { "pairs": 614, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.2295, "control": 198.375, "speedup": 0.9957109765371092 }, "gpu_us": { "candidate": 1.9999570213258266, "control": 2.00001522898674, "speedup": 1.0000291044558922 } } }, { "mlx_fast": { "pairs": 616, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.083, "control": 197.52100000000002, "speedup": 0.9822859217338115 } }, "frozen_register4": { "pairs": 616, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.89600000000002, "control": 199.5, "speedup": 1.0030367629313812 }, "gpu_us": { "candidate": 1.9999570213258266, "control": 2.00001522898674, "speedup": 1.0000291044558922 } }, "mlx_matched": { "pairs": 520, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 205.1875, "control": 214.6045, "speedup": 1.0458946085897045 } } } ], "summary": { "frozen_register4": { "gpu_us": { "speedup": 1.0000291044558922, "round_speedups": [ 1.0000291044558922, 1.0000291044558922, 1.0000291044558922 ], "candidate": 1.9999570213258266, "control": 2.00001522898674 }, "wall_us": { "speedup": 1.0008036293625029, "round_speedups": [ 1.0036827711020004, 0.9957109765371092, 1.0030367629313812 ], "candidate": 198.64524535619614, "control": 198.8048825080862 } }, "mlx_fast": { "wall_us": { "speedup": 0.9895664144596352, "round_speedups": [ 0.9948008402480827, 0.9916553929558063, 0.9822859217338115 ], "candidate": 201.220875900621, "control": 199.12142067940474 } }, "mlx_matched": { "wall_us": { "speedup": 1.0361387259311392, "round_speedups": [ 1.0268611126262601, 1.0357479584353908, 1.0458946085897045 ], "candidate": 202.42792923625126, "control": 209.74341669172827 } } } }, { "name": "float16_256x1009", "dtype": "float16", "batches": 256, "width": 1009, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "b1fe01c17c282dc265d750302d65238bff0f311379c37b5e9650cafe40ad9a8a", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 }, "mlx_matched": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "mlx_fast": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "ca8204464d79c2fc321323a988388e3cf7608e7f4edfce8846896960ec8dd552", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 584, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 210.72899999999998, "control": 210.3125, "speedup": 0.9980235278485639 }, "gpu_us": { "candidate": 5.41668850928545, "control": 5.583337042480707, "speedup": 1.0307657589890176 } }, "mlx_matched": { "pairs": 556, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 211.60399999999998, "control": 231.66649999999998, "speedup": 1.0948115347535963 } }, "mlx_fast": { "pairs": 585, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 211.208, "control": 210.166, "speedup": 0.9950664747547441 } } }, { "mlx_matched": { "pairs": 557, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 210.333, "control": 231.959, "speedup": 1.1028179125481974 } }, "mlx_fast": { "pairs": 523, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 212.583, "control": 213.75, "speedup": 1.0054896205246893 } }, "frozen_register4": { "pairs": 585, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 209.75, "control": 211.458, "speedup": 1.0081430274135876 }, "gpu_us": { "candidate": 5.458365194499493, "control": 5.583337042480707, "speedup": 1.0228954720924777 } } }, { "mlx_fast": { "pairs": 579, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 210.917, "control": 211.375, "speedup": 1.0021714702940019 } }, "frozen_register4": { "pairs": 587, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 209.417, "control": 210.375, "speedup": 1.0045746047360051 }, "gpu_us": { "candidate": 5.41668850928545, "control": 5.583337042480707, "speedup": 1.0307657589890176 } }, "mlx_matched": { "pairs": 557, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 209.917, "control": 232.583, "speedup": 1.1079760095656854 } } } ], "summary": { "frozen_register4": { "gpu_us": { "speedup": 1.0281356245978268, "round_speedups": [ 1.0307657589890176, 1.0228954720924777, 1.0307657589890176 ], "candidate": 5.430545259692493, "control": 5.583337042480708 }, "wall_us": { "speedup": 1.0035716287668621, "round_speedups": [ 0.9980235278485639, 1.0081430274135876, 1.0045746047360051 ], "candidate": 209.96459561708113, "control": 210.71451120680962 } }, "mlx_fast": { "wall_us": { "speedup": 1.000899733944726, "round_speedups": [ 0.9950664747547441, 1.0054896205246893, 1.0021714702940019 ], "candidate": 211.56808758621636, "control": 211.7584425762384 } }, "mlx_matched": { "wall_us": { "speedup": 1.1018551629260736, "round_speedups": [ 1.0948115347535963, 1.1028179125481974, 1.1079760095656854 ], "candidate": 210.61677902144064, "control": 232.06918536363435 } } } }, { "name": "float16_1x1024", "dtype": "float16", "batches": 1, "width": 1024, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "5788b26fccc0f4c16bf5fa37806b50aeedce80dec44ee6bc5cfeb17488931f02", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "mlx_matched": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "mlx_fast": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "a30e8c10d04f7806837b7362bac4a0f599f0d6d17735fc2e88198ca5dcb4e73d", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 577, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.833, "control": 200.25, "speedup": 0.9921568821748673 }, "gpu_us": { "candidate": 1.500011421740055, "control": 1.583306584507227, "speedup": 1.0555296856810243 } }, "mlx_matched": { "pairs": 601, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.167, "control": 202.916, "speedup": 1.0086942689407308 } }, "mlx_fast": { "pairs": 612, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.875, "control": 198.167, "speedup": 0.9816321981424149 } } }, { "mlx_matched": { "pairs": 605, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.0, "control": 202.75, "speedup": 1.0087064676616915 } }, "mlx_fast": { "pairs": 614, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.958, "control": 198.0, "speedup": 0.9755713004661063 } }, "frozen_register4": { "pairs": 620, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.6875, "control": 198.8965, "speedup": 1.001051903114187 }, "gpu_us": { "candidate": 1.4999532140791416, "control": 1.5416881069540977, "speedup": 1.0278241297683264 } } }, { "mlx_fast": { "pairs": 617, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.625, "control": 197.25, "speedup": 0.983177570093458 } }, "frozen_register4": { "pairs": 636, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.3125, "control": 197.70850000000002, "speedup": 0.9919523361555347 }, "gpu_us": { "candidate": 1.4999532140791416, "control": 1.5416881069540977, "speedup": 1.0278241297683264 } }, "mlx_matched": { "pairs": 602, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.45850000000002, "control": 204.8755, "speedup": 1.0169613096493817 } } } ], "summary": { "frozen_register4": { "gpu_us": { "speedup": 1.03697755601497, "round_speedups": [ 1.0555296856810243, 1.0278241297683264, 1.0278241297683264 ], "candidate": 1.4999726163818043, "control": 1.5554379378249839 }, "wall_us": { "speedup": 0.9950446824045711, "round_speedups": [ 0.9921568821748673, 1.001051903114187, 0.9919523361555347 ], "candidate": 199.93972285803991, "control": 198.94895803133647 } }, "mlx_fast": { "wall_us": { "speedup": 0.9801215187052754, "round_speedups": [ 0.9816321981424149, 0.9755713004661063, 0.983177570093458 ], "candidate": 201.81708142378207, "control": 197.8052643457435 } }, "mlx_matched": { "wall_us": { "speedup": 1.0114465322508526, "round_speedups": [ 1.0086942689407308, 1.0087064676616915, 1.0169613096493817 ], "candidate": 201.20841081138406, "control": 203.51154937487948 } } } }, { "name": "float16_32x1024", "dtype": "float16", "batches": 32, "width": 1024, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "41392812a0c995fa7df504bbe6893544cd787281bc6904b2d6f3ef4015a1ce2b", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 }, "mlx_matched": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "mlx_fast": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "a30e8c10d04f7806837b7362bac4a0f599f0d6d17735fc2e88198ca5dcb4e73d", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 619, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.709, "control": 198.167, "speedup": 1.0023165359189516 }, "gpu_us": { "candidate": 1.7916900105774403, "control": 1.9166618585586548, "speedup": 1.069750820311231 } }, "mlx_matched": { "pairs": 556, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 203.2285, "control": 210.5, "speedup": 1.0357799225994386 } }, "mlx_fast": { "pairs": 604, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.04149999999998, "control": 196.5, "speedup": 0.9872313060341689 } } }, { "mlx_matched": { "pairs": 572, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.7705, "control": 210.958, "speedup": 1.0507420163818888 } }, "mlx_fast": { "pairs": 599, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.333, "control": 198.875, "speedup": 0.9877913705155141 } }, "frozen_register4": { "pairs": 576, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.3125, "control": 199.33350000000002, "speedup": 1.005148439962181 }, "gpu_us": { "candidate": 1.7916900105774403, "control": 1.9166618585586548, "speedup": 1.069750820311231 } } }, { "mlx_fast": { "pairs": 617, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.375, "control": 198.292, "speedup": 0.9896044915782907 } }, "frozen_register4": { "pairs": 614, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.1245, "control": 199.8125, "speedup": 1.0034551248088506 }, "gpu_us": { "candidate": 1.7916900105774403, "control": 1.9166618585586548, "speedup": 1.069750820311231 } }, "mlx_matched": { "pairs": 592, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.3125, "control": 208.8125, "speedup": 1.0321285140562249 } } } ], "summary": { "frozen_register4": { "gpu_us": { "speedup": 1.069750820311231, "round_speedups": [ 1.069750820311231, 1.069750820311231, 1.069750820311231 ], "candidate": 1.7916900105774403, "control": 1.9166618585586548 }, "wall_us": { "speedup": 1.0036393592853492, "round_speedups": [ 1.0023165359189516, 1.005148439962181, 1.0034551248088506 ], "candidate": 198.38115254434751, "control": 199.1031328338982 } }, "mlx_fast": { "wall_us": { "speedup": 0.9882085371671493, "round_speedups": [ 0.9872313060341689, 0.9877913705155141, 0.9896044915782907 ], "candidate": 200.24762721286314, "control": 197.88641475921605 } }, "mlx_matched": { "wall_us": { "speedup": 1.0395190547937778, "round_speedups": [ 1.0357799225994386, 1.0507420163818888, 1.0321285140562249 ], "candidate": 202.10128569065338, "control": 210.0881374737554 } } } }, { "name": "float16_256x1024", "dtype": "float16", "batches": 256, "width": 1024, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "6ef50c4533756dc08e97d195665eb272011778737bdac2b66d413cacbb0539ab", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 }, "mlx_matched": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 }, "mlx_fast": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "a30e8c10d04f7806837b7362bac4a0f599f0d6d17735fc2e88198ca5dcb4e73d", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 599, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.25, "control": 204.083, "speedup": 0.9991823745410037 }, "gpu_us": { "candidate": 4.583329427987337, "control": 4.9166264943778515, "speedup": 1.0727194219021856 } }, "mlx_matched": { "pairs": 559, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 207.334, "control": 230.916, "speedup": 1.113739184118379 } }, "mlx_fast": { "pairs": 576, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 209.8125, "control": 209.52100000000002, "speedup": 0.9986106642835866 } } }, { "mlx_matched": { "pairs": 561, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 206.334, "control": 230.875, "speedup": 1.1189382263708356 } }, "mlx_fast": { "pairs": 589, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 208.334, "control": 207.75, "speedup": 0.9971968089702112 } }, "frozen_register4": { "pairs": 601, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.416, "control": 203.667, "speedup": 1.0061803414749821 }, "gpu_us": { "candidate": 4.541710950434208, "control": 4.9166264943778515, "speedup": 1.0825494066080537 } } }, { "mlx_fast": { "pairs": 592, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 205.2295, "control": 207.1875, "speedup": 1.0095405387627023 } }, "frozen_register4": { "pairs": 600, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 203.89600000000002, "control": 203.792, "speedup": 0.9994899360458273 }, "gpu_us": { "candidate": 4.541710950434208, "control": 4.9166264943778515, "speedup": 1.0825494066080537 } }, "mlx_matched": { "pairs": 563, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 206.834, "control": 231.375, "speedup": 1.1186507053965982 } } } ], "summary": { "frozen_register4": { "gpu_us": { "speedup": 1.079262776900166, "round_speedups": [ 1.0727194219021856, 1.0825494066080537, 1.0825494066080537 ], "candidate": 4.5555416156381074, "control": 4.9166264943778515 }, "wall_us": { "speedup": 1.00161235428532, "round_speedups": [ 0.9991823745410037, 1.0061803414749821, 0.9994899360458273 ], "candidate": 203.51911393592792, "control": 203.84725885142694 } }, "mlx_fast": { "wall_us": { "speedup": 1.0017675222850826, "round_speedups": [ 0.9986106642835866, 0.9971968089702112, 1.0095405387627023 ], "candidate": 207.78320108495362, "control": 208.15046252333707 } }, "mlx_matched": { "wall_us": { "speedup": 1.1171068213864381, "round_speedups": [ 1.113739184118379, 1.1189382263708356, 1.1186507053965982 ], "candidate": 206.8335970996274, "control": 231.0552222118879 } } } }, { "name": "float32_1x1009", "dtype": "float32", "batches": 1, "width": 1009, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "f13ad154dce82c599466a62d9fefda45da8cffe99a7aba166483d0cf189c8276", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 4.76837158203125e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 4.76837158203125e-07, "rtol": 3e-05, "atol": 2e-05 }, "mlx_matched": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "mlx_fast": { "passed": true, "max_absolute_error": 4.76837158203125e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "c1d33e27fc56debd55c6a508dc39b24b01c51c4f01d8ebe463b73c7d94ad343d", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 613, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.0, "control": 198.583, "speedup": 0.9979045226130653 }, "gpu_us": { "candidate": 1.583306584507227, "control": 1.6666599549353123, "speedup": 1.0526451233410536 } }, "mlx_matched": { "pairs": 614, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.47899999999998, "control": 200.64600000000002, "speedup": 1.0008330049531373 } }, "mlx_fast": { "pairs": 536, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.25, "control": 202.9375, "speedup": 0.9935740514075887 } } }, { "mlx_matched": { "pairs": 609, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.0, "control": 201.541, "speedup": 1.0026915422885572 } }, "mlx_fast": { "pairs": 582, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 203.02100000000002, "control": 200.25, "speedup": 0.986351165642963 } }, "frozen_register4": { "pairs": 619, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.167, "control": 198.083, "speedup": 0.9945573312848012 }, "gpu_us": { "candidate": 1.583306584507227, "control": 1.625041477382183, "speedup": 1.0263593250248153 } } }, { "mlx_fast": { "pairs": 615, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.875, "control": 196.917, "speedup": 0.9852007504690432 } }, "frozen_register4": { "pairs": 602, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.22899999999998, "control": 201.0005, "speedup": 1.0038530882139949 }, "gpu_us": { "candidate": 1.5833647921681404, "control": 1.6666599549353123, "speedup": 1.0526064259980883 } }, "mlx_matched": { "pairs": 609, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.291, "control": 200.417, "speedup": 0.9956580274329205 } } } ], "summary": { "frozen_register4": { "gpu_us": { "speedup": 1.0437964386843457, "round_speedups": [ 1.0526451233410536, 1.0263593250248153, 1.0526064259980883 ], "candidate": 1.583325986823102, "control": 1.6526700263223313 }, "wall_us": { "speedup": 0.9987642555325004, "round_speedups": [ 0.9979045226130653, 0.9945573312848012, 1.0038530882139949 ], "candidate": 199.46459162970427, "control": 199.21810436413577 } }, "mlx_fast": { "wall_us": { "speedup": 0.9883683861079052, "round_speedups": [ 0.9935740514075887, 0.986351165642963, 0.9852007504690432 ], "candidate": 202.37358950972447, "control": 200.01965805459005 } }, "mlx_matched": { "wall_us": { "speedup": 0.9997230911686569, "round_speedups": [ 1.0008330049531373, 1.0026915422885572, 0.9956580274329205 ], "candidate": 200.9230524518926, "control": 200.86741508424808 } } } }, { "name": "float32_32x1009", "dtype": "float32", "batches": 32, "width": 1009, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "1aa98eaf8559293d68537497ba4b1d6ffffe410fe2a519e1363d883bbed3f406", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "mlx_matched": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "mlx_fast": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "c1d33e27fc56debd55c6a508dc39b24b01c51c4f01d8ebe463b73c7d94ad343d", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 610, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.333, "control": 200.33350000000002, "speedup": 1.0000024958444191 }, "gpu_us": { "candidate": 2.333370503038168, "control": 2.41666566580534, "speedup": 1.0356973582458153 } }, "mlx_matched": { "pairs": 515, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.375, "control": 213.167, "speedup": 1.0430189602446482 } }, "mlx_fast": { "pairs": 430, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 243.41649999999998, "control": 255.04149999999998, "speedup": 1.0477576499538857 } } }, { "mlx_matched": { "pairs": 460, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 238.89600000000002, "control": 265.54150000000004, "speedup": 1.1115359821847164 } }, "mlx_fast": { "pairs": 505, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 212.959, "control": 219.042, "speedup": 1.0285641837161144 } }, "frozen_register4": { "pairs": 600, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.70850000000002, "control": 205.20850000000002, "speedup": 1.0024424975025463 }, "gpu_us": { "candidate": 2.374988980591297, "control": 2.41666566580534, "speedup": 1.0175481594039508 } } }, { "mlx_fast": { "pairs": 604, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.10399999999998, "control": 201.66649999999998, "speedup": 0.9880575588915455 } }, "frozen_register4": { "pairs": 604, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 203.91649999999998, "control": 200.0, "speedup": 0.9807936091488428 }, "gpu_us": { "candidate": 2.333370503038168, "control": 2.41666566580534, "speedup": 1.0356973582458153 } }, "mlx_matched": { "pairs": 588, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.52100000000002, "control": 209.3955, "speedup": 1.0238337383447176 } } } ], "summary": { "frozen_register4": { "gpu_us": { "speedup": 1.02961193939828, "round_speedups": [ 1.0356973582458153, 1.0175481594039508, 1.0356973582458153 ], "candidate": 2.3471616570585554, "control": 2.41666566580534 }, "wall_us": { "speedup": 0.9943655286850116, "round_speedups": [ 1.0000024958444191, 1.0024424975025463, 0.9807936091488428 ], "candidate": 202.97703909983517, "control": 201.83337079542576 } }, "mlx_fast": { "wall_us": { "speedup": 1.021154591086457, "round_speedups": [ 1.0477576499538857, 1.0285641837161144, 0.9880575588915455 ], "candidate": 219.5326784560006, "control": 224.176802498852 } }, "mlx_matched": { "wall_us": { "speedup": 1.0588027371350186, "round_speedups": [ 1.0430189602446482, 1.1115359821847164, 1.0238337383447176 ], "candidate": 215.34007098830108, "control": 228.0026565772625 } } } }, { "name": "float32_256x1009", "dtype": "float32", "batches": 256, "width": 1009, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "04bba57bf1faebf6990e5407c042b12b66a56dc9105d818df66b0027678d4be7", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 1.430511474609375e-06, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 1.430511474609375e-06, "rtol": 3e-05, "atol": 2e-05 }, "mlx_matched": { "passed": true, "max_absolute_error": 1.430511474609375e-06, "rtol": 3e-05, "atol": 2e-05 }, "mlx_fast": { "passed": true, "max_absolute_error": 1.430511474609375e-06, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "c1d33e27fc56debd55c6a508dc39b24b01c51c4f01d8ebe463b73c7d94ad343d", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 570, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 218.6245, "control": 218.708, "speedup": 1.0003819334063657 }, "gpu_us": { "candidate": 8.333357982337475, "control": 8.375034667551517, "speedup": 1.0050011874327704 } }, "mlx_matched": { "pairs": 390, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 228.8125, "control": 242.75, "speedup": 1.0609123190385141 } }, "mlx_fast": { "pairs": 558, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 220.79149999999998, "control": 220.70850000000002, "speedup": 0.9996240797313304 } } }, { "mlx_matched": { "pairs": 517, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 222.667, "control": 232.709, "speedup": 1.0450987348821335 } }, "mlx_fast": { "pairs": 563, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 221.458, "control": 220.459, "speedup": 0.9954889866250034 } }, "frozen_register4": { "pairs": 570, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 218.72899999999998, "control": 218.60399999999998, "speedup": 0.9994285165661618 }, "gpu_us": { "candidate": 8.333299774676561, "control": 8.374976459890604, "speedup": 1.0050012223658018 } } }, { "mlx_fast": { "pairs": 561, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 222.75, "control": 219.458, "speedup": 0.9852210998877665 } }, "frozen_register4": { "pairs": 571, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 218.708, "control": 218.209, "speedup": 0.9977184190793204 }, "gpu_us": { "candidate": 8.333299774676561, "control": 8.374976459890604, "speedup": 1.0050012223658018 } }, "mlx_matched": { "pairs": 549, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 219.292, "control": 229.625, "speedup": 1.0471198219725297 } } } ], "summary": { "frozen_register4": { "gpu_us": { "speedup": 1.0050012107214579, "round_speedups": [ 1.0050011874327704, 1.0050012223658018, 1.0050012223658018 ], "candidate": 8.333319177185023, "control": 8.374995862399292 }, "wall_us": { "speedup": 0.9991756819380933, "round_speedups": [ 1.0003819334063657, 0.9994285165661618, 0.9977184190793204 ], "candidate": 218.68716200882116, "control": 218.50689423127017 } }, "mlx_fast": { "wall_us": { "speedup": 0.9934262337807716, "round_speedups": [ 0.9996240797313304, 0.9954889866250034, 0.9852210998877665 ], "candidate": 221.66501030014604, "control": 220.20783634345008 } }, "mlx_matched": { "wall_us": { "speedup": 1.0510202050336634, "round_speedups": [ 1.0609123190385141, 1.0450987348821335, 1.0471198219725297 ], "candidate": 223.55589730921156, "control": 234.96176502641237 } } } }, { "name": "float32_1x1024", "dtype": "float32", "batches": 1, "width": 1024, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "15b2d7a1b2f3cb4ff9fb2046e87c3019ad9dcf6f7b2e07869220eab417ab7fc3", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "mlx_matched": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 }, "mlx_fast": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "26dcd97c409e667a170eb1ec796096fa645431253522d88e56e53edb0819b727", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 618, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.1875, "control": 198.97899999999998, "speedup": 0.9939631595379331 }, "gpu_us": { "candidate": 1.5416881069540977, "control": 1.7082784324884415, "speedup": 1.108057086762818 } }, "mlx_matched": { "pairs": 612, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.083, "control": 201.2295, "speedup": 1.0057301219993702 } }, "mlx_fast": { "pairs": 522, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.4795, "control": 203.52100000000002, "speedup": 0.9953124885379708 } } }, { "mlx_matched": { "pairs": 611, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.375, "control": 199.875, "speedup": 0.9925512104283054 } }, "mlx_fast": { "pairs": 617, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.334, "control": 198.208, "speedup": 0.9893877225034192 } }, "frozen_register4": { "pairs": 618, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.83350000000002, "control": 197.79149999999998, "speedup": 0.9897814930929998 }, "gpu_us": { "candidate": 1.500011421740055, "control": 1.6249832697212696, "speedup": 1.083313930927435 } } }, { "mlx_fast": { "pairs": 618, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.33350000000002, "control": 197.6045, "speedup": 0.9863777151599706 } }, "frozen_register4": { "pairs": 620, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.79149999999998, "control": 198.375, "speedup": 1.0029500762166221 }, "gpu_us": { "candidate": 1.500011421740055, "control": 1.6249832697212696, "speedup": 1.083313930927435 } }, "mlx_matched": { "pairs": 594, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.6455, "control": 202.75, "speedup": 1.0054774344084048 } } } ], "summary": { "frozen_register4": { "gpu_us": { "speedup": 1.091499641086997, "round_speedups": [ 1.108057086762818, 1.083313930927435, 1.083313930927435 ], "candidate": 1.5137769383809812, "control": 1.652286984928614 }, "wall_us": { "speedup": 0.9955497727935728, "round_speedups": [ 0.9939631595379331, 0.9897814930929998, 1.0029500762166221 ], "candidate": 199.26802893910718, "control": 198.38124093535131 } }, "mlx_fast": { "wall_us": { "speedup": 0.9903523596310191, "round_speedups": [ 0.9953124885379708, 0.9893877225034192, 0.9863777151599706 ], "candidate": 201.70624221008669, "control": 199.76025292506526 } }, "mlx_matched": { "wall_us": { "speedup": 1.0012339556218117, "round_speedups": [ 1.0057301219993702, 0.9925512104283054, 1.0054774344084048 ], "candidate": 201.033342163153, "control": 201.2814083858867 } } } }, { "name": "float32_32x1024", "dtype": "float32", "batches": 32, "width": 1024, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "416f28be6885381eb5144f423d06fa77f23366329b3a1e34dfe0fe0b166273b8", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "mlx_matched": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "mlx_fast": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "26dcd97c409e667a170eb1ec796096fa645431253522d88e56e53edb0819b727", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 565, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.584, "control": 199.792, "speedup": 0.9960515295337614 }, "gpu_us": { "candidate": 2.333370503038168, "control": 2.333370503038168, "speedup": 1.0 } }, "mlx_matched": { "pairs": 594, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.9375, "control": 207.7295, "speedup": 1.0236131813982137 } }, "mlx_fast": { "pairs": 614, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.89600000000002, "control": 198.125, "speedup": 0.9813220668066727 } } }, { "mlx_matched": { "pairs": 498, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.54149999999998, "control": 207.938, "speedup": 1.0266439223566528 } }, "mlx_fast": { "pairs": 615, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.875, "control": 197.959, "speedup": 0.9904140087554721 } }, "frozen_register4": { "pairs": 616, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.0005, "control": 199.10399999999998, "speedup": 1.0106776378740154 }, "gpu_us": { "candidate": 2.333370503038168, "control": 2.333370503038168, "speedup": 1.0 } } }, { "mlx_fast": { "pairs": 613, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.209, "control": 197.584, "speedup": 0.9819839072804895 } }, "frozen_register4": { "pairs": 620, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.29149999999998, "control": 198.458, "speedup": 1.0059125709926682 }, "gpu_us": { "candidate": 2.333370503038168, "control": 2.333370503038168, "speedup": 1.0 } }, "mlx_matched": { "pairs": 604, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.5, "control": 206.2295, "speedup": 1.0337318295739348 } } } ], "summary": { "frozen_register4": { "gpu_us": { "speedup": 1.0, "round_speedups": [ 1.0, 1.0, 1.0 ], "candidate": 2.333370503038168, "control": 2.333370503038168 }, "wall_us": { "speedup": 1.0041954123886199, "round_speedups": [ 0.9960515295337614, 1.0106776378740154, 1.0059125709926682 ], "candidate": 198.2853661557495, "control": 199.11725503740115 } }, "mlx_fast": { "wall_us": { "speedup": 0.9845646453561784, "round_speedups": [ 0.9813220668066727, 0.9904140087554721, 0.9819839072804895 ], "candidate": 200.99158022919718, "control": 197.88920390793743 } }, "mlx_matched": { "wall_us": { "speedup": 1.0279875770856908, "round_speedups": [ 1.0236131813982137, 1.0266439223566528, 1.0337318295739348 ], "candidate": 201.6537995288641, "control": 207.29760078780077 } } } }, { "name": "float32_256x1024", "dtype": "float32", "batches": 256, "width": 1024, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "f9b5d63567b5ec31f59a97fbe844dc9754feaf90a4a82fae03b23d30e6797d88", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "mlx_matched": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "mlx_fast": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "26dcd97c409e667a170eb1ec796096fa645431253522d88e56e53edb0819b727", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 560, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 218.45850000000002, "control": 218.25, "speedup": 0.9990455853171196 }, "gpu_us": { "candidate": 8.000002708286047, "control": 8.000002708286047, "speedup": 1.0 } }, "mlx_matched": { "pairs": 547, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 220.625, "control": 231.416, "speedup": 1.0489110481586401 } }, "mlx_fast": { "pairs": 563, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 220.875, "control": 218.208, "speedup": 0.9879252971137521 } } }, { "mlx_matched": { "pairs": 546, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 221.52100000000002, "control": 231.7715, "speedup": 1.0462732652886182 } }, "mlx_fast": { "pairs": 538, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 221.02100000000002, "control": 222.542, "speedup": 1.0068816990240745 } }, "frozen_register4": { "pairs": 527, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { 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"float32_32x1024", "float32_256x1024" ], "failed_wall_cases": [], "failed_ragged_gpu_cases": [ "float16_1x1009", "float32_1x1009" ] } }, { "variant": { "name": "register8_blocked4", "elements_per_thread": 8, "layout": "blocked4" }, "eligible": true, "regression_guard_failures": 6, "minimum_aligned_throughput_gpu_speedup": 0.8814602420184451, "geomean_aligned_throughput_gpu_speedup": 0.9208678007594686, "training_gate": { "passed": false, "policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "failed_aligned_throughput_gpu_cases": [ "float16_32x1024", "float16_256x1024", "float32_32x1024", "float32_256x1024" ], "failed_wall_cases": [], "failed_ragged_gpu_cases": [ "float16_1x1009", "float16_32x1009", "float16_256x1009", "float32_1x1009", "float32_32x1009", "float32_256x1009" ] } }, { "variant": { "name": "register16_striped", "elements_per_thread": 16, "layout": "striped" }, "eligible": true, "regression_guard_failures": 4, "minimum_aligned_throughput_gpu_speedup": 0.9542795309833677, "geomean_aligned_throughput_gpu_speedup": 1.00466326240963, "training_gate": { "passed": false, "policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "failed_aligned_throughput_gpu_cases": [ "float16_32x1024", "float16_256x1024", "float32_32x1024", "float32_256x1024" ], "failed_wall_cases": [], "failed_ragged_gpu_cases": [ "float16_1x1009", "float16_32x1009", "float32_1x1009", "float32_32x1009" ] } }, { "variant": { "name": "register16_blocked4", "elements_per_thread": 16, "layout": "blocked4" }, "eligible": true, "regression_guard_failures": 6, "minimum_aligned_throughput_gpu_speedup": 0.766666666588103, "geomean_aligned_throughput_gpu_speedup": 0.8232797524681654, "training_gate": { "passed": false, "policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "failed_aligned_throughput_gpu_cases": [ "float16_32x1024", "float16_256x1024", "float32_32x1024", "float32_256x1024" ], "failed_wall_cases": [], "failed_ragged_gpu_cases": [ "float16_1x1009", "float16_32x1009", "float16_256x1009", "float32_1x1009", "float32_32x1009", "float32_256x1009" ] } }, { "variant": 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