{ "kind": "static_air_inspection", "recorded_at": "2026-10-02T18:46:30.166864+00:00", "precision_comparison": { "class": "same_storage_precision", "same_weight_representation": true, "bitwise_exact": false }, "compiler_implementation_sha256": "f255b038cc297ff6ba053b68cc787f7e16d855c0b665ab82b8d5ea33c463f8be", "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "input_report": "benchmarks/results/m5-rmsnorm-tiling-tuning.json", "input_report_sha256": "7f337dfd0ebceb36956bdc0b4410585797e40b0acdd60b80c8089c6b347e28f4", "command": [ "xcrun", "-sdk", "macosx", "metal", "-O2", "-ffast-math", "-S", "-emit-llvm", "-c", "kernel.metal", "-o", "kernel.ll" ], "limitations": [ "Intermediate AIR operation counts are not AGX machine instruction counts.", "The surviving branch reduction demonstrates exposed range information, not a standalone timing attribution.", "GPU comparisons are in the frozen-policy heldout reports; this inspection performs no GPU execution." ], "cases": [ { "name": "float16_32x1009", "dtype": "float16", "width": 1009, "batches": 32, "arms": { "frozen_register4": { "source_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "air_sha256": "628f550626a4a4edfae9d879dab5ff5e4c78b161d154e5bf9146d23a4643c79f", "conditional_branches": 14, "scalar_device_memory_operations": 12, "vector_device_memory_operations": 0, "textual_air": "; ModuleID = '/var/folders/x7/hs9bdmg17g167js6kt76dlxh0000gn/T/metile-tiling-air-report-dh59nkto/float16_32x1009_frozen_register4.metal'\nsource_filename = \"/var/folders/x7/hs9bdmg17g167js6kt76dlxh0000gn/T/metile-tiling-air-report-dh59nkto/float16_32x1009_frozen_register4.metal\"\ntarget datalayout = \"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-n8:16:32\"\ntarget triple = \"air64_v28-apple-macosx26.0.0\"\n\n@_ZZ22mtile_rmsnorm_registerPU9MTLdeviceKDhS0_PU9MTLdeviceDhRU11MTLconstantKfDv3_jjjjE26_metile_register_reduction = internal unnamed_addr addrspace(3) global [8 x float] undef, align 4\n\n; Function Attrs: convergent mustprogress nounwind willreturn\ndefine void @mtile_rmsnorm_register(half addrspace(1)* nocapture noundef readonly \"air-buffer-no-alias\" %0, half addrspace(1)* nocapture noundef readonly \"air-buffer-no-alias\" %1, half addrspace(1)* nocapture noundef writeonly \"air-buffer-no-alias\" %2, float addrspace(2)* nocapture noundef readonly align 4 dereferenceable(4) \"air-buffer-no-alias\" %3, <3 x i32> noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7) local_unnamed_addr #0 {\n %9 = extractelement <3 x i32> %4, i64 0\n %10 = mul nsw i32 %9, 1009\n %11 = add i32 %5, 256\n %12 = add i32 %5, 512\n %13 = add i32 %5, 768\n %14 = icmp slt i32 %5, 1009\n %15 = xor i32 %5, -1\n %16 = lshr i32 %15, 31\n %17 = zext i1 %14 to i32\n %18 = and i32 %16, %17\n %19 = icmp ne i32 %18, 0\n %20 = icmp ult i32 %11, 1009\n %21 = icmp ult i32 %12, 1009\n %22 = icmp ult i32 %13, 1009\n %23 = add nsw i32 %10, %5\n %24 = add nsw i32 %10, %11\n %25 = add nsw i32 %10, %12\n %26 = add nsw i32 %10, %13\n br i1 %19, label %27, label %32\n\n27: ; preds = %8\n %28 = sext i32 %23 to i64\n %29 = getelementptr inbounds half, half addrspace(1)* %0, i64 %28\n %30 = load half, half addrspace(1)* %29, align 2, !tbaa !27, !alias.scope !31, !noalias !34\n %31 = fpext half %30 to float\n br label %32\n\n32: ; preds = %8, %27\n %33 = phi float [ %31, %27 ], [ 0.000000e+00, %8 ]\n br i1 %20, label %34, label %39\n\n34: ; preds = %32\n %35 = sext i32 %24 to i64\n %36 = getelementptr inbounds half, half addrspace(1)* %0, i64 %35\n %37 = load half, half addrspace(1)* %36, align 2, !tbaa !27, !alias.scope !31, !noalias !34\n %38 = fpext half %37 to float\n br label %39\n\n39: ; preds = %32, %34\n %40 = phi float [ %38, %34 ], [ 0.000000e+00, %32 ]\n br i1 %21, label %41, label %46\n\n41: ; preds = %39\n %42 = sext i32 %25 to i64\n %43 = getelementptr inbounds half, half addrspace(1)* %0, i64 %42\n %44 = load half, half addrspace(1)* %43, align 2, !tbaa !27, !alias.scope !31, !noalias !34\n %45 = fpext half %44 to float\n br label %46\n\n46: ; preds = %39, %41\n %47 = phi float [ %45, %41 ], [ 0.000000e+00, %39 ]\n br i1 %22, label %48, label %53\n\n48: ; preds = %46\n %49 = sext i32 %26 to i64\n %50 = getelementptr inbounds half, half addrspace(1)* %0, i64 %49\n %51 = load half, half addrspace(1)* %50, align 2, !tbaa !27, !alias.scope !31, !noalias !34\n %52 = fpext half %51 to float\n br label %53\n\n53: ; preds = %46, %48\n %54 = phi float [ %52, %48 ], [ 0.000000e+00, %46 ]\n %55 = fmul fast float %33, %33\n %56 = fmul fast float %40, %40\n %57 = fmul fast float %47, %47\n %58 = fmul fast float %54, %54\n %59 = fadd fast float %56, %55\n %60 = fadd fast float %59, %57\n %61 = fadd fast float %60, %58\n %62 = tail call fast float @air.simd_sum.f32(float %61) #3\n %63 = icmp eq i32 %7, 0\n br i1 %63, label %64, label %67\n\n64: ; preds = %53\n %65 = zext i32 %6 to i64\n %66 = getelementptr inbounds [8 x float], [8 x float] addrspace(3)* @_ZZ22mtile_rmsnorm_registerPU9MTLdeviceKDhS0_PU9MTLdeviceDhRU11MTLconstantKfDv3_jjjjE26_metile_register_reduction, i64 0, i64 %65\n store float %62, float addrspace(3)* %66, align 4, !tbaa !38\n br label %67\n\n67: ; preds = %64, %53\n tail call void @air.wg.barrier(i32 2, i32 1) #3\n %68 = icmp ult i32 %7, 8\n br i1 %68, label %69, label %73\n\n69: ; preds = %67\n %70 = zext i32 %7 to i64\n %71 = getelementptr inbounds [8 x float], [8 x float] addrspace(3)* @_ZZ22mtile_rmsnorm_registerPU9MTLdeviceKDhS0_PU9MTLdeviceDhRU11MTLconstantKfDv3_jjjjE26_metile_register_reduction, i64 0, i64 %70\n %72 = load float, float addrspace(3)* %71, align 4, !tbaa !38\n br label %73\n\n73: ; preds = %67, %69\n %74 = phi fast float [ %72, %69 ], [ 0.000000e+00, %67 ]\n %75 = tail call fast float @air.simd_sum.f32(float %74) #3\n %76 = fmul fast float %75, 0x3F503CE460000000\n %77 = load float, float addrspace(2)* %3, align 4, !tbaa !38, !alias.scope !40, !noalias !41\n %78 = fadd fast float %76, %77\n %79 = tail call fast float @air.fast_sqrt.f32(float %78) #4\n %80 = fdiv fast float 1.000000e+00, %79\n br i1 %19, label %81, label %86\n\n81: ; preds = %73\n %82 = sext i32 %5 to i64\n %83 = getelementptr inbounds half, half addrspace(1)* %1, i64 %82\n %84 = load half, half addrspace(1)* %83, align 2, !tbaa !27, !alias.scope !42, !noalias !43\n %85 = fpext half %84 to float\n br label %86\n\n86: ; preds = %73, %81\n %87 = phi float [ %85, %81 ], [ 0.000000e+00, %73 ]\n br i1 %20, label %88, label %93\n\n88: ; preds = %86\n %89 = zext i32 %11 to i64\n %90 = getelementptr inbounds half, half addrspace(1)* %1, i64 %89\n %91 = load half, half addrspace(1)* %90, align 2, !tbaa !27, !alias.scope !42, !noalias !43\n %92 = fpext half %91 to float\n br label %93\n\n93: ; preds = %86, %88\n %94 = phi float [ %92, %88 ], [ 0.000000e+00, %86 ]\n br i1 %21, label %95, label %100\n\n95: ; preds = %93\n %96 = zext i32 %12 to i64\n %97 = getelementptr inbounds half, half addrspace(1)* %1, i64 %96\n %98 = load half, half addrspace(1)* %97, align 2, !tbaa !27, !alias.scope !42, !noalias !43\n %99 = fpext half %98 to float\n br label %100\n\n100: ; preds = %93, %95\n %101 = phi float [ %99, %95 ], [ 0.000000e+00, %93 ]\n br i1 %22, label %102, label %107\n\n102: ; preds = %100\n %103 = zext i32 %13 to i64\n %104 = getelementptr inbounds half, half addrspace(1)* %1, i64 %103\n %105 = load half, half addrspace(1)* %104, align 2, !tbaa !27, !alias.scope !42, !noalias !43\n %106 = fpext half %105 to float\n br label %107\n\n107: ; preds = %100, %102\n %108 = phi float [ %106, %102 ], [ 0.000000e+00, %100 ]\n %109 = fmul fast float %80, %40\n %110 = fmul fast float %80, %47\n %111 = fmul fast float %80, %54\n %112 = fmul fast float %109, %94\n %113 = fmul fast float %110, %101\n %114 = fmul fast float %111, %108\n br i1 %19, label %115, label %121\n\n115: ; preds = %107\n %116 = sext i32 %23 to i64\n %117 = getelementptr inbounds half, half addrspace(1)* %2, i64 %116\n %118 = fmul fast float %80, %33\n %119 = fmul fast float %118, %87\n %120 = fptrunc float %119 to half\n store half %120, half addrspace(1)* %117, align 2, !tbaa !27, !alias.scope !44, !noalias !45\n br label %121\n\n121: ; preds = %115, %107\n br i1 %20, label %122, label %126\n\n122: ; preds = %121\n %123 = sext i32 %24 to i64\n %124 = getelementptr inbounds half, half addrspace(1)* %2, i64 %123\n %125 = fptrunc float %112 to half\n store half %125, half addrspace(1)* %124, align 2, !tbaa !27, !alias.scope !44, !noalias !45\n br label %126\n\n126: ; preds = %122, %121\n br i1 %21, label %127, label %131\n\n127: ; preds = %126\n %128 = sext i32 %25 to i64\n %129 = getelementptr inbounds half, half addrspace(1)* %2, i64 %128\n %130 = fptrunc float %113 to half\n store half %130, half addrspace(1)* %129, align 2, !tbaa !27, !alias.scope !44, !noalias !45\n br label %131\n\n131: ; preds = %127, %126\n br i1 %22, label %132, label %136\n\n132: ; preds = %131\n %133 = sext i32 %26 to i64\n %134 = getelementptr inbounds half, half addrspace(1)* %2, i64 %133\n %135 = fptrunc float %114 to half\n store half %135, half addrspace(1)* %134, align 2, !tbaa !27, !alias.scope !44, !noalias !45\n br label %136\n\n136: ; preds = %132, %131\n ret void\n}\n\n; Function Attrs: convergent mustprogress nounwind willreturn\ndeclare void @air.wg.barrier(i32, i32) local_unnamed_addr #1\n\n; Function Attrs: mustprogress nofree nosync nounwind readnone willreturn\ndeclare float @air.fast_sqrt.f32(float) local_unnamed_addr #2\n\n; Function Attrs: convergent mustprogress nounwind willreturn\ndeclare float @air.simd_sum.f32(float) local_unnamed_addr #1\n\nattributes #0 = { convergent mustprogress nounwind willreturn \"approx-func-fp-math\"=\"true\" \"frame-pointer\"=\"all\" \"min-legal-vector-width\"=\"96\" \"no-builtins\" \"no-infs-fp-math\"=\"true\" \"no-nans-fp-math\"=\"true\" \"no-signed-zeros-fp-math\"=\"true\" \"no-trapping-math\"=\"true\" \"stack-protector-buffer-size\"=\"8\" \"unsafe-fp-math\"=\"true\" }\nattributes #1 = { convergent mustprogress nounwind willreturn }\nattributes #2 = { mustprogress nofree nosync nounwind readnone willreturn }\nattributes #3 = { convergent nounwind willreturn }\nattributes #4 = { nounwind readnone willreturn }\n\n!llvm.module.flags = !{!0, !1, !2, !3, !4, !5, !6, !7, !8}\n!air.kernel = !{!9}\n!air.compile_options = !{!20, !21, !22}\n!llvm.ident = !{!23}\n!air.version = !{!24}\n!air.language_version = !{!25}\n!air.source_file_name = !{!26}\n\n!0 = !{i32 2, !\"SDK Version\", [2 x i32] [i32 26, i32 2]}\n!1 = !{i32 1, !\"wchar_size\", i32 4}\n!2 = !{i32 7, !\"frame-pointer\", i32 2}\n!3 = !{i32 7, !\"air.max_device_buffers\", i32 31}\n!4 = !{i32 7, !\"air.max_constant_buffers\", i32 31}\n!5 = !{i32 7, !\"air.max_threadgroup_buffers\", i32 31}\n!6 = !{i32 7, !\"air.max_textures\", i32 128}\n!7 = !{i32 7, !\"air.max_read_write_textures\", i32 8}\n!8 = !{i32 7, !\"air.max_samplers\", i32 16}\n!9 = !{void (half addrspace(1)*, half addrspace(1)*, half addrspace(1)*, float addrspace(2)*, <3 x i32>, i32, i32, i32)* @mtile_rmsnorm_register, !10, !11}\n!10 = !{}\n!11 = !{!12, !13, !14, !15, !16, !17, !18, !19}\n!12 = !{i32 0, !\"air.buffer\", !\"air.location_index\", i32 0, i32 1, !\"air.read\", !\"air.address_space\", i32 1, !\"air.arg_type_size\", i32 2, !\"air.arg_type_align_size\", i32 2, !\"air.arg_type_name\", !\"half\", !\"air.arg_name\", !\"X\"}\n!13 = !{i32 1, !\"air.buffer\", !\"air.location_index\", i32 1, i32 1, !\"air.read\", !\"air.address_space\", i32 1, !\"air.arg_type_size\", i32 2, !\"air.arg_type_align_size\", i32 2, !\"air.arg_type_name\", !\"half\", !\"air.arg_name\", !\"W\"}\n!14 = !{i32 2, !\"air.buffer\", !\"air.location_index\", i32 2, i32 1, !\"air.read_write\", !\"air.address_space\", i32 1, !\"air.arg_type_size\", i32 2, !\"air.arg_type_align_size\", i32 2, !\"air.arg_type_name\", !\"half\", !\"air.arg_name\", !\"Out\"}\n!15 = !{i32 3, !\"air.buffer\", !\"air.buffer_size\", i32 4, !\"air.location_index\", i32 3, i32 1, !\"air.read\", !\"air.address_space\", i32 2, !\"air.arg_type_size\", i32 4, !\"air.arg_type_align_size\", i32 4, !\"air.arg_type_name\", !\"float\", !\"air.arg_name\", !\"eps\"}\n!16 = !{i32 4, !\"air.threadgroup_position_in_grid\", !\"air.arg_type_name\", !\"uint3\", !\"air.arg_name\", !\"tgp_id\"}\n!17 = !{i32 5, !\"air.thread_index_in_threadgroup\", !\"air.arg_type_name\", !\"uint\", !\"air.arg_name\", !\"lid\"}\n!18 = !{i32 6, !\"air.simdgroup_index_in_threadgroup\", !\"air.arg_type_name\", !\"uint\", !\"air.arg_name\", !\"sgid\"}\n!19 = !{i32 7, !\"air.thread_index_in_simdgroup\", !\"air.arg_type_name\", !\"uint\", !\"air.arg_name\", !\"slid\"}\n!20 = !{!\"air.compile.denorms_disable\"}\n!21 = !{!\"air.compile.fast_math_enable\"}\n!22 = !{!\"air.compile.framebuffer_fetch_enable\"}\n!23 = !{!\"Apple metal version 32023.864 (metalfe-32023.864)\"}\n!24 = !{i32 2, i32 8, i32 0}\n!25 = !{!\"Metal\", i32 4, i32 0, i32 0}\n!26 = !{!\"/private/var/folders/x7/hs9bdmg17g167js6kt76dlxh0000gn/T/metile-tiling-air-report-dh59nkto/float16_32x1009_frozen_register4.metal\"}\n!27 = !{!28, !28, i64 0}\n!28 = !{!\"half\", !29, i64 0}\n!29 = !{!\"omnipotent char\", !30, i64 0}\n!30 = !{!\"Simple C++ TBAA\"}\n!31 = !{!32}\n!32 = distinct !{!32, !33, !\"air-alias-scope-arg(0)\"}\n!33 = distinct !{!33, !\"air-alias-scopes(mtile_rmsnorm_register)\"}\n!34 = !{!35, !36, !37}\n!35 = distinct !{!35, !33, !\"air-alias-scope-arg(1)\"}\n!36 = distinct !{!36, !33, !\"air-alias-scope-arg(2)\"}\n!37 = distinct !{!37, !33, !\"air-alias-scope-arg(3)\"}\n!38 = !{!39, !39, i64 0}\n!39 = !{!\"float\", !29, i64 0}\n!40 = !{!37}\n!41 = !{!32, !35, !36}\n!42 = !{!35}\n!43 = !{!32, !36, !37}\n!44 = !{!36}\n!45 = !{!32, !35, !37}\n" }, "range_aware_register4": { "source_sha256": "ca8204464d79c2fc321323a988388e3cf7608e7f4edfce8846896960ec8dd552", "air_sha256": "b8f7450907c7920780cab37c1f40164b5e847e684f4991ac9c7747209604418f", "conditional_branches": 5, "scalar_device_memory_operations": 12, "vector_device_memory_operations": 0, "textual_air": "; ModuleID = '/var/folders/x7/hs9bdmg17g167js6kt76dlxh0000gn/T/metile-tiling-air-report-dh59nkto/float16_32x1009_range_aware_register4.metal'\nsource_filename = \"/var/folders/x7/hs9bdmg17g167js6kt76dlxh0000gn/T/metile-tiling-air-report-dh59nkto/float16_32x1009_range_aware_register4.metal\"\ntarget datalayout = \"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-n8:16:32\"\ntarget triple = \"air64_v28-apple-macosx26.0.0\"\n\n@_ZZ22mtile_rmsnorm_registerPU9MTLdeviceKDhS0_PU9MTLdeviceDhRU11MTLconstantKfDv3_jjjjE26_metile_register_reduction = internal unnamed_addr addrspace(3) global [8 x float] undef, align 4\n\n; Function Attrs: convergent mustprogress nounwind willreturn\ndefine void @mtile_rmsnorm_register(half addrspace(1)* nocapture noundef readonly \"air-buffer-no-alias\" %0, half addrspace(1)* nocapture noundef readonly \"air-buffer-no-alias\" %1, half addrspace(1)* nocapture noundef writeonly \"air-buffer-no-alias\" %2, float addrspace(2)* nocapture noundef readonly align 4 dereferenceable(4) \"air-buffer-no-alias\" %3, <3 x i32> noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7) local_unnamed_addr #0 {\n %9 = extractelement <3 x i32> %4, i64 0\n %10 = mul nsw i32 %9, 1009\n %11 = and i32 %5, 255\n %12 = or i32 %11, 256\n %13 = or i32 %11, 512\n %14 = or i32 %11, 768\n %15 = icmp ult i32 %14, 1009\n %16 = add nsw i32 %10, %11\n %17 = add nsw i32 %12, %10\n %18 = add nsw i32 %13, %10\n %19 = add nsw i32 %14, %10\n %20 = sext i32 %16 to i64\n %21 = getelementptr inbounds half, half addrspace(1)* %0, i64 %20\n %22 = load half, half addrspace(1)* %21, align 2, !tbaa !27, !alias.scope !31, !noalias !34\n %23 = sext i32 %17 to i64\n %24 = getelementptr inbounds half, half addrspace(1)* %0, i64 %23\n %25 = load half, half addrspace(1)* %24, align 2, !tbaa !27, !alias.scope !31, !noalias !34\n %26 = sext i32 %18 to i64\n %27 = getelementptr inbounds half, half addrspace(1)* %0, i64 %26\n %28 = load half, half addrspace(1)* %27, align 2, !tbaa !27, !alias.scope !31, !noalias !34\n br i1 %15, label %29, label %34\n\n29: ; preds = %8\n %30 = sext i32 %19 to i64\n %31 = getelementptr inbounds half, half addrspace(1)* %0, i64 %30\n %32 = load half, half addrspace(1)* %31, align 2, !tbaa !27, !alias.scope !31, !noalias !34\n %33 = fpext half %32 to float\n br label %34\n\n34: ; preds = %8, %29\n %35 = phi float [ %33, %29 ], [ 0.000000e+00, %8 ]\n %36 = fpext half %22 to float\n %37 = fpext half %25 to float\n %38 = fpext half %28 to float\n %39 = fmul fast float %36, %36\n %40 = fmul fast float %37, %37\n %41 = fmul fast float %38, %38\n %42 = fmul fast float %35, %35\n %43 = fadd fast float %40, %39\n %44 = fadd fast float %43, %41\n %45 = fadd fast float %44, %42\n %46 = tail call fast float @air.simd_sum.f32(float %45) #3\n %47 = icmp eq i32 %7, 0\n br i1 %47, label %48, label %51\n\n48: ; preds = %34\n %49 = zext i32 %6 to i64\n %50 = getelementptr inbounds [8 x float], [8 x float] addrspace(3)* @_ZZ22mtile_rmsnorm_registerPU9MTLdeviceKDhS0_PU9MTLdeviceDhRU11MTLconstantKfDv3_jjjjE26_metile_register_reduction, i64 0, i64 %49\n store float %46, float addrspace(3)* %50, align 4, !tbaa !38\n br label %51\n\n51: ; preds = %48, %34\n tail call void @air.wg.barrier(i32 2, i32 1) #3\n %52 = icmp ult i32 %7, 8\n br i1 %52, label %53, label %57\n\n53: ; preds = %51\n %54 = zext i32 %7 to i64\n %55 = getelementptr inbounds [8 x float], [8 x float] addrspace(3)* @_ZZ22mtile_rmsnorm_registerPU9MTLdeviceKDhS0_PU9MTLdeviceDhRU11MTLconstantKfDv3_jjjjE26_metile_register_reduction, i64 0, i64 %54\n %56 = load float, float addrspace(3)* %55, align 4, !tbaa !38\n br label %57\n\n57: ; preds = %51, %53\n %58 = phi fast float [ %56, %53 ], [ 0.000000e+00, %51 ]\n %59 = tail call fast float @air.simd_sum.f32(float %58) #3\n %60 = fmul fast float %59, 0x3F503CE460000000\n %61 = load float, float addrspace(2)* %3, align 4, !tbaa !38, !alias.scope !40, !noalias !41\n %62 = fadd fast float %60, %61\n %63 = tail call fast float @air.fast_sqrt.f32(float %62) #4\n %64 = fdiv fast float 1.000000e+00, %63\n %65 = zext i32 %11 to i64\n %66 = getelementptr inbounds half, half addrspace(1)* %1, i64 %65\n %67 = load half, half addrspace(1)* %66, align 2, !tbaa !27, !alias.scope !42, !noalias !43\n %68 = zext i32 %12 to i64\n %69 = getelementptr inbounds half, half addrspace(1)* %1, i64 %68\n %70 = load half, half addrspace(1)* %69, align 2, !tbaa !27, !alias.scope !42, !noalias !43\n %71 = zext i32 %13 to i64\n %72 = getelementptr inbounds half, half addrspace(1)* %1, i64 %71\n %73 = load half, half addrspace(1)* %72, align 2, !tbaa !27, !alias.scope !42, !noalias !43\n br i1 %15, label %74, label %79\n\n74: ; preds = %57\n %75 = zext i32 %14 to i64\n %76 = getelementptr inbounds half, half addrspace(1)* %1, i64 %75\n %77 = load half, half addrspace(1)* %76, align 2, !tbaa !27, !alias.scope !42, !noalias !43\n %78 = fpext half %77 to float\n br label %79\n\n79: ; preds = %57, %74\n %80 = phi float [ %78, %74 ], [ 0.000000e+00, %57 ]\n %81 = fpext half %70 to float\n %82 = fpext half %73 to float\n %83 = fmul fast float %64, %37\n %84 = fmul fast float %64, %38\n %85 = fmul fast float %83, %81\n %86 = fmul fast float %84, %82\n %87 = fmul fast float %64, %36\n %88 = fpext half %67 to float\n %89 = fmul fast float %87, %88\n %90 = fptrunc float %89 to half\n %91 = getelementptr inbounds half, half addrspace(1)* %2, i64 %20\n store half %90, half addrspace(1)* %91, align 2, !tbaa !27, !alias.scope !44, !noalias !45\n %92 = fptrunc float %85 to half\n %93 = getelementptr inbounds half, half addrspace(1)* %2, i64 %23\n store half %92, half addrspace(1)* %93, align 2, !tbaa !27, !alias.scope !44, !noalias !45\n %94 = fptrunc float %86 to half\n %95 = getelementptr inbounds half, half addrspace(1)* %2, i64 %26\n store half %94, half addrspace(1)* %95, align 2, !tbaa !27, !alias.scope !44, !noalias !45\n br i1 %15, label %96, label %102\n\n96: ; preds = %79\n %97 = sext i32 %19 to i64\n %98 = getelementptr inbounds half, half addrspace(1)* %2, i64 %97\n %99 = fmul fast float %64, %35\n %100 = fmul fast float %99, %80\n %101 = fptrunc float %100 to half\n store half %101, half addrspace(1)* %98, align 2, !tbaa !27, !alias.scope !44, !noalias !45\n br label %102\n\n102: ; preds = %96, %79\n ret void\n}\n\n; Function Attrs: convergent mustprogress nounwind willreturn\ndeclare void @air.wg.barrier(i32, i32) local_unnamed_addr #1\n\n; Function Attrs: mustprogress nofree nosync nounwind readnone willreturn\ndeclare float @air.fast_sqrt.f32(float) local_unnamed_addr #2\n\n; Function Attrs: convergent mustprogress nounwind willreturn\ndeclare float @air.simd_sum.f32(float) local_unnamed_addr #1\n\nattributes #0 = { convergent mustprogress nounwind willreturn \"approx-func-fp-math\"=\"true\" \"frame-pointer\"=\"all\" \"min-legal-vector-width\"=\"96\" \"no-builtins\" \"no-infs-fp-math\"=\"true\" \"no-nans-fp-math\"=\"true\" \"no-signed-zeros-fp-math\"=\"true\" \"no-trapping-math\"=\"true\" \"stack-protector-buffer-size\"=\"8\" \"unsafe-fp-math\"=\"true\" }\nattributes #1 = { convergent mustprogress nounwind willreturn }\nattributes #2 = { mustprogress nofree nosync nounwind readnone willreturn }\nattributes #3 = { convergent nounwind willreturn }\nattributes #4 = { nounwind readnone willreturn }\n\n!llvm.module.flags = !{!0, !1, !2, !3, !4, !5, !6, !7, !8}\n!air.kernel = !{!9}\n!air.compile_options = !{!20, !21, !22}\n!llvm.ident = !{!23}\n!air.version = !{!24}\n!air.language_version = !{!25}\n!air.source_file_name = !{!26}\n\n!0 = !{i32 2, !\"SDK Version\", [2 x i32] [i32 26, i32 2]}\n!1 = !{i32 1, !\"wchar_size\", i32 4}\n!2 = !{i32 7, !\"frame-pointer\", i32 2}\n!3 = !{i32 7, !\"air.max_device_buffers\", i32 31}\n!4 = !{i32 7, !\"air.max_constant_buffers\", i32 31}\n!5 = !{i32 7, !\"air.max_threadgroup_buffers\", i32 31}\n!6 = !{i32 7, !\"air.max_textures\", i32 128}\n!7 = !{i32 7, !\"air.max_read_write_textures\", i32 8}\n!8 = !{i32 7, !\"air.max_samplers\", i32 16}\n!9 = !{void (half addrspace(1)*, half addrspace(1)*, half addrspace(1)*, float addrspace(2)*, <3 x i32>, i32, i32, i32)* @mtile_rmsnorm_register, !10, !11}\n!10 = !{}\n!11 = !{!12, !13, !14, !15, !16, !17, !18, !19}\n!12 = !{i32 0, !\"air.buffer\", !\"air.location_index\", i32 0, i32 1, !\"air.read\", !\"air.address_space\", i32 1, !\"air.arg_type_size\", i32 2, !\"air.arg_type_align_size\", i32 2, !\"air.arg_type_name\", !\"half\", !\"air.arg_name\", !\"X\"}\n!13 = !{i32 1, !\"air.buffer\", !\"air.location_index\", i32 1, i32 1, !\"air.read\", !\"air.address_space\", i32 1, !\"air.arg_type_size\", i32 2, !\"air.arg_type_align_size\", i32 2, !\"air.arg_type_name\", !\"half\", !\"air.arg_name\", !\"W\"}\n!14 = !{i32 2, !\"air.buffer\", !\"air.location_index\", i32 2, i32 1, !\"air.read_write\", !\"air.address_space\", i32 1, !\"air.arg_type_size\", i32 2, !\"air.arg_type_align_size\", i32 2, !\"air.arg_type_name\", !\"half\", !\"air.arg_name\", !\"Out\"}\n!15 = !{i32 3, !\"air.buffer\", !\"air.buffer_size\", i32 4, !\"air.location_index\", i32 3, i32 1, !\"air.read\", !\"air.address_space\", i32 2, !\"air.arg_type_size\", i32 4, !\"air.arg_type_align_size\", i32 4, !\"air.arg_type_name\", !\"float\", !\"air.arg_name\", !\"eps\"}\n!16 = !{i32 4, !\"air.threadgroup_position_in_grid\", !\"air.arg_type_name\", !\"uint3\", !\"air.arg_name\", !\"tgp_id\"}\n!17 = !{i32 5, !\"air.thread_index_in_threadgroup\", !\"air.arg_type_name\", !\"uint\", !\"air.arg_name\", !\"lid\"}\n!18 = !{i32 6, !\"air.simdgroup_index_in_threadgroup\", !\"air.arg_type_name\", !\"uint\", !\"air.arg_name\", !\"sgid\"}\n!19 = !{i32 7, !\"air.thread_index_in_simdgroup\", !\"air.arg_type_name\", !\"uint\", !\"air.arg_name\", !\"slid\"}\n!20 = !{!\"air.compile.denorms_disable\"}\n!21 = !{!\"air.compile.fast_math_enable\"}\n!22 = !{!\"air.compile.framebuffer_fetch_enable\"}\n!23 = !{!\"Apple metal version 32023.864 (metalfe-32023.864)\"}\n!24 = !{i32 2, i32 8, i32 0}\n!25 = !{!\"Metal\", i32 4, i32 0, i32 0}\n!26 = !{!\"/private/var/folders/x7/hs9bdmg17g167js6kt76dlxh0000gn/T/metile-tiling-air-report-dh59nkto/float16_32x1009_range_aware_register4.metal\"}\n!27 = !{!28, !28, i64 0}\n!28 = !{!\"half\", !29, i64 0}\n!29 = !{!\"omnipotent char\", !30, i64 0}\n!30 = !{!\"Simple C++ TBAA\"}\n!31 = !{!32}\n!32 = distinct !{!32, !33, !\"air-alias-scope-arg(0)\"}\n!33 = distinct !{!33, !\"air-alias-scopes(mtile_rmsnorm_register)\"}\n!34 = !{!35, !36, !37}\n!35 = distinct !{!35, !33, !\"air-alias-scope-arg(1)\"}\n!36 = distinct !{!36, !33, !\"air-alias-scope-arg(2)\"}\n!37 = distinct !{!37, !33, !\"air-alias-scope-arg(3)\"}\n!38 = !{!39, !39, i64 0}\n!39 = !{!\"float\", !29, i64 0}\n!40 = !{!37}\n!41 = !{!32, !35, !36}\n!42 = !{!35}\n!43 = !{!32, !36, !37}\n!44 = !{!36}\n!45 = !{!32, !35, !37}\n" } } }, { "name": "float16_32x1024", "dtype": "float16", "width": 1024, "batches": 32, "arms": { "frozen_register4": { "source_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "air_sha256": "4cd5aeaff3b86da4dc35fa6996ccdb061fb70f3ba28a9bff6e4d2f31c8fac8eb", "conditional_branches": 14, "scalar_device_memory_operations": 12, "vector_device_memory_operations": 0, "textual_air": "; ModuleID = '/var/folders/x7/hs9bdmg17g167js6kt76dlxh0000gn/T/metile-tiling-air-report-dh59nkto/float16_32x1024_frozen_register4.metal'\nsource_filename = \"/var/folders/x7/hs9bdmg17g167js6kt76dlxh0000gn/T/metile-tiling-air-report-dh59nkto/float16_32x1024_frozen_register4.metal\"\ntarget datalayout = \"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-n8:16:32\"\ntarget triple = \"air64_v28-apple-macosx26.0.0\"\n\n@_ZZ22mtile_rmsnorm_registerPU9MTLdeviceKDhS0_PU9MTLdeviceDhRU11MTLconstantKfDv3_jjjjE26_metile_register_reduction = internal unnamed_addr addrspace(3) global [8 x float] undef, align 4\n\n; Function Attrs: convergent mustprogress nounwind willreturn\ndefine void @mtile_rmsnorm_register(half addrspace(1)* nocapture noundef readonly \"air-buffer-no-alias\" %0, half addrspace(1)* nocapture noundef readonly \"air-buffer-no-alias\" %1, half addrspace(1)* nocapture noundef writeonly \"air-buffer-no-alias\" %2, float addrspace(2)* nocapture noundef readonly align 4 dereferenceable(4) \"air-buffer-no-alias\" %3, <3 x i32> noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7) local_unnamed_addr #0 {\n %9 = extractelement <3 x i32> %4, i64 0\n %10 = shl nsw i32 %9, 10\n %11 = add i32 %5, 256\n %12 = add i32 %5, 512\n %13 = add i32 %5, 768\n %14 = icmp slt i32 %5, 1024\n %15 = xor i32 %5, -1\n %16 = lshr i32 %15, 31\n %17 = zext i1 %14 to i32\n %18 = and i32 %16, %17\n %19 = icmp ne i32 %18, 0\n %20 = icmp ult i32 %11, 1024\n %21 = icmp ult i32 %12, 1024\n %22 = icmp ult i32 %13, 1024\n %23 = add nsw i32 %10, %5\n %24 = add nsw i32 %10, %11\n %25 = add nsw i32 %10, %12\n %26 = add nsw i32 %10, %13\n br i1 %19, label %27, label %32\n\n27: ; preds = %8\n %28 = sext i32 %23 to i64\n %29 = getelementptr inbounds half, half addrspace(1)* %0, i64 %28\n %30 = load half, half addrspace(1)* %29, align 2, !tbaa !27, !alias.scope !31, !noalias !34\n %31 = fpext half %30 to float\n br label %32\n\n32: ; preds = %8, %27\n %33 = phi float [ %31, %27 ], [ 0.000000e+00, %8 ]\n br i1 %20, label %34, label %39\n\n34: ; preds = %32\n %35 = sext i32 %24 to i64\n %36 = getelementptr inbounds half, half addrspace(1)* %0, i64 %35\n %37 = load half, half addrspace(1)* %36, align 2, !tbaa !27, !alias.scope !31, !noalias !34\n %38 = fpext half %37 to float\n br label %39\n\n39: ; preds = %32, %34\n %40 = phi float [ %38, %34 ], [ 0.000000e+00, %32 ]\n br i1 %21, label %41, label %46\n\n41: ; preds = %39\n %42 = sext i32 %25 to i64\n %43 = getelementptr inbounds half, half addrspace(1)* %0, i64 %42\n %44 = load half, half addrspace(1)* %43, align 2, !tbaa !27, !alias.scope !31, !noalias !34\n %45 = fpext half %44 to float\n br label %46\n\n46: ; preds = %39, %41\n %47 = phi float [ %45, %41 ], [ 0.000000e+00, %39 ]\n br i1 %22, label %48, label %53\n\n48: ; preds = %46\n %49 = sext i32 %26 to i64\n %50 = getelementptr inbounds half, half addrspace(1)* %0, i64 %49\n %51 = load half, half addrspace(1)* %50, align 2, !tbaa !27, !alias.scope !31, !noalias !34\n %52 = fpext half %51 to float\n br label %53\n\n53: ; preds = %46, %48\n %54 = phi float [ %52, %48 ], [ 0.000000e+00, %46 ]\n %55 = fmul fast float %33, %33\n %56 = fmul fast float %40, %40\n %57 = fmul fast float %47, %47\n %58 = fmul fast float %54, %54\n %59 = fadd fast float %56, %55\n %60 = fadd fast float %59, %57\n %61 = fadd fast float %60, %58\n %62 = tail call fast float @air.simd_sum.f32(float %61) #3\n %63 = icmp eq i32 %7, 0\n br i1 %63, label %64, label %67\n\n64: ; preds = %53\n %65 = zext i32 %6 to i64\n %66 = getelementptr inbounds [8 x float], [8 x float] addrspace(3)* @_ZZ22mtile_rmsnorm_registerPU9MTLdeviceKDhS0_PU9MTLdeviceDhRU11MTLconstantKfDv3_jjjjE26_metile_register_reduction, i64 0, i64 %65\n store float %62, float addrspace(3)* %66, align 4, !tbaa !38\n br label %67\n\n67: ; preds = %64, %53\n tail call void @air.wg.barrier(i32 2, i32 1) #3\n %68 = icmp ult i32 %7, 8\n br i1 %68, label %69, label %73\n\n69: ; preds = %67\n %70 = zext i32 %7 to i64\n %71 = getelementptr inbounds [8 x float], [8 x float] addrspace(3)* @_ZZ22mtile_rmsnorm_registerPU9MTLdeviceKDhS0_PU9MTLdeviceDhRU11MTLconstantKfDv3_jjjjE26_metile_register_reduction, i64 0, i64 %70\n %72 = load float, float addrspace(3)* %71, align 4, !tbaa !38\n br label %73\n\n73: ; preds = %67, %69\n %74 = phi fast float [ %72, %69 ], [ 0.000000e+00, %67 ]\n %75 = tail call fast float @air.simd_sum.f32(float %74) #3\n %76 = fmul fast float %75, 0x3F50000000000000\n %77 = load float, float addrspace(2)* %3, align 4, !tbaa !38, !alias.scope !40, !noalias !41\n %78 = fadd fast float %76, %77\n %79 = tail call fast float @air.fast_sqrt.f32(float %78) #4\n %80 = fdiv fast float 1.000000e+00, %79\n br i1 %19, label %81, label %86\n\n81: ; preds = %73\n %82 = sext i32 %5 to i64\n %83 = getelementptr inbounds half, half addrspace(1)* %1, i64 %82\n %84 = load half, half addrspace(1)* %83, align 2, !tbaa !27, !alias.scope !42, !noalias !43\n %85 = fpext half %84 to float\n br label %86\n\n86: ; preds = %73, %81\n %87 = phi float [ %85, %81 ], [ 0.000000e+00, %73 ]\n br i1 %20, label %88, label %93\n\n88: ; preds = %86\n %89 = zext i32 %11 to i64\n %90 = getelementptr inbounds half, half addrspace(1)* %1, i64 %89\n %91 = load half, half addrspace(1)* %90, align 2, !tbaa !27, !alias.scope !42, !noalias !43\n %92 = fpext half %91 to float\n br label %93\n\n93: ; preds = %86, %88\n %94 = phi float [ %92, %88 ], [ 0.000000e+00, %86 ]\n br i1 %21, label %95, label %100\n\n95: ; preds = %93\n %96 = zext i32 %12 to i64\n %97 = getelementptr inbounds half, half addrspace(1)* %1, i64 %96\n %98 = load half, half addrspace(1)* %97, align 2, !tbaa !27, !alias.scope !42, !noalias !43\n %99 = fpext half %98 to float\n br label %100\n\n100: ; preds = %93, %95\n %101 = phi float [ %99, %95 ], [ 0.000000e+00, %93 ]\n br i1 %22, label %102, label %107\n\n102: ; preds = %100\n %103 = zext i32 %13 to i64\n %104 = getelementptr inbounds half, half addrspace(1)* %1, i64 %103\n %105 = load half, half addrspace(1)* %104, align 2, !tbaa !27, !alias.scope !42, !noalias !43\n %106 = fpext half %105 to float\n br label %107\n\n107: ; preds = %100, %102\n %108 = phi float [ %106, %102 ], [ 0.000000e+00, %100 ]\n %109 = fmul fast float %80, %40\n %110 = fmul fast float %80, %47\n %111 = fmul fast float %80, %54\n %112 = fmul fast float %109, %94\n %113 = fmul fast float %110, %101\n %114 = fmul fast float %111, %108\n br i1 %19, label %115, label %121\n\n115: ; preds = %107\n %116 = sext i32 %23 to i64\n %117 = getelementptr inbounds half, half addrspace(1)* %2, i64 %116\n %118 = fmul fast float %80, %33\n %119 = fmul fast float %118, %87\n %120 = fptrunc float %119 to half\n store half %120, half addrspace(1)* %117, align 2, !tbaa !27, !alias.scope !44, !noalias !45\n br label %121\n\n121: ; preds = %115, %107\n br i1 %20, label %122, label %126\n\n122: ; preds = %121\n %123 = sext i32 %24 to i64\n %124 = getelementptr inbounds half, half addrspace(1)* %2, i64 %123\n %125 = fptrunc float %112 to half\n store half %125, half addrspace(1)* %124, align 2, !tbaa !27, !alias.scope !44, !noalias !45\n br label %126\n\n126: ; preds = %122, %121\n br i1 %21, label %127, label %131\n\n127: ; preds = %126\n %128 = sext i32 %25 to i64\n %129 = getelementptr inbounds half, half addrspace(1)* %2, i64 %128\n %130 = fptrunc float %113 to half\n store half %130, half addrspace(1)* %129, align 2, !tbaa !27, !alias.scope !44, !noalias !45\n br label %131\n\n131: ; preds = %127, %126\n br i1 %22, label %132, label %136\n\n132: ; preds = %131\n %133 = sext i32 %26 to i64\n %134 = getelementptr inbounds half, half addrspace(1)* %2, i64 %133\n %135 = fptrunc float %114 to half\n store half %135, half addrspace(1)* %134, align 2, !tbaa !27, !alias.scope !44, !noalias !45\n br label %136\n\n136: ; preds = %132, %131\n ret void\n}\n\n; Function Attrs: convergent mustprogress nounwind willreturn\ndeclare void @air.wg.barrier(i32, i32) local_unnamed_addr #1\n\n; Function Attrs: mustprogress nofree nosync nounwind readnone willreturn\ndeclare float @air.fast_sqrt.f32(float) local_unnamed_addr #2\n\n; Function Attrs: convergent mustprogress nounwind willreturn\ndeclare float @air.simd_sum.f32(float) local_unnamed_addr #1\n\nattributes #0 = { convergent mustprogress nounwind willreturn \"approx-func-fp-math\"=\"true\" \"frame-pointer\"=\"all\" \"min-legal-vector-width\"=\"96\" \"no-builtins\" \"no-infs-fp-math\"=\"true\" \"no-nans-fp-math\"=\"true\" \"no-signed-zeros-fp-math\"=\"true\" \"no-trapping-math\"=\"true\" \"stack-protector-buffer-size\"=\"8\" \"unsafe-fp-math\"=\"true\" }\nattributes #1 = { convergent mustprogress nounwind willreturn }\nattributes #2 = { mustprogress nofree nosync nounwind readnone willreturn }\nattributes #3 = { convergent nounwind willreturn }\nattributes #4 = { nounwind readnone willreturn }\n\n!llvm.module.flags = !{!0, !1, !2, !3, !4, !5, !6, !7, !8}\n!air.kernel = !{!9}\n!air.compile_options = !{!20, !21, !22}\n!llvm.ident = !{!23}\n!air.version = !{!24}\n!air.language_version = !{!25}\n!air.source_file_name = !{!26}\n\n!0 = !{i32 2, !\"SDK Version\", [2 x i32] [i32 26, i32 2]}\n!1 = !{i32 1, !\"wchar_size\", i32 4}\n!2 = !{i32 7, !\"frame-pointer\", i32 2}\n!3 = !{i32 7, !\"air.max_device_buffers\", i32 31}\n!4 = !{i32 7, !\"air.max_constant_buffers\", i32 31}\n!5 = !{i32 7, !\"air.max_threadgroup_buffers\", i32 31}\n!6 = !{i32 7, !\"air.max_textures\", i32 128}\n!7 = !{i32 7, !\"air.max_read_write_textures\", i32 8}\n!8 = !{i32 7, !\"air.max_samplers\", i32 16}\n!9 = !{void (half addrspace(1)*, half addrspace(1)*, half addrspace(1)*, float addrspace(2)*, <3 x i32>, i32, i32, i32)* @mtile_rmsnorm_register, !10, !11}\n!10 = !{}\n!11 = !{!12, !13, !14, !15, !16, !17, !18, !19}\n!12 = !{i32 0, !\"air.buffer\", !\"air.location_index\", i32 0, i32 1, !\"air.read\", !\"air.address_space\", i32 1, !\"air.arg_type_size\", i32 2, !\"air.arg_type_align_size\", i32 2, !\"air.arg_type_name\", !\"half\", !\"air.arg_name\", !\"X\"}\n!13 = !{i32 1, !\"air.buffer\", !\"air.location_index\", i32 1, i32 1, !\"air.read\", !\"air.address_space\", i32 1, !\"air.arg_type_size\", i32 2, !\"air.arg_type_align_size\", i32 2, !\"air.arg_type_name\", !\"half\", !\"air.arg_name\", !\"W\"}\n!14 = !{i32 2, !\"air.buffer\", !\"air.location_index\", i32 2, i32 1, !\"air.read_write\", !\"air.address_space\", i32 1, !\"air.arg_type_size\", i32 2, !\"air.arg_type_align_size\", i32 2, !\"air.arg_type_name\", !\"half\", !\"air.arg_name\", !\"Out\"}\n!15 = !{i32 3, !\"air.buffer\", !\"air.buffer_size\", i32 4, !\"air.location_index\", i32 3, i32 1, !\"air.read\", !\"air.address_space\", i32 2, !\"air.arg_type_size\", i32 4, !\"air.arg_type_align_size\", i32 4, !\"air.arg_type_name\", !\"float\", !\"air.arg_name\", !\"eps\"}\n!16 = !{i32 4, !\"air.threadgroup_position_in_grid\", !\"air.arg_type_name\", !\"uint3\", !\"air.arg_name\", !\"tgp_id\"}\n!17 = !{i32 5, !\"air.thread_index_in_threadgroup\", !\"air.arg_type_name\", !\"uint\", !\"air.arg_name\", !\"lid\"}\n!18 = !{i32 6, !\"air.simdgroup_index_in_threadgroup\", !\"air.arg_type_name\", !\"uint\", !\"air.arg_name\", !\"sgid\"}\n!19 = !{i32 7, !\"air.thread_index_in_simdgroup\", !\"air.arg_type_name\", !\"uint\", !\"air.arg_name\", !\"slid\"}\n!20 = !{!\"air.compile.denorms_disable\"}\n!21 = !{!\"air.compile.fast_math_enable\"}\n!22 = !{!\"air.compile.framebuffer_fetch_enable\"}\n!23 = !{!\"Apple metal version 32023.864 (metalfe-32023.864)\"}\n!24 = !{i32 2, i32 8, i32 0}\n!25 = !{!\"Metal\", i32 4, i32 0, i32 0}\n!26 = !{!\"/private/var/folders/x7/hs9bdmg17g167js6kt76dlxh0000gn/T/metile-tiling-air-report-dh59nkto/float16_32x1024_frozen_register4.metal\"}\n!27 = !{!28, !28, i64 0}\n!28 = !{!\"half\", !29, i64 0}\n!29 = !{!\"omnipotent char\", !30, i64 0}\n!30 = !{!\"Simple C++ TBAA\"}\n!31 = !{!32}\n!32 = distinct !{!32, !33, !\"air-alias-scope-arg(0)\"}\n!33 = distinct !{!33, !\"air-alias-scopes(mtile_rmsnorm_register)\"}\n!34 = !{!35, !36, !37}\n!35 = distinct !{!35, !33, !\"air-alias-scope-arg(1)\"}\n!36 = distinct !{!36, !33, !\"air-alias-scope-arg(2)\"}\n!37 = distinct !{!37, !33, !\"air-alias-scope-arg(3)\"}\n!38 = !{!39, !39, i64 0}\n!39 = !{!\"float\", !29, i64 0}\n!40 = !{!37}\n!41 = !{!32, !35, !36}\n!42 = !{!35}\n!43 = !{!32, !36, !37}\n!44 = !{!36}\n!45 = !{!32, !35, !37}\n" }, "range_aware_register4": { "source_sha256": "a30e8c10d04f7806837b7362bac4a0f599f0d6d17735fc2e88198ca5dcb4e73d", "air_sha256": "0c7a861883616690e2eee973718d043cee24c1b4e5a36934531dc7b4d25d3a17", "conditional_branches": 2, "scalar_device_memory_operations": 12, "vector_device_memory_operations": 0, "textual_air": "; ModuleID = '/var/folders/x7/hs9bdmg17g167js6kt76dlxh0000gn/T/metile-tiling-air-report-dh59nkto/float16_32x1024_range_aware_register4.metal'\nsource_filename = \"/var/folders/x7/hs9bdmg17g167js6kt76dlxh0000gn/T/metile-tiling-air-report-dh59nkto/float16_32x1024_range_aware_register4.metal\"\ntarget datalayout = \"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-n8:16:32\"\ntarget triple = \"air64_v28-apple-macosx26.0.0\"\n\n@_ZZ22mtile_rmsnorm_registerPU9MTLdeviceKDhS0_PU9MTLdeviceDhRU11MTLconstantKfDv3_jjjjE26_metile_register_reduction = internal unnamed_addr addrspace(3) global [8 x float] undef, align 4\n\n; Function Attrs: convergent mustprogress nounwind willreturn\ndefine void @mtile_rmsnorm_register(half addrspace(1)* nocapture noundef readonly \"air-buffer-no-alias\" %0, half addrspace(1)* nocapture noundef readonly \"air-buffer-no-alias\" %1, half addrspace(1)* nocapture noundef writeonly \"air-buffer-no-alias\" %2, float addrspace(2)* nocapture noundef readonly align 4 dereferenceable(4) \"air-buffer-no-alias\" %3, <3 x i32> noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7) local_unnamed_addr #0 {\n %9 = extractelement <3 x i32> %4, i64 0\n %10 = shl nsw i32 %9, 10\n %11 = and i32 %5, 255\n %12 = or i32 %11, 256\n %13 = or i32 %11, 512\n %14 = or i32 %11, 768\n %15 = or i32 %10, %11\n %16 = or i32 %12, %10\n %17 = or i32 %13, %10\n %18 = or i32 %14, %10\n %19 = sext i32 %15 to i64\n %20 = getelementptr inbounds half, half addrspace(1)* %0, i64 %19\n %21 = load half, half addrspace(1)* %20, align 2, !tbaa !27, !alias.scope !31, !noalias !34\n %22 = sext i32 %16 to i64\n %23 = getelementptr inbounds half, half addrspace(1)* %0, i64 %22\n %24 = load half, half addrspace(1)* %23, align 2, !tbaa !27, !alias.scope !31, !noalias !34\n %25 = sext i32 %17 to i64\n %26 = getelementptr inbounds half, half addrspace(1)* %0, i64 %25\n %27 = load half, half addrspace(1)* %26, align 2, !tbaa !27, !alias.scope !31, !noalias !34\n %28 = sext i32 %18 to i64\n %29 = getelementptr inbounds half, half addrspace(1)* %0, i64 %28\n %30 = load half, half addrspace(1)* %29, align 2, !tbaa !27, !alias.scope !31, !noalias !34\n %31 = fpext half %21 to float\n %32 = fpext half %24 to float\n %33 = fpext half %27 to float\n %34 = fpext half %30 to float\n %35 = fmul fast float %31, %31\n %36 = fmul fast float %32, %32\n %37 = fmul fast float %33, %33\n %38 = fmul fast float %34, %34\n %39 = fadd fast float %36, %35\n %40 = fadd fast float %39, %37\n %41 = fadd fast float %40, %38\n %42 = tail call fast float @air.simd_sum.f32(float %41) #3\n %43 = icmp eq i32 %7, 0\n br i1 %43, label %44, label %47\n\n44: ; preds = %8\n %45 = zext i32 %6 to i64\n %46 = getelementptr inbounds [8 x float], [8 x float] addrspace(3)* @_ZZ22mtile_rmsnorm_registerPU9MTLdeviceKDhS0_PU9MTLdeviceDhRU11MTLconstantKfDv3_jjjjE26_metile_register_reduction, i64 0, i64 %45\n store float %42, float addrspace(3)* %46, align 4, !tbaa !38\n br label %47\n\n47: ; preds = %44, %8\n tail call void @air.wg.barrier(i32 2, i32 1) #3\n %48 = icmp ult i32 %7, 8\n br i1 %48, label %49, label %53\n\n49: ; preds = %47\n %50 = zext i32 %7 to i64\n %51 = getelementptr inbounds [8 x float], [8 x float] addrspace(3)* @_ZZ22mtile_rmsnorm_registerPU9MTLdeviceKDhS0_PU9MTLdeviceDhRU11MTLconstantKfDv3_jjjjE26_metile_register_reduction, i64 0, i64 %50\n %52 = load float, float addrspace(3)* %51, align 4, !tbaa !38\n br label %53\n\n53: ; preds = %47, %49\n %54 = phi fast float [ %52, %49 ], [ 0.000000e+00, %47 ]\n %55 = tail call fast float @air.simd_sum.f32(float %54) #3\n %56 = fmul fast float %55, 0x3F50000000000000\n %57 = load float, float addrspace(2)* %3, align 4, !tbaa !38, !alias.scope !40, !noalias !41\n %58 = fadd fast float %56, %57\n %59 = tail call fast float @air.fast_sqrt.f32(float %58) #4\n %60 = fdiv fast float 1.000000e+00, %59\n %61 = zext i32 %11 to i64\n %62 = getelementptr inbounds half, half addrspace(1)* %1, i64 %61\n %63 = load half, half addrspace(1)* %62, align 2, !tbaa !27, !alias.scope !42, !noalias !43\n %64 = zext i32 %12 to i64\n %65 = getelementptr inbounds half, half addrspace(1)* %1, i64 %64\n %66 = load half, half addrspace(1)* %65, align 2, !tbaa !27, !alias.scope !42, !noalias !43\n %67 = zext i32 %13 to i64\n %68 = getelementptr inbounds half, half addrspace(1)* %1, i64 %67\n %69 = load half, half addrspace(1)* %68, align 2, !tbaa !27, !alias.scope !42, !noalias !43\n %70 = zext i32 %14 to i64\n %71 = getelementptr inbounds half, half addrspace(1)* %1, i64 %70\n %72 = load half, half addrspace(1)* %71, align 2, !tbaa !27, !alias.scope !42, !noalias !43\n %73 = fpext half %66 to float\n %74 = fpext half %69 to float\n %75 = fpext half %72 to float\n %76 = fmul fast float %60, %32\n %77 = fmul fast float %60, %33\n %78 = fmul fast float %60, %34\n %79 = fmul fast float %76, %73\n %80 = fmul fast float %77, %74\n %81 = fmul fast float %78, %75\n %82 = fmul fast float %60, %31\n %83 = fpext half %63 to float\n %84 = fmul fast float %82, %83\n %85 = fptrunc float %84 to half\n %86 = getelementptr inbounds half, half addrspace(1)* %2, i64 %19\n store half %85, half addrspace(1)* %86, align 2, !tbaa !27, !alias.scope !44, !noalias !45\n %87 = fptrunc float %79 to half\n %88 = getelementptr inbounds half, half addrspace(1)* %2, i64 %22\n store half %87, half addrspace(1)* %88, align 2, !tbaa !27, !alias.scope !44, !noalias !45\n %89 = fptrunc float %80 to half\n %90 = getelementptr inbounds half, half addrspace(1)* %2, i64 %25\n store half %89, half addrspace(1)* %90, align 2, !tbaa !27, !alias.scope !44, !noalias !45\n %91 = fptrunc float %81 to half\n %92 = getelementptr inbounds half, half addrspace(1)* %2, i64 %28\n store half %91, half addrspace(1)* %92, align 2, !tbaa !27, !alias.scope !44, !noalias !45\n ret void\n}\n\n; Function Attrs: convergent mustprogress nounwind willreturn\ndeclare void @air.wg.barrier(i32, i32) local_unnamed_addr #1\n\n; Function Attrs: mustprogress nofree nosync nounwind readnone willreturn\ndeclare float @air.fast_sqrt.f32(float) local_unnamed_addr #2\n\n; Function Attrs: convergent mustprogress nounwind willreturn\ndeclare float @air.simd_sum.f32(float) local_unnamed_addr #1\n\nattributes #0 = { convergent mustprogress nounwind willreturn \"approx-func-fp-math\"=\"true\" \"frame-pointer\"=\"all\" \"min-legal-vector-width\"=\"96\" \"no-builtins\" \"no-infs-fp-math\"=\"true\" \"no-nans-fp-math\"=\"true\" \"no-signed-zeros-fp-math\"=\"true\" \"no-trapping-math\"=\"true\" \"stack-protector-buffer-size\"=\"8\" \"unsafe-fp-math\"=\"true\" }\nattributes #1 = { convergent mustprogress nounwind willreturn }\nattributes #2 = { mustprogress nofree nosync nounwind readnone willreturn }\nattributes #3 = { convergent nounwind willreturn }\nattributes #4 = { nounwind readnone willreturn }\n\n!llvm.module.flags = !{!0, !1, !2, !3, !4, !5, !6, !7, !8}\n!air.kernel = !{!9}\n!air.compile_options = !{!20, !21, !22}\n!llvm.ident = !{!23}\n!air.version = !{!24}\n!air.language_version = !{!25}\n!air.source_file_name = !{!26}\n\n!0 = !{i32 2, !\"SDK Version\", [2 x i32] [i32 26, i32 2]}\n!1 = !{i32 1, !\"wchar_size\", i32 4}\n!2 = !{i32 7, !\"frame-pointer\", i32 2}\n!3 = !{i32 7, !\"air.max_device_buffers\", i32 31}\n!4 = !{i32 7, !\"air.max_constant_buffers\", i32 31}\n!5 = !{i32 7, !\"air.max_threadgroup_buffers\", i32 31}\n!6 = !{i32 7, !\"air.max_textures\", i32 128}\n!7 = !{i32 7, !\"air.max_read_write_textures\", i32 8}\n!8 = !{i32 7, !\"air.max_samplers\", i32 16}\n!9 = !{void (half addrspace(1)*, half addrspace(1)*, half addrspace(1)*, float addrspace(2)*, <3 x i32>, i32, i32, i32)* @mtile_rmsnorm_register, !10, !11}\n!10 = !{}\n!11 = !{!12, !13, !14, !15, !16, !17, !18, !19}\n!12 = !{i32 0, !\"air.buffer\", !\"air.location_index\", i32 0, i32 1, !\"air.read\", !\"air.address_space\", i32 1, !\"air.arg_type_size\", i32 2, !\"air.arg_type_align_size\", i32 2, !\"air.arg_type_name\", !\"half\", !\"air.arg_name\", !\"X\"}\n!13 = !{i32 1, !\"air.buffer\", !\"air.location_index\", i32 1, i32 1, !\"air.read\", !\"air.address_space\", i32 1, !\"air.arg_type_size\", i32 2, !\"air.arg_type_align_size\", i32 2, !\"air.arg_type_name\", !\"half\", !\"air.arg_name\", !\"W\"}\n!14 = !{i32 2, !\"air.buffer\", !\"air.location_index\", i32 2, i32 1, !\"air.read_write\", !\"air.address_space\", i32 1, !\"air.arg_type_size\", i32 2, !\"air.arg_type_align_size\", i32 2, !\"air.arg_type_name\", !\"half\", !\"air.arg_name\", !\"Out\"}\n!15 = !{i32 3, !\"air.buffer\", !\"air.buffer_size\", i32 4, !\"air.location_index\", i32 3, i32 1, !\"air.read\", !\"air.address_space\", i32 2, !\"air.arg_type_size\", i32 4, !\"air.arg_type_align_size\", i32 4, !\"air.arg_type_name\", !\"float\", !\"air.arg_name\", !\"eps\"}\n!16 = !{i32 4, !\"air.threadgroup_position_in_grid\", !\"air.arg_type_name\", !\"uint3\", !\"air.arg_name\", !\"tgp_id\"}\n!17 = !{i32 5, !\"air.thread_index_in_threadgroup\", !\"air.arg_type_name\", !\"uint\", !\"air.arg_name\", !\"lid\"}\n!18 = !{i32 6, !\"air.simdgroup_index_in_threadgroup\", !\"air.arg_type_name\", !\"uint\", !\"air.arg_name\", !\"sgid\"}\n!19 = !{i32 7, !\"air.thread_index_in_simdgroup\", !\"air.arg_type_name\", !\"uint\", !\"air.arg_name\", !\"slid\"}\n!20 = !{!\"air.compile.denorms_disable\"}\n!21 = !{!\"air.compile.fast_math_enable\"}\n!22 = !{!\"air.compile.framebuffer_fetch_enable\"}\n!23 = !{!\"Apple metal version 32023.864 (metalfe-32023.864)\"}\n!24 = !{i32 2, i32 8, i32 0}\n!25 = !{!\"Metal\", i32 4, i32 0, i32 0}\n!26 = !{!\"/private/var/folders/x7/hs9bdmg17g167js6kt76dlxh0000gn/T/metile-tiling-air-report-dh59nkto/float16_32x1024_range_aware_register4.metal\"}\n!27 = !{!28, !28, i64 0}\n!28 = !{!\"half\", !29, i64 0}\n!29 = !{!\"omnipotent char\", !30, i64 0}\n!30 = !{!\"Simple C++ TBAA\"}\n!31 = !{!32}\n!32 = distinct !{!32, !33, !\"air-alias-scope-arg(0)\"}\n!33 = distinct !{!33, !\"air-alias-scopes(mtile_rmsnorm_register)\"}\n!34 = !{!35, !36, !37}\n!35 = distinct !{!35, !33, !\"air-alias-scope-arg(1)\"}\n!36 = distinct !{!36, !33, !\"air-alias-scope-arg(2)\"}\n!37 = distinct !{!37, !33, !\"air-alias-scope-arg(3)\"}\n!38 = !{!39, !39, i64 0}\n!39 = !{!\"float\", !29, i64 0}\n!40 = !{!37}\n!41 = !{!32, !35, !36}\n!42 = !{!35}\n!43 = !{!32, !36, !37}\n!44 = !{!36}\n!45 = !{!32, !35, !37}\n" } } }, { "name": "float32_32x1009", "dtype": "float32", "width": 1009, "batches": 32, "arms": { "frozen_register4": { "source_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "air_sha256": "87dc9bc6a5f43513ebb3321a54ef408fc56242feee7db82608fd711cfdd465b2", "conditional_branches": 14, "scalar_device_memory_operations": 12, "vector_device_memory_operations": 0, "textual_air": "; ModuleID = '/var/folders/x7/hs9bdmg17g167js6kt76dlxh0000gn/T/metile-tiling-air-report-dh59nkto/float32_32x1009_frozen_register4.metal'\nsource_filename = \"/var/folders/x7/hs9bdmg17g167js6kt76dlxh0000gn/T/metile-tiling-air-report-dh59nkto/float32_32x1009_frozen_register4.metal\"\ntarget datalayout = \"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-n8:16:32\"\ntarget triple = \"air64_v28-apple-macosx26.0.0\"\n\n@_ZZ22mtile_rmsnorm_registerPU9MTLdeviceKfS0_PU9MTLdevicefRU11MTLconstantKfDv3_jjjjE26_metile_register_reduction = internal unnamed_addr addrspace(3) global [8 x float] undef, align 4\n\n; Function Attrs: convergent mustprogress nounwind willreturn\ndefine void @mtile_rmsnorm_register(float addrspace(1)* nocapture noundef readonly \"air-buffer-no-alias\" %0, float addrspace(1)* nocapture noundef readonly \"air-buffer-no-alias\" %1, float addrspace(1)* nocapture noundef writeonly \"air-buffer-no-alias\" %2, float addrspace(2)* nocapture noundef readonly align 4 dereferenceable(4) \"air-buffer-no-alias\" %3, <3 x i32> noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7) local_unnamed_addr #0 {\n %9 = extractelement <3 x i32> %4, i64 0\n %10 = mul nsw i32 %9, 1009\n %11 = add i32 %5, 256\n %12 = add i32 %5, 512\n %13 = add i32 %5, 768\n %14 = icmp slt i32 %5, 1009\n %15 = xor i32 %5, -1\n %16 = lshr i32 %15, 31\n %17 = zext i1 %14 to i32\n %18 = and i32 %16, %17\n %19 = icmp ne i32 %18, 0\n %20 = icmp ult i32 %11, 1009\n %21 = icmp ult i32 %12, 1009\n %22 = icmp ult i32 %13, 1009\n %23 = add nsw i32 %10, %5\n %24 = add nsw i32 %10, %11\n %25 = add nsw i32 %10, %12\n %26 = add nsw i32 %10, %13\n br i1 %19, label %27, label %31\n\n27: ; preds = %8\n %28 = sext i32 %23 to i64\n %29 = getelementptr inbounds float, float addrspace(1)* %0, i64 %28\n %30 = load float, float addrspace(1)* %29, align 4, !tbaa !27, !alias.scope !31, !noalias !34\n br label %31\n\n31: ; preds = %8, %27\n %32 = phi fast float [ %30, %27 ], [ 0.000000e+00, %8 ]\n br i1 %20, label %33, label %37\n\n33: ; preds = %31\n %34 = sext i32 %24 to i64\n %35 = getelementptr inbounds float, float addrspace(1)* %0, i64 %34\n %36 = load float, float addrspace(1)* %35, align 4, !tbaa !27, !alias.scope !31, !noalias !34\n br label %37\n\n37: ; preds = %31, %33\n %38 = phi fast float [ %36, %33 ], [ 0.000000e+00, %31 ]\n br i1 %21, label %39, label %43\n\n39: ; preds = %37\n %40 = sext i32 %25 to i64\n %41 = getelementptr inbounds float, float addrspace(1)* %0, i64 %40\n %42 = load float, float addrspace(1)* %41, align 4, !tbaa !27, !alias.scope !31, !noalias !34\n br label %43\n\n43: ; preds = %37, %39\n %44 = phi fast float [ %42, %39 ], [ 0.000000e+00, %37 ]\n br i1 %22, label %45, label %49\n\n45: ; preds = %43\n %46 = sext i32 %26 to i64\n %47 = getelementptr inbounds float, float addrspace(1)* %0, i64 %46\n %48 = load float, float addrspace(1)* %47, align 4, !tbaa !27, !alias.scope !31, !noalias !34\n br label %49\n\n49: ; preds = %43, %45\n %50 = phi fast float [ %48, %45 ], [ 0.000000e+00, %43 ]\n %51 = fmul fast float %32, %32\n %52 = fmul fast float %38, %38\n %53 = fmul fast float %44, %44\n %54 = fmul fast float %50, %50\n %55 = fadd fast float %52, %51\n %56 = fadd fast float %55, %53\n %57 = fadd fast float %56, %54\n %58 = tail call fast float @air.simd_sum.f32(float %57) #3\n %59 = icmp eq i32 %7, 0\n br i1 %59, label %60, label %63\n\n60: ; preds = %49\n %61 = zext i32 %6 to i64\n %62 = getelementptr inbounds [8 x float], [8 x float] addrspace(3)* @_ZZ22mtile_rmsnorm_registerPU9MTLdeviceKfS0_PU9MTLdevicefRU11MTLconstantKfDv3_jjjjE26_metile_register_reduction, i64 0, i64 %61\n store float %58, float addrspace(3)* %62, align 4, !tbaa !27\n br label %63\n\n63: ; preds = %60, %49\n tail call void @air.wg.barrier(i32 2, i32 1) #3\n %64 = icmp ult i32 %7, 8\n br i1 %64, label %65, label %69\n\n65: ; preds = %63\n %66 = zext i32 %7 to i64\n %67 = getelementptr inbounds [8 x float], [8 x float] addrspace(3)* @_ZZ22mtile_rmsnorm_registerPU9MTLdeviceKfS0_PU9MTLdevicefRU11MTLconstantKfDv3_jjjjE26_metile_register_reduction, i64 0, i64 %66\n %68 = load float, float addrspace(3)* %67, align 4, !tbaa !27\n br label %69\n\n69: ; preds = %63, %65\n %70 = phi fast float [ %68, %65 ], [ 0.000000e+00, %63 ]\n %71 = tail call fast float @air.simd_sum.f32(float %70) #3\n %72 = fmul fast float %71, 0x3F503CE460000000\n %73 = load float, float addrspace(2)* %3, align 4, !tbaa !27, !alias.scope !38, !noalias !39\n %74 = fadd fast float %72, %73\n %75 = tail call fast float @air.fast_sqrt.f32(float %74) #4\n %76 = fdiv fast float 1.000000e+00, %75\n br i1 %19, label %77, label %81\n\n77: ; preds = %69\n %78 = sext i32 %5 to i64\n %79 = getelementptr inbounds float, float addrspace(1)* %1, i64 %78\n %80 = load float, float addrspace(1)* %79, align 4, !tbaa !27, !alias.scope !40, !noalias !41\n br label %81\n\n81: ; preds = %69, %77\n %82 = phi fast float [ %80, %77 ], [ 0.000000e+00, %69 ]\n br i1 %20, label %83, label %87\n\n83: ; preds = %81\n %84 = zext i32 %11 to i64\n %85 = getelementptr inbounds float, float addrspace(1)* %1, i64 %84\n %86 = load float, float addrspace(1)* %85, align 4, !tbaa !27, !alias.scope !40, !noalias !41\n br label %87\n\n87: ; preds = %81, %83\n %88 = phi fast float [ %86, %83 ], [ 0.000000e+00, %81 ]\n br i1 %21, label %89, label %93\n\n89: ; preds = %87\n %90 = zext i32 %12 to i64\n %91 = getelementptr inbounds float, float addrspace(1)* %1, i64 %90\n %92 = load float, float addrspace(1)* %91, align 4, !tbaa !27, !alias.scope !40, !noalias !41\n br label %93\n\n93: ; preds = %87, %89\n %94 = phi fast float [ %92, %89 ], [ 0.000000e+00, %87 ]\n br i1 %22, label %95, label %99\n\n95: ; preds = %93\n %96 = zext i32 %13 to i64\n %97 = getelementptr inbounds float, float addrspace(1)* %1, i64 %96\n %98 = load float, float addrspace(1)* %97, align 4, !tbaa !27, !alias.scope !40, !noalias !41\n br label %99\n\n99: ; preds = %93, %95\n %100 = phi fast float [ %98, %95 ], [ 0.000000e+00, %93 ]\n %101 = fmul fast float %76, %38\n %102 = fmul fast float %76, %44\n %103 = fmul fast float %76, %50\n %104 = fmul fast float %101, %88\n %105 = fmul fast float %102, %94\n %106 = fmul fast float %103, %100\n br i1 %19, label %107, label %112\n\n107: ; preds = %99\n %108 = sext i32 %23 to i64\n %109 = getelementptr inbounds float, float addrspace(1)* %2, i64 %108\n %110 = fmul fast float %76, %32\n %111 = fmul fast float %110, %82\n store float %111, float addrspace(1)* %109, align 4, !tbaa !27, !alias.scope !42, !noalias !43\n br label %112\n\n112: ; preds = %107, %99\n br i1 %20, label %113, label %116\n\n113: ; preds = %112\n %114 = sext i32 %24 to i64\n %115 = getelementptr inbounds float, float addrspace(1)* %2, i64 %114\n store float %104, float addrspace(1)* %115, align 4, !tbaa !27, !alias.scope !42, !noalias !43\n br label %116\n\n116: ; preds = %113, %112\n br i1 %21, label %117, label %120\n\n117: ; preds = %116\n %118 = sext i32 %25 to i64\n %119 = getelementptr inbounds float, float addrspace(1)* %2, i64 %118\n store float %105, float addrspace(1)* %119, align 4, !tbaa !27, !alias.scope !42, !noalias !43\n br label %120\n\n120: ; preds = %117, %116\n br i1 %22, label %121, label %124\n\n121: ; preds = %120\n %122 = sext i32 %26 to i64\n %123 = getelementptr inbounds float, float addrspace(1)* %2, i64 %122\n store float %106, float addrspace(1)* %123, align 4, !tbaa !27, !alias.scope !42, !noalias !43\n br label %124\n\n124: ; preds = %121, %120\n ret void\n}\n\n; Function Attrs: convergent mustprogress nounwind willreturn\ndeclare void @air.wg.barrier(i32, i32) local_unnamed_addr #1\n\n; Function Attrs: mustprogress nofree nosync nounwind readnone willreturn\ndeclare float @air.fast_sqrt.f32(float) local_unnamed_addr #2\n\n; Function Attrs: convergent mustprogress nounwind willreturn\ndeclare float @air.simd_sum.f32(float) local_unnamed_addr #1\n\nattributes #0 = { convergent mustprogress nounwind willreturn \"approx-func-fp-math\"=\"true\" \"frame-pointer\"=\"all\" \"min-legal-vector-width\"=\"96\" \"no-builtins\" \"no-infs-fp-math\"=\"true\" \"no-nans-fp-math\"=\"true\" \"no-signed-zeros-fp-math\"=\"true\" \"no-trapping-math\"=\"true\" \"stack-protector-buffer-size\"=\"8\" \"unsafe-fp-math\"=\"true\" }\nattributes #1 = { convergent mustprogress nounwind willreturn }\nattributes #2 = { mustprogress nofree nosync nounwind readnone willreturn }\nattributes #3 = { convergent nounwind willreturn }\nattributes #4 = { nounwind readnone willreturn }\n\n!llvm.module.flags = !{!0, !1, !2, !3, !4, !5, !6, !7, !8}\n!air.kernel = !{!9}\n!air.compile_options = !{!20, !21, !22}\n!llvm.ident = !{!23}\n!air.version = !{!24}\n!air.language_version = !{!25}\n!air.source_file_name = !{!26}\n\n!0 = !{i32 2, !\"SDK Version\", [2 x i32] [i32 26, i32 2]}\n!1 = !{i32 1, !\"wchar_size\", i32 4}\n!2 = !{i32 7, !\"frame-pointer\", i32 2}\n!3 = !{i32 7, !\"air.max_device_buffers\", i32 31}\n!4 = !{i32 7, !\"air.max_constant_buffers\", i32 31}\n!5 = !{i32 7, !\"air.max_threadgroup_buffers\", i32 31}\n!6 = !{i32 7, !\"air.max_textures\", i32 128}\n!7 = !{i32 7, !\"air.max_read_write_textures\", i32 8}\n!8 = !{i32 7, !\"air.max_samplers\", i32 16}\n!9 = !{void (float addrspace(1)*, float addrspace(1)*, float addrspace(1)*, float addrspace(2)*, <3 x i32>, i32, i32, i32)* @mtile_rmsnorm_register, !10, !11}\n!10 = !{}\n!11 = !{!12, !13, !14, !15, !16, !17, !18, !19}\n!12 = !{i32 0, !\"air.buffer\", !\"air.location_index\", i32 0, i32 1, !\"air.read\", !\"air.address_space\", i32 1, !\"air.arg_type_size\", i32 4, !\"air.arg_type_align_size\", i32 4, !\"air.arg_type_name\", !\"float\", !\"air.arg_name\", !\"X\"}\n!13 = !{i32 1, !\"air.buffer\", !\"air.location_index\", i32 1, i32 1, !\"air.read\", !\"air.address_space\", i32 1, !\"air.arg_type_size\", i32 4, !\"air.arg_type_align_size\", i32 4, !\"air.arg_type_name\", !\"float\", !\"air.arg_name\", !\"W\"}\n!14 = !{i32 2, !\"air.buffer\", !\"air.location_index\", i32 2, i32 1, !\"air.read_write\", !\"air.address_space\", i32 1, !\"air.arg_type_size\", i32 4, !\"air.arg_type_align_size\", i32 4, !\"air.arg_type_name\", !\"float\", !\"air.arg_name\", !\"Out\"}\n!15 = !{i32 3, !\"air.buffer\", !\"air.buffer_size\", i32 4, !\"air.location_index\", i32 3, i32 1, !\"air.read\", !\"air.address_space\", i32 2, !\"air.arg_type_size\", i32 4, !\"air.arg_type_align_size\", i32 4, !\"air.arg_type_name\", !\"float\", !\"air.arg_name\", !\"eps\"}\n!16 = !{i32 4, !\"air.threadgroup_position_in_grid\", !\"air.arg_type_name\", !\"uint3\", !\"air.arg_name\", !\"tgp_id\"}\n!17 = !{i32 5, !\"air.thread_index_in_threadgroup\", !\"air.arg_type_name\", !\"uint\", !\"air.arg_name\", !\"lid\"}\n!18 = !{i32 6, !\"air.simdgroup_index_in_threadgroup\", !\"air.arg_type_name\", !\"uint\", !\"air.arg_name\", !\"sgid\"}\n!19 = !{i32 7, !\"air.thread_index_in_simdgroup\", !\"air.arg_type_name\", !\"uint\", !\"air.arg_name\", !\"slid\"}\n!20 = !{!\"air.compile.denorms_disable\"}\n!21 = !{!\"air.compile.fast_math_enable\"}\n!22 = !{!\"air.compile.framebuffer_fetch_enable\"}\n!23 = !{!\"Apple metal version 32023.864 (metalfe-32023.864)\"}\n!24 = !{i32 2, i32 8, i32 0}\n!25 = !{!\"Metal\", i32 4, i32 0, i32 0}\n!26 = !{!\"/private/var/folders/x7/hs9bdmg17g167js6kt76dlxh0000gn/T/metile-tiling-air-report-dh59nkto/float32_32x1009_frozen_register4.metal\"}\n!27 = !{!28, !28, i64 0}\n!28 = !{!\"float\", !29, i64 0}\n!29 = !{!\"omnipotent char\", !30, i64 0}\n!30 = !{!\"Simple C++ TBAA\"}\n!31 = !{!32}\n!32 = distinct !{!32, !33, !\"air-alias-scope-arg(0)\"}\n!33 = distinct !{!33, !\"air-alias-scopes(mtile_rmsnorm_register)\"}\n!34 = !{!35, !36, !37}\n!35 = distinct !{!35, !33, !\"air-alias-scope-arg(1)\"}\n!36 = distinct !{!36, !33, !\"air-alias-scope-arg(2)\"}\n!37 = distinct !{!37, !33, !\"air-alias-scope-arg(3)\"}\n!38 = !{!37}\n!39 = !{!32, !35, !36}\n!40 = !{!35}\n!41 = !{!32, !36, !37}\n!42 = !{!36}\n!43 = !{!32, !35, !37}\n" }, "range_aware_register4": { "source_sha256": "c1d33e27fc56debd55c6a508dc39b24b01c51c4f01d8ebe463b73c7d94ad343d", "air_sha256": "81ec8eef891302e535eb779ba5239fe253e95230a41375f55dfa902beb20a909", "conditional_branches": 5, "scalar_device_memory_operations": 12, "vector_device_memory_operations": 0, "textual_air": "; ModuleID = '/var/folders/x7/hs9bdmg17g167js6kt76dlxh0000gn/T/metile-tiling-air-report-dh59nkto/float32_32x1009_range_aware_register4.metal'\nsource_filename = \"/var/folders/x7/hs9bdmg17g167js6kt76dlxh0000gn/T/metile-tiling-air-report-dh59nkto/float32_32x1009_range_aware_register4.metal\"\ntarget datalayout = \"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-n8:16:32\"\ntarget triple = \"air64_v28-apple-macosx26.0.0\"\n\n@_ZZ22mtile_rmsnorm_registerPU9MTLdeviceKfS0_PU9MTLdevicefRU11MTLconstantKfDv3_jjjjE26_metile_register_reduction = internal unnamed_addr addrspace(3) global [8 x float] undef, align 4\n\n; Function Attrs: convergent mustprogress nounwind willreturn\ndefine void @mtile_rmsnorm_register(float addrspace(1)* nocapture noundef readonly \"air-buffer-no-alias\" %0, float addrspace(1)* nocapture noundef readonly \"air-buffer-no-alias\" %1, float addrspace(1)* nocapture noundef writeonly \"air-buffer-no-alias\" %2, float addrspace(2)* nocapture noundef readonly align 4 dereferenceable(4) \"air-buffer-no-alias\" %3, <3 x i32> noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7) local_unnamed_addr #0 {\n %9 = extractelement <3 x i32> %4, i64 0\n %10 = mul nsw i32 %9, 1009\n %11 = and i32 %5, 255\n %12 = or i32 %11, 256\n %13 = or i32 %11, 512\n %14 = or i32 %11, 768\n %15 = icmp ult i32 %14, 1009\n %16 = add nsw i32 %10, %11\n %17 = add nsw i32 %12, %10\n %18 = add nsw i32 %13, %10\n %19 = add nsw i32 %14, %10\n %20 = sext i32 %16 to i64\n %21 = getelementptr inbounds float, float addrspace(1)* %0, i64 %20\n %22 = load float, float addrspace(1)* %21, align 4, !tbaa !27, !alias.scope !31, !noalias !34\n %23 = sext i32 %17 to i64\n %24 = getelementptr inbounds float, float addrspace(1)* %0, i64 %23\n %25 = load float, float addrspace(1)* %24, align 4, !tbaa !27, !alias.scope !31, !noalias !34\n %26 = sext i32 %18 to i64\n %27 = getelementptr inbounds float, float addrspace(1)* %0, i64 %26\n %28 = load float, float addrspace(1)* %27, align 4, !tbaa !27, !alias.scope !31, !noalias !34\n br i1 %15, label %29, label %33\n\n29: ; preds = %8\n %30 = sext i32 %19 to i64\n %31 = getelementptr inbounds float, float addrspace(1)* %0, i64 %30\n %32 = load float, float addrspace(1)* %31, align 4, !tbaa !27, !alias.scope !31, !noalias !34\n br label %33\n\n33: ; preds = %8, %29\n %34 = phi fast float [ %32, %29 ], [ 0.000000e+00, %8 ]\n %35 = fmul fast float %22, %22\n %36 = fmul fast float %25, %25\n %37 = fmul fast float %28, %28\n %38 = fmul fast float %34, %34\n %39 = fadd fast float %36, %35\n %40 = fadd fast float %39, %37\n %41 = fadd fast float %40, %38\n %42 = tail call fast float @air.simd_sum.f32(float %41) #3\n %43 = icmp eq i32 %7, 0\n br i1 %43, label %44, label %47\n\n44: ; preds = %33\n %45 = zext i32 %6 to i64\n %46 = getelementptr inbounds [8 x float], [8 x float] addrspace(3)* @_ZZ22mtile_rmsnorm_registerPU9MTLdeviceKfS0_PU9MTLdevicefRU11MTLconstantKfDv3_jjjjE26_metile_register_reduction, i64 0, i64 %45\n store float %42, float addrspace(3)* %46, align 4, !tbaa !27\n br label %47\n\n47: ; preds = %44, %33\n tail call void @air.wg.barrier(i32 2, i32 1) #3\n %48 = icmp ult i32 %7, 8\n br i1 %48, label %49, label %53\n\n49: ; preds = %47\n %50 = zext i32 %7 to i64\n %51 = getelementptr inbounds [8 x float], [8 x float] addrspace(3)* @_ZZ22mtile_rmsnorm_registerPU9MTLdeviceKfS0_PU9MTLdevicefRU11MTLconstantKfDv3_jjjjE26_metile_register_reduction, i64 0, i64 %50\n %52 = load float, float addrspace(3)* %51, align 4, !tbaa !27\n br label %53\n\n53: ; preds = %47, %49\n %54 = phi fast float [ %52, %49 ], [ 0.000000e+00, %47 ]\n %55 = tail call fast float @air.simd_sum.f32(float %54) #3\n %56 = fmul fast float %55, 0x3F503CE460000000\n %57 = load float, float addrspace(2)* %3, align 4, !tbaa !27, !alias.scope !38, !noalias !39\n %58 = fadd fast float %56, %57\n %59 = tail call fast float @air.fast_sqrt.f32(float %58) #4\n %60 = fdiv fast float 1.000000e+00, %59\n %61 = zext i32 %11 to i64\n %62 = getelementptr inbounds float, float addrspace(1)* %1, i64 %61\n %63 = load float, float addrspace(1)* %62, align 4, !tbaa !27, !alias.scope !40, !noalias !41\n %64 = zext i32 %12 to i64\n %65 = getelementptr inbounds float, float addrspace(1)* %1, i64 %64\n %66 = load float, float addrspace(1)* %65, align 4, !tbaa !27, !alias.scope !40, !noalias !41\n %67 = zext i32 %13 to i64\n %68 = getelementptr inbounds float, float addrspace(1)* %1, i64 %67\n %69 = load float, float addrspace(1)* %68, align 4, !tbaa !27, !alias.scope !40, !noalias !41\n br i1 %15, label %70, label %74\n\n70: ; preds = %53\n %71 = zext i32 %14 to i64\n %72 = getelementptr inbounds float, float addrspace(1)* %1, i64 %71\n %73 = load float, float addrspace(1)* %72, align 4, !tbaa !27, !alias.scope !40, !noalias !41\n br label %74\n\n74: ; preds = %53, %70\n %75 = phi fast float [ %73, %70 ], [ 0.000000e+00, %53 ]\n %76 = fmul fast float %60, %25\n %77 = fmul fast float %60, %28\n %78 = fmul fast float %76, %66\n %79 = fmul fast float %77, %69\n %80 = fmul fast float %60, %22\n %81 = fmul fast float %80, %63\n %82 = getelementptr inbounds float, float addrspace(1)* %2, i64 %20\n store float %81, float addrspace(1)* %82, align 4, !tbaa !27, !alias.scope !42, !noalias !43\n %83 = getelementptr inbounds float, float addrspace(1)* %2, i64 %23\n store float %78, float addrspace(1)* %83, align 4, !tbaa !27, !alias.scope !42, !noalias !43\n %84 = getelementptr inbounds float, float addrspace(1)* %2, i64 %26\n store float %79, float addrspace(1)* %84, align 4, !tbaa !27, !alias.scope !42, !noalias !43\n br i1 %15, label %85, label %90\n\n85: ; preds = %74\n %86 = sext i32 %19 to i64\n %87 = getelementptr inbounds float, float addrspace(1)* %2, i64 %86\n %88 = fmul fast float %60, %34\n %89 = fmul fast float %88, %75\n store float %89, float addrspace(1)* %87, align 4, !tbaa !27, !alias.scope !42, !noalias !43\n br label %90\n\n90: ; preds = %85, %74\n ret void\n}\n\n; Function Attrs: convergent mustprogress nounwind willreturn\ndeclare void @air.wg.barrier(i32, i32) local_unnamed_addr #1\n\n; Function Attrs: mustprogress nofree nosync nounwind readnone willreturn\ndeclare float @air.fast_sqrt.f32(float) local_unnamed_addr #2\n\n; Function Attrs: convergent mustprogress nounwind willreturn\ndeclare float @air.simd_sum.f32(float) local_unnamed_addr #1\n\nattributes #0 = { convergent mustprogress nounwind willreturn \"approx-func-fp-math\"=\"true\" \"frame-pointer\"=\"all\" \"min-legal-vector-width\"=\"96\" \"no-builtins\" \"no-infs-fp-math\"=\"true\" \"no-nans-fp-math\"=\"true\" \"no-signed-zeros-fp-math\"=\"true\" \"no-trapping-math\"=\"true\" \"stack-protector-buffer-size\"=\"8\" \"unsafe-fp-math\"=\"true\" }\nattributes #1 = { convergent mustprogress nounwind willreturn }\nattributes #2 = { mustprogress nofree nosync nounwind readnone willreturn }\nattributes #3 = { convergent nounwind willreturn }\nattributes #4 = { nounwind readnone willreturn }\n\n!llvm.module.flags = !{!0, !1, !2, !3, !4, !5, !6, !7, !8}\n!air.kernel = !{!9}\n!air.compile_options = !{!20, !21, !22}\n!llvm.ident = !{!23}\n!air.version = !{!24}\n!air.language_version = !{!25}\n!air.source_file_name = !{!26}\n\n!0 = !{i32 2, !\"SDK Version\", [2 x i32] [i32 26, i32 2]}\n!1 = !{i32 1, !\"wchar_size\", i32 4}\n!2 = !{i32 7, !\"frame-pointer\", i32 2}\n!3 = !{i32 7, !\"air.max_device_buffers\", i32 31}\n!4 = !{i32 7, !\"air.max_constant_buffers\", i32 31}\n!5 = !{i32 7, !\"air.max_threadgroup_buffers\", i32 31}\n!6 = !{i32 7, !\"air.max_textures\", i32 128}\n!7 = !{i32 7, !\"air.max_read_write_textures\", i32 8}\n!8 = !{i32 7, !\"air.max_samplers\", i32 16}\n!9 = !{void (float addrspace(1)*, float addrspace(1)*, float addrspace(1)*, float addrspace(2)*, <3 x i32>, i32, i32, i32)* @mtile_rmsnorm_register, !10, !11}\n!10 = !{}\n!11 = !{!12, !13, !14, !15, !16, !17, !18, !19}\n!12 = !{i32 0, !\"air.buffer\", !\"air.location_index\", i32 0, i32 1, !\"air.read\", !\"air.address_space\", i32 1, !\"air.arg_type_size\", i32 4, !\"air.arg_type_align_size\", i32 4, !\"air.arg_type_name\", !\"float\", !\"air.arg_name\", !\"X\"}\n!13 = !{i32 1, !\"air.buffer\", !\"air.location_index\", i32 1, i32 1, !\"air.read\", !\"air.address_space\", i32 1, !\"air.arg_type_size\", i32 4, !\"air.arg_type_align_size\", i32 4, !\"air.arg_type_name\", !\"float\", !\"air.arg_name\", !\"W\"}\n!14 = !{i32 2, !\"air.buffer\", !\"air.location_index\", i32 2, i32 1, !\"air.read_write\", !\"air.address_space\", i32 1, !\"air.arg_type_size\", i32 4, !\"air.arg_type_align_size\", i32 4, !\"air.arg_type_name\", !\"float\", !\"air.arg_name\", !\"Out\"}\n!15 = !{i32 3, !\"air.buffer\", !\"air.buffer_size\", i32 4, !\"air.location_index\", i32 3, i32 1, !\"air.read\", !\"air.address_space\", i32 2, !\"air.arg_type_size\", i32 4, !\"air.arg_type_align_size\", i32 4, !\"air.arg_type_name\", !\"float\", !\"air.arg_name\", !\"eps\"}\n!16 = !{i32 4, !\"air.threadgroup_position_in_grid\", !\"air.arg_type_name\", !\"uint3\", !\"air.arg_name\", !\"tgp_id\"}\n!17 = !{i32 5, !\"air.thread_index_in_threadgroup\", !\"air.arg_type_name\", !\"uint\", !\"air.arg_name\", !\"lid\"}\n!18 = !{i32 6, !\"air.simdgroup_index_in_threadgroup\", !\"air.arg_type_name\", !\"uint\", !\"air.arg_name\", !\"sgid\"}\n!19 = !{i32 7, !\"air.thread_index_in_simdgroup\", !\"air.arg_type_name\", !\"uint\", !\"air.arg_name\", !\"slid\"}\n!20 = !{!\"air.compile.denorms_disable\"}\n!21 = !{!\"air.compile.fast_math_enable\"}\n!22 = !{!\"air.compile.framebuffer_fetch_enable\"}\n!23 = !{!\"Apple metal version 32023.864 (metalfe-32023.864)\"}\n!24 = !{i32 2, i32 8, i32 0}\n!25 = !{!\"Metal\", i32 4, i32 0, i32 0}\n!26 = !{!\"/private/var/folders/x7/hs9bdmg17g167js6kt76dlxh0000gn/T/metile-tiling-air-report-dh59nkto/float32_32x1009_range_aware_register4.metal\"}\n!27 = !{!28, !28, i64 0}\n!28 = !{!\"float\", !29, i64 0}\n!29 = !{!\"omnipotent char\", !30, i64 0}\n!30 = !{!\"Simple C++ TBAA\"}\n!31 = !{!32}\n!32 = distinct !{!32, !33, !\"air-alias-scope-arg(0)\"}\n!33 = distinct !{!33, !\"air-alias-scopes(mtile_rmsnorm_register)\"}\n!34 = !{!35, !36, !37}\n!35 = distinct !{!35, !33, !\"air-alias-scope-arg(1)\"}\n!36 = distinct !{!36, !33, !\"air-alias-scope-arg(2)\"}\n!37 = distinct !{!37, !33, !\"air-alias-scope-arg(3)\"}\n!38 = !{!37}\n!39 = !{!32, !35, !36}\n!40 = !{!35}\n!41 = !{!32, !36, !37}\n!42 = !{!36}\n!43 = !{!32, !35, !37}\n" } } }, { "name": "float32_32x1024", "dtype": "float32", "width": 1024, "batches": 32, "arms": { "frozen_register4": { "source_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "air_sha256": "8ff5240542a1e2d80ce3c6d6459f26c067f4ca865a8c16f43a3005ce69d0a99e", "conditional_branches": 14, "scalar_device_memory_operations": 12, "vector_device_memory_operations": 0, "textual_air": "; ModuleID = '/var/folders/x7/hs9bdmg17g167js6kt76dlxh0000gn/T/metile-tiling-air-report-dh59nkto/float32_32x1024_frozen_register4.metal'\nsource_filename = \"/var/folders/x7/hs9bdmg17g167js6kt76dlxh0000gn/T/metile-tiling-air-report-dh59nkto/float32_32x1024_frozen_register4.metal\"\ntarget datalayout = \"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-n8:16:32\"\ntarget triple = \"air64_v28-apple-macosx26.0.0\"\n\n@_ZZ22mtile_rmsnorm_registerPU9MTLdeviceKfS0_PU9MTLdevicefRU11MTLconstantKfDv3_jjjjE26_metile_register_reduction = internal unnamed_addr addrspace(3) global [8 x float] undef, align 4\n\n; Function Attrs: convergent mustprogress nounwind willreturn\ndefine void @mtile_rmsnorm_register(float addrspace(1)* nocapture noundef readonly \"air-buffer-no-alias\" %0, float addrspace(1)* nocapture noundef readonly \"air-buffer-no-alias\" %1, float addrspace(1)* nocapture noundef writeonly \"air-buffer-no-alias\" %2, float addrspace(2)* nocapture noundef readonly align 4 dereferenceable(4) \"air-buffer-no-alias\" %3, <3 x i32> noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7) local_unnamed_addr #0 {\n %9 = extractelement <3 x i32> %4, i64 0\n %10 = shl nsw i32 %9, 10\n %11 = add i32 %5, 256\n %12 = add i32 %5, 512\n %13 = add i32 %5, 768\n %14 = icmp slt i32 %5, 1024\n %15 = xor i32 %5, -1\n %16 = lshr i32 %15, 31\n %17 = zext i1 %14 to i32\n %18 = and i32 %16, %17\n %19 = icmp ne i32 %18, 0\n %20 = icmp ult i32 %11, 1024\n %21 = icmp ult i32 %12, 1024\n %22 = icmp ult i32 %13, 1024\n %23 = add nsw i32 %10, %5\n %24 = add nsw i32 %10, %11\n %25 = add nsw i32 %10, %12\n %26 = add nsw i32 %10, %13\n br i1 %19, label %27, label %31\n\n27: ; preds = %8\n %28 = sext i32 %23 to i64\n %29 = getelementptr inbounds float, float addrspace(1)* %0, i64 %28\n %30 = load float, float addrspace(1)* %29, align 4, !tbaa !27, !alias.scope !31, !noalias !34\n br label %31\n\n31: ; preds = %8, %27\n %32 = phi fast float [ %30, %27 ], [ 0.000000e+00, %8 ]\n br i1 %20, label %33, label %37\n\n33: ; preds = %31\n %34 = sext i32 %24 to i64\n %35 = getelementptr inbounds float, float addrspace(1)* %0, i64 %34\n %36 = load float, float addrspace(1)* %35, align 4, !tbaa !27, !alias.scope !31, !noalias !34\n br label %37\n\n37: ; preds = %31, %33\n %38 = phi fast float [ %36, %33 ], [ 0.000000e+00, %31 ]\n br i1 %21, label %39, label %43\n\n39: ; preds = %37\n %40 = sext i32 %25 to i64\n %41 = getelementptr inbounds float, float addrspace(1)* %0, i64 %40\n %42 = load float, float addrspace(1)* %41, align 4, !tbaa !27, !alias.scope !31, !noalias !34\n br label %43\n\n43: ; preds = %37, %39\n %44 = phi fast float [ %42, %39 ], [ 0.000000e+00, %37 ]\n br i1 %22, label %45, label %49\n\n45: ; preds = %43\n %46 = sext i32 %26 to i64\n %47 = getelementptr inbounds float, float addrspace(1)* %0, i64 %46\n %48 = load float, float addrspace(1)* %47, align 4, !tbaa !27, !alias.scope !31, !noalias !34\n br label %49\n\n49: ; preds = %43, %45\n %50 = phi fast float [ %48, %45 ], [ 0.000000e+00, %43 ]\n %51 = fmul fast float %32, %32\n %52 = fmul fast float %38, %38\n %53 = fmul fast float %44, %44\n %54 = fmul fast float %50, %50\n %55 = fadd fast float %52, %51\n %56 = fadd fast float %55, %53\n %57 = fadd fast float %56, %54\n %58 = tail call fast float @air.simd_sum.f32(float %57) #3\n %59 = icmp eq i32 %7, 0\n br i1 %59, label %60, label %63\n\n60: ; preds = %49\n %61 = zext i32 %6 to i64\n %62 = getelementptr inbounds [8 x float], [8 x float] addrspace(3)* @_ZZ22mtile_rmsnorm_registerPU9MTLdeviceKfS0_PU9MTLdevicefRU11MTLconstantKfDv3_jjjjE26_metile_register_reduction, i64 0, i64 %61\n store float %58, float addrspace(3)* %62, align 4, !tbaa !27\n br label %63\n\n63: ; preds = %60, %49\n tail call void @air.wg.barrier(i32 2, i32 1) #3\n %64 = icmp ult i32 %7, 8\n br i1 %64, label %65, label %69\n\n65: ; preds = %63\n %66 = zext i32 %7 to i64\n %67 = getelementptr inbounds [8 x float], [8 x float] addrspace(3)* @_ZZ22mtile_rmsnorm_registerPU9MTLdeviceKfS0_PU9MTLdevicefRU11MTLconstantKfDv3_jjjjE26_metile_register_reduction, i64 0, i64 %66\n %68 = load float, float addrspace(3)* %67, align 4, !tbaa !27\n br label %69\n\n69: ; preds = %63, %65\n %70 = phi fast float [ %68, %65 ], [ 0.000000e+00, %63 ]\n %71 = tail call fast float @air.simd_sum.f32(float %70) #3\n %72 = fmul fast float %71, 0x3F50000000000000\n %73 = load float, float addrspace(2)* %3, align 4, !tbaa !27, !alias.scope !38, !noalias !39\n %74 = fadd fast float %72, %73\n %75 = tail call fast float @air.fast_sqrt.f32(float %74) #4\n %76 = fdiv fast float 1.000000e+00, %75\n br i1 %19, label %77, label %81\n\n77: ; preds = %69\n %78 = sext i32 %5 to i64\n %79 = getelementptr inbounds float, float addrspace(1)* %1, i64 %78\n %80 = load float, float addrspace(1)* %79, align 4, !tbaa !27, !alias.scope !40, !noalias !41\n br label %81\n\n81: ; preds = %69, %77\n %82 = phi fast float [ %80, %77 ], [ 0.000000e+00, %69 ]\n br i1 %20, label %83, label %87\n\n83: ; preds = %81\n %84 = zext i32 %11 to i64\n %85 = getelementptr inbounds float, float addrspace(1)* %1, i64 %84\n %86 = load float, float addrspace(1)* %85, align 4, !tbaa !27, !alias.scope !40, !noalias !41\n br label %87\n\n87: ; preds = %81, %83\n %88 = phi fast float [ %86, %83 ], [ 0.000000e+00, %81 ]\n br i1 %21, label %89, label %93\n\n89: ; preds = %87\n %90 = zext i32 %12 to i64\n %91 = getelementptr inbounds float, float addrspace(1)* %1, i64 %90\n %92 = load float, float addrspace(1)* %91, align 4, !tbaa !27, !alias.scope !40, !noalias !41\n br label %93\n\n93: ; preds = %87, %89\n %94 = phi fast float [ %92, %89 ], [ 0.000000e+00, %87 ]\n br i1 %22, label %95, label %99\n\n95: ; preds = %93\n %96 = zext i32 %13 to i64\n %97 = getelementptr inbounds float, float addrspace(1)* %1, i64 %96\n %98 = load float, float addrspace(1)* %97, align 4, !tbaa !27, !alias.scope !40, !noalias !41\n br label %99\n\n99: ; preds = %93, %95\n %100 = phi fast float [ %98, %95 ], [ 0.000000e+00, %93 ]\n %101 = fmul fast float %76, %38\n %102 = fmul fast float %76, %44\n %103 = fmul fast float %76, %50\n %104 = fmul fast float %101, %88\n %105 = fmul fast float %102, %94\n %106 = fmul fast float %103, %100\n br i1 %19, label %107, label %112\n\n107: ; preds = %99\n %108 = sext i32 %23 to i64\n %109 = getelementptr inbounds float, float addrspace(1)* %2, i64 %108\n %110 = fmul fast float %76, %32\n %111 = fmul fast float %110, %82\n store float %111, float addrspace(1)* %109, align 4, !tbaa !27, !alias.scope !42, !noalias !43\n br label %112\n\n112: ; preds = %107, %99\n br i1 %20, label %113, label %116\n\n113: ; preds = %112\n %114 = sext i32 %24 to i64\n %115 = getelementptr inbounds float, float addrspace(1)* %2, i64 %114\n store float %104, float addrspace(1)* %115, align 4, !tbaa !27, !alias.scope !42, !noalias !43\n br label %116\n\n116: ; preds = %113, %112\n br i1 %21, label %117, label %120\n\n117: ; preds = %116\n %118 = sext i32 %25 to i64\n %119 = getelementptr inbounds float, float addrspace(1)* %2, i64 %118\n store float %105, float addrspace(1)* %119, align 4, !tbaa !27, !alias.scope !42, !noalias !43\n br label %120\n\n120: ; preds = %117, %116\n br i1 %22, label %121, label %124\n\n121: ; preds = %120\n %122 = sext i32 %26 to i64\n %123 = getelementptr inbounds float, float addrspace(1)* %2, i64 %122\n store float %106, float addrspace(1)* %123, align 4, !tbaa !27, !alias.scope !42, !noalias !43\n br label %124\n\n124: ; preds = %121, %120\n ret void\n}\n\n; Function Attrs: convergent mustprogress nounwind willreturn\ndeclare void @air.wg.barrier(i32, i32) local_unnamed_addr #1\n\n; Function Attrs: mustprogress nofree nosync nounwind readnone willreturn\ndeclare float @air.fast_sqrt.f32(float) local_unnamed_addr #2\n\n; Function Attrs: convergent mustprogress nounwind willreturn\ndeclare float @air.simd_sum.f32(float) local_unnamed_addr #1\n\nattributes #0 = { convergent mustprogress nounwind willreturn \"approx-func-fp-math\"=\"true\" \"frame-pointer\"=\"all\" \"min-legal-vector-width\"=\"96\" \"no-builtins\" \"no-infs-fp-math\"=\"true\" \"no-nans-fp-math\"=\"true\" \"no-signed-zeros-fp-math\"=\"true\" \"no-trapping-math\"=\"true\" \"stack-protector-buffer-size\"=\"8\" \"unsafe-fp-math\"=\"true\" }\nattributes #1 = { convergent mustprogress nounwind willreturn }\nattributes #2 = { mustprogress nofree nosync nounwind readnone willreturn }\nattributes #3 = { convergent nounwind willreturn }\nattributes #4 = { nounwind readnone willreturn }\n\n!llvm.module.flags = !{!0, !1, !2, !3, !4, !5, !6, !7, !8}\n!air.kernel = !{!9}\n!air.compile_options = !{!20, !21, !22}\n!llvm.ident = !{!23}\n!air.version = !{!24}\n!air.language_version = !{!25}\n!air.source_file_name = !{!26}\n\n!0 = !{i32 2, !\"SDK Version\", [2 x i32] [i32 26, i32 2]}\n!1 = !{i32 1, !\"wchar_size\", i32 4}\n!2 = !{i32 7, !\"frame-pointer\", i32 2}\n!3 = !{i32 7, !\"air.max_device_buffers\", i32 31}\n!4 = !{i32 7, !\"air.max_constant_buffers\", i32 31}\n!5 = !{i32 7, !\"air.max_threadgroup_buffers\", i32 31}\n!6 = !{i32 7, !\"air.max_textures\", i32 128}\n!7 = !{i32 7, !\"air.max_read_write_textures\", i32 8}\n!8 = !{i32 7, !\"air.max_samplers\", i32 16}\n!9 = !{void (float addrspace(1)*, float addrspace(1)*, float addrspace(1)*, float addrspace(2)*, <3 x i32>, i32, i32, i32)* @mtile_rmsnorm_register, !10, !11}\n!10 = !{}\n!11 = !{!12, !13, !14, !15, !16, !17, !18, !19}\n!12 = !{i32 0, !\"air.buffer\", !\"air.location_index\", i32 0, i32 1, !\"air.read\", !\"air.address_space\", i32 1, !\"air.arg_type_size\", i32 4, !\"air.arg_type_align_size\", i32 4, !\"air.arg_type_name\", !\"float\", !\"air.arg_name\", !\"X\"}\n!13 = !{i32 1, !\"air.buffer\", !\"air.location_index\", i32 1, i32 1, !\"air.read\", !\"air.address_space\", i32 1, !\"air.arg_type_size\", i32 4, !\"air.arg_type_align_size\", i32 4, !\"air.arg_type_name\", !\"float\", !\"air.arg_name\", !\"W\"}\n!14 = !{i32 2, !\"air.buffer\", !\"air.location_index\", i32 2, i32 1, !\"air.read_write\", !\"air.address_space\", i32 1, !\"air.arg_type_size\", i32 4, !\"air.arg_type_align_size\", i32 4, !\"air.arg_type_name\", !\"float\", !\"air.arg_name\", !\"Out\"}\n!15 = !{i32 3, !\"air.buffer\", !\"air.buffer_size\", i32 4, !\"air.location_index\", i32 3, i32 1, !\"air.read\", !\"air.address_space\", i32 2, !\"air.arg_type_size\", i32 4, !\"air.arg_type_align_size\", i32 4, !\"air.arg_type_name\", !\"float\", !\"air.arg_name\", !\"eps\"}\n!16 = !{i32 4, !\"air.threadgroup_position_in_grid\", !\"air.arg_type_name\", !\"uint3\", !\"air.arg_name\", !\"tgp_id\"}\n!17 = !{i32 5, !\"air.thread_index_in_threadgroup\", !\"air.arg_type_name\", !\"uint\", !\"air.arg_name\", !\"lid\"}\n!18 = !{i32 6, !\"air.simdgroup_index_in_threadgroup\", !\"air.arg_type_name\", !\"uint\", !\"air.arg_name\", !\"sgid\"}\n!19 = !{i32 7, !\"air.thread_index_in_simdgroup\", !\"air.arg_type_name\", !\"uint\", !\"air.arg_name\", !\"slid\"}\n!20 = !{!\"air.compile.denorms_disable\"}\n!21 = !{!\"air.compile.fast_math_enable\"}\n!22 = !{!\"air.compile.framebuffer_fetch_enable\"}\n!23 = !{!\"Apple metal version 32023.864 (metalfe-32023.864)\"}\n!24 = !{i32 2, i32 8, i32 0}\n!25 = !{!\"Metal\", i32 4, i32 0, i32 0}\n!26 = !{!\"/private/var/folders/x7/hs9bdmg17g167js6kt76dlxh0000gn/T/metile-tiling-air-report-dh59nkto/float32_32x1024_frozen_register4.metal\"}\n!27 = !{!28, !28, i64 0}\n!28 = !{!\"float\", !29, i64 0}\n!29 = !{!\"omnipotent char\", !30, i64 0}\n!30 = !{!\"Simple C++ TBAA\"}\n!31 = !{!32}\n!32 = distinct !{!32, !33, !\"air-alias-scope-arg(0)\"}\n!33 = distinct !{!33, !\"air-alias-scopes(mtile_rmsnorm_register)\"}\n!34 = !{!35, !36, !37}\n!35 = distinct !{!35, !33, !\"air-alias-scope-arg(1)\"}\n!36 = distinct !{!36, !33, !\"air-alias-scope-arg(2)\"}\n!37 = distinct !{!37, !33, !\"air-alias-scope-arg(3)\"}\n!38 = !{!37}\n!39 = !{!32, !35, !36}\n!40 = !{!35}\n!41 = !{!32, !36, !37}\n!42 = !{!36}\n!43 = !{!32, !35, !37}\n" }, "range_aware_register4": { "source_sha256": "26dcd97c409e667a170eb1ec796096fa645431253522d88e56e53edb0819b727", "air_sha256": "04ff9fe49f2e2742247cf927570813c7e9d22d4d1325f39fbda070c4c3c693aa", "conditional_branches": 2, "scalar_device_memory_operations": 12, "vector_device_memory_operations": 0, "textual_air": "; ModuleID = '/var/folders/x7/hs9bdmg17g167js6kt76dlxh0000gn/T/metile-tiling-air-report-dh59nkto/float32_32x1024_range_aware_register4.metal'\nsource_filename = \"/var/folders/x7/hs9bdmg17g167js6kt76dlxh0000gn/T/metile-tiling-air-report-dh59nkto/float32_32x1024_range_aware_register4.metal\"\ntarget datalayout = \"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-n8:16:32\"\ntarget triple = \"air64_v28-apple-macosx26.0.0\"\n\n@_ZZ22mtile_rmsnorm_registerPU9MTLdeviceKfS0_PU9MTLdevicefRU11MTLconstantKfDv3_jjjjE26_metile_register_reduction = internal unnamed_addr addrspace(3) global [8 x float] undef, align 4\n\n; Function Attrs: convergent mustprogress nounwind willreturn\ndefine void @mtile_rmsnorm_register(float addrspace(1)* nocapture noundef readonly \"air-buffer-no-alias\" %0, float addrspace(1)* nocapture noundef readonly \"air-buffer-no-alias\" %1, float addrspace(1)* nocapture noundef writeonly \"air-buffer-no-alias\" %2, float addrspace(2)* nocapture noundef readonly align 4 dereferenceable(4) \"air-buffer-no-alias\" %3, <3 x i32> noundef %4, i32 noundef %5, i32 noundef %6, i32 noundef %7) local_unnamed_addr #0 {\n %9 = extractelement <3 x i32> %4, i64 0\n %10 = shl nsw i32 %9, 10\n %11 = and i32 %5, 255\n %12 = or i32 %11, 256\n %13 = or i32 %11, 512\n %14 = or i32 %11, 768\n %15 = or i32 %10, %11\n %16 = or i32 %12, %10\n %17 = or i32 %13, %10\n %18 = or i32 %14, %10\n %19 = sext i32 %15 to i64\n %20 = getelementptr inbounds float, float addrspace(1)* %0, i64 %19\n %21 = load float, float addrspace(1)* %20, align 4, !tbaa !27, !alias.scope !31, !noalias !34\n %22 = sext i32 %16 to i64\n %23 = getelementptr inbounds float, float addrspace(1)* %0, i64 %22\n %24 = load float, float addrspace(1)* %23, align 4, !tbaa !27, !alias.scope !31, !noalias !34\n %25 = sext i32 %17 to i64\n %26 = getelementptr inbounds float, float addrspace(1)* %0, i64 %25\n %27 = load float, float addrspace(1)* %26, align 4, !tbaa !27, !alias.scope !31, !noalias !34\n %28 = sext i32 %18 to i64\n %29 = getelementptr inbounds float, float addrspace(1)* %0, i64 %28\n %30 = load float, float addrspace(1)* %29, align 4, !tbaa !27, !alias.scope !31, !noalias !34\n %31 = fmul fast float %21, %21\n %32 = fmul fast float %24, %24\n %33 = fmul fast float %27, %27\n %34 = fmul fast float %30, %30\n %35 = fadd fast float %32, %31\n %36 = fadd fast float %35, %33\n %37 = fadd fast float %36, %34\n %38 = tail call fast float @air.simd_sum.f32(float %37) #3\n %39 = icmp eq i32 %7, 0\n br i1 %39, label %40, label %43\n\n40: ; preds = %8\n %41 = zext i32 %6 to i64\n %42 = getelementptr inbounds [8 x float], [8 x float] addrspace(3)* @_ZZ22mtile_rmsnorm_registerPU9MTLdeviceKfS0_PU9MTLdevicefRU11MTLconstantKfDv3_jjjjE26_metile_register_reduction, i64 0, i64 %41\n store float %38, float addrspace(3)* %42, align 4, !tbaa !27\n br label %43\n\n43: ; preds = %40, %8\n tail call void @air.wg.barrier(i32 2, i32 1) #3\n %44 = icmp ult i32 %7, 8\n br i1 %44, label %45, label %49\n\n45: ; preds = %43\n %46 = zext i32 %7 to i64\n %47 = getelementptr inbounds [8 x float], [8 x float] addrspace(3)* @_ZZ22mtile_rmsnorm_registerPU9MTLdeviceKfS0_PU9MTLdevicefRU11MTLconstantKfDv3_jjjjE26_metile_register_reduction, i64 0, i64 %46\n %48 = load float, float addrspace(3)* %47, align 4, !tbaa !27\n br label %49\n\n49: ; preds = %43, %45\n %50 = phi fast float [ %48, %45 ], [ 0.000000e+00, %43 ]\n %51 = tail call fast float @air.simd_sum.f32(float %50) #3\n %52 = fmul fast float %51, 0x3F50000000000000\n %53 = load float, float addrspace(2)* %3, align 4, !tbaa !27, !alias.scope !38, !noalias !39\n %54 = fadd fast float %52, %53\n %55 = tail call fast float @air.fast_sqrt.f32(float %54) #4\n %56 = fdiv fast float 1.000000e+00, %55\n %57 = zext i32 %11 to i64\n %58 = getelementptr inbounds float, float addrspace(1)* %1, i64 %57\n %59 = load float, float addrspace(1)* %58, align 4, !tbaa !27, !alias.scope !40, !noalias !41\n %60 = zext i32 %12 to i64\n %61 = getelementptr inbounds float, float addrspace(1)* %1, i64 %60\n %62 = load float, float addrspace(1)* %61, align 4, !tbaa !27, !alias.scope !40, !noalias !41\n %63 = zext i32 %13 to i64\n %64 = getelementptr inbounds float, float addrspace(1)* %1, i64 %63\n %65 = load float, float addrspace(1)* %64, align 4, !tbaa !27, !alias.scope !40, !noalias !41\n %66 = zext i32 %14 to i64\n %67 = getelementptr inbounds float, float addrspace(1)* %1, i64 %66\n %68 = load float, float addrspace(1)* %67, align 4, !tbaa !27, !alias.scope !40, !noalias !41\n %69 = fmul fast float %56, %24\n %70 = fmul fast float %56, %27\n %71 = fmul fast float %56, %30\n %72 = fmul fast float %69, %62\n %73 = fmul fast float %70, %65\n %74 = fmul fast float %71, %68\n %75 = fmul fast float %56, %21\n %76 = fmul fast float %75, %59\n %77 = getelementptr inbounds float, float addrspace(1)* %2, i64 %19\n store float %76, float addrspace(1)* %77, align 4, !tbaa !27, !alias.scope !42, !noalias !43\n %78 = getelementptr inbounds float, float addrspace(1)* %2, i64 %22\n store float %72, float addrspace(1)* %78, align 4, !tbaa !27, !alias.scope !42, !noalias !43\n %79 = getelementptr inbounds float, float addrspace(1)* %2, i64 %25\n store float %73, float addrspace(1)* %79, align 4, !tbaa !27, !alias.scope !42, !noalias !43\n %80 = getelementptr inbounds float, float addrspace(1)* %2, i64 %28\n store float %74, float addrspace(1)* %80, align 4, !tbaa !27, !alias.scope !42, !noalias !43\n ret void\n}\n\n; Function Attrs: convergent mustprogress nounwind willreturn\ndeclare void @air.wg.barrier(i32, i32) local_unnamed_addr #1\n\n; Function Attrs: mustprogress nofree nosync nounwind readnone willreturn\ndeclare float @air.fast_sqrt.f32(float) local_unnamed_addr #2\n\n; Function Attrs: convergent mustprogress nounwind willreturn\ndeclare float @air.simd_sum.f32(float) local_unnamed_addr #1\n\nattributes #0 = { convergent mustprogress nounwind willreturn \"approx-func-fp-math\"=\"true\" \"frame-pointer\"=\"all\" \"min-legal-vector-width\"=\"96\" \"no-builtins\" \"no-infs-fp-math\"=\"true\" \"no-nans-fp-math\"=\"true\" \"no-signed-zeros-fp-math\"=\"true\" \"no-trapping-math\"=\"true\" \"stack-protector-buffer-size\"=\"8\" \"unsafe-fp-math\"=\"true\" }\nattributes #1 = { convergent mustprogress nounwind willreturn }\nattributes #2 = { mustprogress nofree nosync nounwind readnone willreturn }\nattributes #3 = { convergent nounwind willreturn }\nattributes #4 = { nounwind readnone willreturn }\n\n!llvm.module.flags = !{!0, !1, !2, !3, !4, !5, !6, !7, !8}\n!air.kernel = !{!9}\n!air.compile_options = !{!20, !21, !22}\n!llvm.ident = !{!23}\n!air.version = !{!24}\n!air.language_version = !{!25}\n!air.source_file_name = !{!26}\n\n!0 = !{i32 2, !\"SDK Version\", [2 x i32] [i32 26, i32 2]}\n!1 = !{i32 1, !\"wchar_size\", i32 4}\n!2 = !{i32 7, !\"frame-pointer\", i32 2}\n!3 = !{i32 7, !\"air.max_device_buffers\", i32 31}\n!4 = !{i32 7, !\"air.max_constant_buffers\", i32 31}\n!5 = !{i32 7, !\"air.max_threadgroup_buffers\", i32 31}\n!6 = !{i32 7, !\"air.max_textures\", i32 128}\n!7 = !{i32 7, !\"air.max_read_write_textures\", i32 8}\n!8 = !{i32 7, !\"air.max_samplers\", i32 16}\n!9 = !{void (float addrspace(1)*, float addrspace(1)*, float addrspace(1)*, float addrspace(2)*, <3 x i32>, i32, i32, i32)* @mtile_rmsnorm_register, !10, !11}\n!10 = !{}\n!11 = !{!12, !13, !14, !15, !16, !17, !18, !19}\n!12 = !{i32 0, !\"air.buffer\", !\"air.location_index\", i32 0, i32 1, !\"air.read\", !\"air.address_space\", i32 1, !\"air.arg_type_size\", i32 4, !\"air.arg_type_align_size\", i32 4, !\"air.arg_type_name\", !\"float\", !\"air.arg_name\", !\"X\"}\n!13 = !{i32 1, !\"air.buffer\", !\"air.location_index\", i32 1, i32 1, !\"air.read\", !\"air.address_space\", i32 1, !\"air.arg_type_size\", i32 4, !\"air.arg_type_align_size\", i32 4, !\"air.arg_type_name\", !\"float\", !\"air.arg_name\", !\"W\"}\n!14 = !{i32 2, !\"air.buffer\", !\"air.location_index\", i32 2, i32 1, !\"air.read_write\", !\"air.address_space\", i32 1, !\"air.arg_type_size\", i32 4, !\"air.arg_type_align_size\", i32 4, !\"air.arg_type_name\", !\"float\", !\"air.arg_name\", !\"Out\"}\n!15 = !{i32 3, !\"air.buffer\", !\"air.buffer_size\", i32 4, !\"air.location_index\", i32 3, i32 1, !\"air.read\", !\"air.address_space\", i32 2, !\"air.arg_type_size\", i32 4, !\"air.arg_type_align_size\", i32 4, !\"air.arg_type_name\", !\"float\", !\"air.arg_name\", !\"eps\"}\n!16 = !{i32 4, !\"air.threadgroup_position_in_grid\", !\"air.arg_type_name\", !\"uint3\", !\"air.arg_name\", !\"tgp_id\"}\n!17 = !{i32 5, !\"air.thread_index_in_threadgroup\", !\"air.arg_type_name\", !\"uint\", !\"air.arg_name\", !\"lid\"}\n!18 = !{i32 6, !\"air.simdgroup_index_in_threadgroup\", !\"air.arg_type_name\", !\"uint\", !\"air.arg_name\", !\"sgid\"}\n!19 = !{i32 7, !\"air.thread_index_in_simdgroup\", !\"air.arg_type_name\", !\"uint\", !\"air.arg_name\", !\"slid\"}\n!20 = !{!\"air.compile.denorms_disable\"}\n!21 = !{!\"air.compile.fast_math_enable\"}\n!22 = !{!\"air.compile.framebuffer_fetch_enable\"}\n!23 = !{!\"Apple metal version 32023.864 (metalfe-32023.864)\"}\n!24 = !{i32 2, i32 8, i32 0}\n!25 = !{!\"Metal\", i32 4, i32 0, i32 0}\n!26 = !{!\"/private/var/folders/x7/hs9bdmg17g167js6kt76dlxh0000gn/T/metile-tiling-air-report-dh59nkto/float32_32x1024_range_aware_register4.metal\"}\n!27 = !{!28, !28, i64 0}\n!28 = !{!\"float\", !29, i64 0}\n!29 = !{!\"omnipotent char\", !30, i64 0}\n!30 = !{!\"Simple C++ TBAA\"}\n!31 = !{!32}\n!32 = distinct !{!32, !33, !\"air-alias-scope-arg(0)\"}\n!33 = distinct !{!33, !\"air-alias-scopes(mtile_rmsnorm_register)\"}\n!34 = !{!35, !36, !37}\n!35 = distinct !{!35, !33, !\"air-alias-scope-arg(1)\"}\n!36 = distinct !{!36, !33, !\"air-alias-scope-arg(2)\"}\n!37 = distinct !{!37, !33, !\"air-alias-scope-arg(3)\"}\n!38 = !{!37}\n!39 = !{!32, !35, !36}\n!40 = !{!35}\n!41 = !{!32, !36, !37}\n!42 = !{!36}\n!43 = !{!32, !35, !37}\n" } } } ] }