{ "kind": "register_tiling_tune", "recorded_at": "2026-10-02T18:44:42.307458+00:00", "process_id": 81341, "platform": "macOS-26.2-arm64-arm-64bit", "device": "Apple M5", "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "mlx_version": null, "compiler_implementation_sha256": "f255b038cc297ff6ba053b68cc787f7e16d855c0b665ab82b8d5ea33c463f8be", "benchmark_source_sha256": "47a379ae8881b98ece7df1f415afed0c5f2b189f9459bf34a14198a22d112675", "benchmark_sources": { "rmsnorm_tiling.py": "01f23e4595e5a7f978945c8dde559b64415deea275c407dbb3de692b15605536", "register_rmsnorm.py": "3c6fb7144a3c48de6c74a2626eb7fd05b4c4d41918c7ac43d9dcc93165447c61" }, "baseline_export_sha256": "ddda22c512e09d77a855c6cbbd49b6f1bac26d5db71197d8c05b0e4f0ff257f9", "frozen_baseline": { "kind": "frozen_static_width_register4_baseline", "recorded_at": "2026-10-02T18:25:32.133814+00:00", "root": "/private/tmp/metile-tiling-baseline.AKA1sY", "compiler_implementation_sha256": "81570d03d2db5ba7146d00acd5feb8e3ed9e0a0139d9018a1bf4c0b83703f9cf", "device": "Apple M5", "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "seed": 1741, "epsilon": 1e-05, "gate_policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "cases": [ { "name": "float16_1x1009", "dtype": "float16", "batches": 1, "width": 1009, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "20ffd5db614652b191eacaaeaec1d5949ec0b2eac97fa1cb02c0c6d776e088b5", "correctness": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 376, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 307.896, "control": 307.021, "speedup": 0.9971581313170681 }, "gpu_us": { "candidate": 6.958318408578634, "control": 6.958318408578634, "speedup": 1.0 } } }, { "name": "float16_32x1009", "dtype": "float16", "batches": 32, "width": 1009, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "e6d696cff86bdf9ec8254c3438c13725f24b2b1f6073b44660a256dcea0488a8", "correctness": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 510, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 220.542, "control": 223.35399999999998, "speedup": 1.0127504058183927 }, "gpu_us": { "candidate": 3.1041563488543034, "control": 3.249995643272996, "speedup": 1.0469819422828104 } } }, { "name": "float16_256x1009", "dtype": "float16", "batches": 256, "width": 1009, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "3fe4b7685e23d624bcb19d6442cc8d72636943e6c185f3b0049a2ac1e0b63d81", "correctness": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 564, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 211.60399999999998, "control": 210.562, "speedup": 0.9950757074535455 }, "gpu_us": { "candidate": 5.62501372769475, "control": 5.62501372769475, "speedup": 1.0 } } }, { "name": "float16_1x1024", "dtype": "float16", "batches": 1, "width": 1024, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "3cc059cb43f2d2ee6f0120b1b81a1fb6efa6af199ab539eb734dc561564c6ebe", "correctness": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 617, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.125, "control": 199.125, "speedup": 1.0050473186119875 }, "gpu_us": { "candidate": 1.6666599549353123, "control": 1.6666599549353123, "speedup": 1.0 } } }, { "name": "float16_32x1024", "dtype": "float16", "batches": 32, "width": 1024, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "6e821d0e3f7ad3cc0206f556836dd56fc15c5cc3181cc0547765f5bce1880ac4", "correctness": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 615, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.875, "control": 198.209, "speedup": 0.9966511627906977 }, "gpu_us": { "candidate": 2.083310391753912, "control": 2.083310391753912, "speedup": 1.0 } } }, { "name": "float16_256x1024", "dtype": "float16", "batches": 256, "width": 1024, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "fcaf7de00cd83d1d1e75063d1ab252906b9f1076e1f1c8a88d773ec19ed2a30c", "correctness": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 597, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.375, "control": 204.25, "speedup": 0.999388379204893 }, "gpu_us": { "candidate": 4.958303179591894, "control": 4.958361387252808, "speedup": 1.0000117394315766 } } }, { "name": "float32_1x1009", "dtype": "float32", "batches": 1, "width": 1009, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "72c4fd9244d1e3fe8e922e59cd98ff745af158f79bcd15c587482eb6749d4442", "correctness": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 553, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.042, "control": 201.167, "speedup": 1.010676138704394 }, "gpu_us": { "candidate": 1.7500133253633976, "control": 1.7500133253633976, "speedup": 1.0 } } }, { "name": "float32_32x1009", "dtype": "float32", "batches": 32, "width": 1009, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "41fd264c427e4e182eaad0b6751f90d1477b7e8f193b298a4dc8ccbfebb45ec3", "correctness": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 614, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.20850000000002, "control": 197.2295, "speedup": 0.9950607567283946 }, "gpu_us": { "candidate": 2.41666566580534, "control": 2.41666566580534, "speedup": 1.0 } } }, { "name": "float32_256x1009", "dtype": "float32", "batches": 256, "width": 1009, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "7bf6ce415ddd84786a2d450acbead1c0e25e5540b52b07d28c1e7796b91c7626", "correctness": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 559, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 217.792, "control": 216.334, "speedup": 0.9933055392300911 }, "gpu_us": { "candidate": 8.375034667551517, "control": 8.375034667551517, "speedup": 1.0 } } }, { "name": "float32_1x1024", "dtype": "float32", "batches": 1, "width": 1024, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "ddb1751346f69e81810fa3e5e4fc2fa3d8214ffaace8e689775a59ca252f7042", "correctness": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 615, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.166, "control": 197.292, "speedup": 0.9955895562306349 }, "gpu_us": { "candidate": 1.708336640149355, "control": 1.708336640149355, "speedup": 1.0 } } }, { "name": "float32_32x1024", "dtype": "float32", "batches": 32, "width": 1024, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "0fc05dcd6172e2eebffb6471582bea984c5a888fc3b3a095d91b296908e6567b", "correctness": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 605, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.334, "control": 197.875, "speedup": 0.992680626486199 }, "gpu_us": { "candidate": 2.374988980591297, "control": 2.374988980591297, "speedup": 1.0 } } }, { "name": "float32_256x1024", "dtype": "float32", "batches": 256, "width": 1024, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "d91bbc8e56d1e705bcdef1e433ae3b5ce1d9e73a225cd6afc919bf59342546a9", "correctness": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 570, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 215.97899999999998, "control": 214.54149999999998, "speedup": 0.9933442603216054 }, "gpu_us": { "candidate": 8.04167939350009, "control": 8.083297871053219, "speedup": 1.0051753465310702 } } } ] }, "gate_policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "precision_comparison": { "class": "same_storage_precision", "same_weight_representation": true, "bitwise_exact": false, "primary_policy": "identical storage dtype, FP32 sum/normalization/weight multiply, final output cast", "primary_mlx_comparator": "mx.compile explicit full-FP32 graph then final output cast", "mlx_fast_caveat": "secondary only: FP16 normalization rounds to storage before weight multiply; checked against its own rounding reference", "mlx_fast_source": "https://github.com/ml-explore/mlx/blob/v0.32.0/mlx/backend/metal/kernels/rms_norm.metal", "relaxed_precision": false }, "configuration": { "seed": 1741, "rounds": 3, "warmup_ms": 100.0, "rep_ms": 250.0 }, "precision": { "primary": "identical storage dtype, FP32 sum/normalization/weight multiply, final output cast; not bitwise exact", "mlx_matched": "mx.compile explicit full-FP32 graph then final output cast; primary matched-policy wall comparison", "mlx_fast": "secondary only: FP16 normalization rounds to storage before weight multiply, checked against its own rounding reference", "mlx_fast_source": "https://github.com/ml-explore/mlx/blob/v0.32.0/mlx/backend/metal/kernels/rms_norm.metal", "relaxed_precision": false }, "measurement": { "gpu": "paired Metal command-buffer timestamps for candidate and exact frozen register4 shader", "wall": "paired per-invocation synchronized wall latency, compile/setup excluded; MLX includes allocation/evaluation", "compilation": "all meTile shaders rebuilt offline with identical -O2 -ffast-math compiler and default Metal language version", "specialization": "both frozen and current kernels use static N and BLOCK=1024; only compiler/ownership changes vary", "ordering": "AB/BA dispatch pairs; variant order rotates across cases; comparator order rotates across rounds" }, "cases": [ { "name": "float16_1x1009", "dtype": "float16", "batches": 1, "width": 1009, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "20ffd5db614652b191eacaaeaec1d5949ec0b2eac97fa1cb02c0c6d776e088b5", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "ca8204464d79c2fc321323a988388e3cf7608e7f4edfce8846896960ec8dd552", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 619, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 205.167, "control": 206.834, "speedup": 1.0081250883426671 }, "gpu_us": { "candidate": 1.5416881069540977, "control": 1.6249832697212696, "speedup": 1.054028543381409 } } }, { "frozen_register4": { "pairs": 615, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 203.083, "control": 203.042, "speedup": 0.9997981121019485 }, "gpu_us": { "candidate": 1.5416298992931843, "control": 1.5833647921681404, "speedup": 1.0270719275061355 } } }, { "frozen_register4": { "pairs": 615, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.25, "control": 198.5, "speedup": 0.9962358845671268 }, "gpu_us": { "candidate": 1.5416298992931843, "control": 1.5833647921681404, "speedup": 1.0270719275061355 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.001373986957936, "round_speedups": [ 1.0081250883426671, 0.9997981121019485, 0.9962358845671268 ], "candidate": 202.48513044139196, "control": 202.76334236979454 }, "gpu_us": { "speedup": 1.0359799809699914, "round_speedups": [ 1.054028543381409, 1.0270719275061355, 1.0270719275061355 ], "candidate": 1.5416493016026318, "control": 1.5971178141366953 } } } }, { "name": "float16_1x1009", "dtype": "float16", "batches": 1, "width": 1009, "status": "measured", "variant": { "name": "register4_blocked4", "elements_per_thread": 4, "layout": "blocked4" }, "input_sha256": "20ffd5db614652b191eacaaeaec1d5949ec0b2eac97fa1cb02c0c6d776e088b5", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int((((_metile_bounded_thread >> 8) & 1u) << 0) | (((_metile_bounded_thread >> 9) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 6) & 1u) << 8) | (((_metile_bounded_thread >> 7) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 8) & 1u) << 0) | (((_metile_register_packed_ >> 9) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 6) & 1u) << 8) | (((_metile_register_packed_ >> 7) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 8) & 1u) << 0) | (((_metile_register_packed__ >> 9) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 6) & 1u) << 8) | (((_metile_register_packed__ >> 7) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 8) & 1u) << 0) | (((_metile_register_packed___ >> 9) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 6) & 1u) << 8) | (((_metile_register_packed___ >> 7) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = half4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n half _metile_v20_r0 = _metile_vector_load[0];\n half _metile_v20_r1 = _metile_vector_load[1];\n half _metile_v20_r2 = _metile_vector_load[2];\n half _metile_v20_r3 = _metile_vector_load[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half4 _metile_vector_load_;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load_ = half4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load_[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load_[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load_[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load_[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n half _metile_v36_r0 = _metile_vector_load_[0];\n half _metile_v36_r1 = _metile_vector_load_[1];\n half _metile_v36_r2 = _metile_vector_load_[2];\n half _metile_v36_r3 = _metile_vector_load_[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_half4(half4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n}", "source_sha256": "32e68c0449ebffcd9bddb41f7a561299b60a076baf9a7d4067b0b3e1392256c7", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 2, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 2, "grouped_stores": 1 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 527, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 209.333, "control": 209.75, "speedup": 1.001992041388601 }, "gpu_us": { "candidate": 1.8749851733446121, "control": 1.6249832697212696, "speedup": 0.8666645970445797 } } }, { "frozen_register4": { "pairs": 611, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.375, "control": 200.167, "speedup": 1.0039724137931034 }, "gpu_us": { "candidate": 1.8333084881305695, "control": 1.6249832697212696, "speedup": 0.8863665227330455 } } }, { "frozen_register4": { "pairs": 419, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 298.083, "control": 294.875, "speedup": 0.9892378968273936 }, "gpu_us": { "candidate": 7.874972652643919, "control": 6.958318408578634, "speedup": 0.8835990568478317 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9983793716415298, "round_speedups": [ 1.001992041388601, 1.0039724137931034, 0.9892378968273936 ], "candidate": 231.71200514222085, "control": 231.33648609568965 }, "gpu_us": { "speedup": 0.878833388453487, "round_speedups": [ 0.8666645970445797, 0.8863665227330455, 0.8835990568478317 ], "candidate": 3.0025769555624064, "control": 2.6387648799492647 } } } }, { "name": "float16_1x1009", "dtype": "float16", "batches": 1, "width": 1009, "status": "measured", "variant": { "name": "register8_striped", "elements_per_thread": 8, "layout": "striped" }, "input_sha256": "20ffd5db614652b191eacaaeaec1d5949ec0b2eac97fa1cb02c0c6d776e088b5", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 127;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 128;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 256;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 384;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 512;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 640;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 768;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 896;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n half _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n half _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n half _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n half _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_____ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum______ = _metile_register_sum____ + _metile_register_sum_____;\n threadgroup float _metile_register_reduction[4];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 4u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n half _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n half _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n half _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n half _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n}", "source_sha256": "b4460a3d9f572d27169c13ec23164de0b27d29f07cf7c168c5a7763c87c06b01", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 128, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 128, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 8 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 4, "bytes": 16 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 8, "threads": 128, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 401, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 301.75, "control": 303.125, "speedup": 1.004556752278376 }, "gpu_us": { "candidate": 7.499998901039362, "control": 6.958318408578634, "speedup": 0.927775923755714 } } }, { "frozen_register4": { "pairs": 400, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 303.312, "control": 300.438, "speedup": 0.9905246083241018 }, "gpu_us": { "candidate": 7.499998901039362, "control": 6.958318408578634, "speedup": 0.927775923755714 } } }, { "frozen_register4": { "pairs": 366, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 304.60400000000004, "control": 303.875, "speedup": 0.9976067287363264 }, "gpu_us": { "candidate": 7.541675586253405, "control": 6.958318408578634, "speedup": 0.9226488635048046 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9975462464510702, "round_speedups": [ 1.004556752278376, 0.9905246083241018, 0.9976067287363264 ], "candidate": 303.21975409552675, "control": 302.4757275478095 }, "gpu_us": { "speedup": 0.9260637458515943, "round_speedups": [ 0.927775923755714, 0.927775923755714, 0.9226488635048046 ], "candidate": 7.513865476053022, "control": 6.958318408578635 } } } }, { "name": "float16_1x1009", "dtype": "float16", "batches": 1, "width": 1009, "status": "measured", "variant": { "name": "register8_blocked4", "elements_per_thread": 8, "layout": "blocked4" }, "input_sha256": "20ffd5db614652b191eacaaeaec1d5949ec0b2eac97fa1cb02c0c6d776e088b5", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 127;\n int _metile_register_index = int((((_metile_bounded_thread >> 7) & 1u) << 0) | (((_metile_bounded_thread >> 8) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 6) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 128;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 7) & 1u) << 0) | (((_metile_register_packed_ >> 8) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 6) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 256;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 7) & 1u) << 0) | (((_metile_register_packed__ >> 8) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 6) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 384;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 7) & 1u) << 0) | (((_metile_register_packed___ >> 8) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 6) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 512;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 7) & 1u) << 0) | (((_metile_register_packed____ >> 8) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 5) & 1u) << 7) | (((_metile_register_packed____ >> 6) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 640;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 7) & 1u) << 0) | (((_metile_register_packed_____ >> 8) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 5) & 1u) << 7) | (((_metile_register_packed_____ >> 6) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 768;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 7) & 1u) << 0) | (((_metile_register_packed______ >> 8) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 5) & 1u) << 7) | (((_metile_register_packed______ >> 6) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 896;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 7) & 1u) << 0) | (((_metile_register_packed_______ >> 8) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 5) & 1u) << 7) | (((_metile_register_packed_______ >> 6) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n half4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = half4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n half _metile_v20_r0 = _metile_vector_load[0];\n half _metile_v20_r1 = _metile_vector_load[1];\n half _metile_v20_r2 = _metile_vector_load[2];\n half _metile_v20_r3 = _metile_vector_load[3];\n half4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = half4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n half _metile_v20_r4 = _metile_vector_load_[0];\n half _metile_v20_r5 = _metile_vector_load_[1];\n half _metile_v20_r6 = _metile_vector_load_[2];\n half _metile_v20_r7 = _metile_vector_load_[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_____ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum______ = _metile_register_sum____ + _metile_register_sum_____;\n threadgroup float _metile_register_reduction[4];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 4u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n half4 _metile_vector_load__;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load__ = half4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load__[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load__[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load__[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load__[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n half _metile_v36_r0 = _metile_vector_load__[0];\n half _metile_v36_r1 = _metile_vector_load__[1];\n half _metile_v36_r2 = _metile_vector_load__[2];\n half _metile_v36_r3 = _metile_vector_load__[3];\n half4 _metile_vector_load___;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load___ = half4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load___[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load___[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load___[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load___[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n half _metile_v36_r4 = _metile_vector_load___[0];\n half _metile_v36_r5 = _metile_vector_load___[1];\n half _metile_v36_r6 = _metile_vector_load___[2];\n half _metile_v36_r7 = _metile_vector_load___[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_half4(half4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_half4(half4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n}", "source_sha256": "4aeb4ec992d7174b6182b507a2b9a716bd1f0d8ebc18857adde04ecf0d617fd7", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 128, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 128, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 8 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 4, "bytes": 16 } ], "double_buffered": false, "vectorized_loads": 4, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 8, "threads": 128, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 4, "grouped_stores": 2 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 345, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 306.0, "control": 304.75, "speedup": 0.9959150326797386 }, "gpu_us": { "candidate": 9.375042282044888, "control": 6.958318408578634, "speedup": 0.7422172827855111 } } }, { "frozen_register4": { "pairs": 417, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 305.291, "control": 300.833, "speedup": 0.9853975387417252 }, "gpu_us": { "candidate": 9.375042282044888, "control": 6.958318408578634, "speedup": 0.7422172827855111 } } }, { "frozen_register4": { "pairs": 422, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 305.271, "control": 304.16650000000004, "speedup": 0.9963819032924844 }, "gpu_us": { "candidate": 9.374984074383974, "control": 6.958318408578634, "speedup": 0.7422218910847442 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9925518367241872, "round_speedups": [ 0.9959150326797386, 0.9853975387417252, 0.9963819032924844 ], "candidate": 305.5204786483132, "control": 303.24491223923627 }, "gpu_us": { "speedup": 0.7422188188820764, "round_speedups": [ 0.7422172827855111, 0.7422172827855111, 0.7422218910847442 ], "candidate": 9.375022879451095, "control": 6.958318408578635 } } } }, { "name": "float16_1x1009", "dtype": "float16", "batches": 1, "width": 1009, "status": "measured", "variant": { "name": "register16_striped", "elements_per_thread": 16, "layout": "striped" }, "input_sha256": "20ffd5db614652b191eacaaeaec1d5949ec0b2eac97fa1cb02c0c6d776e088b5", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 63;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 64;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 128;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 192;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 256;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 320;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 384;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 448;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n int _metile_register_packed________ = _metile_bounded_thread + 512;\n int _metile_register_index________ = int(_metile_register_packed________);\n int _metile_register_packed_________ = _metile_bounded_thread + 576;\n int _metile_register_index_________ = int(_metile_register_packed_________);\n int _metile_register_packed__________ = _metile_bounded_thread + 640;\n int _metile_register_index__________ = int(_metile_register_packed__________);\n int _metile_register_packed___________ = _metile_bounded_thread + 704;\n int _metile_register_index___________ = int(_metile_register_packed___________);\n int _metile_register_packed____________ = _metile_bounded_thread + 768;\n int _metile_register_index____________ = int(_metile_register_packed____________);\n int _metile_register_packed_____________ = _metile_bounded_thread + 832;\n int _metile_register_index_____________ = int(_metile_register_packed_____________);\n int _metile_register_packed______________ = _metile_bounded_thread + 896;\n int _metile_register_index______________ = int(_metile_register_packed______________);\n int _metile_register_packed_______________ = _metile_bounded_thread + 960;\n int _metile_register_index_______________ = int(_metile_register_packed_______________);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v17_r8 = _metile_register_index________ < 1009;\n bool _metile_v17_r9 = _metile_register_index_________ < 1009;\n bool _metile_v17_r10 = _metile_register_index__________ < 1009;\n bool _metile_v17_r11 = _metile_register_index___________ < 1009;\n bool _metile_v17_r12 = _metile_register_index____________ < 1009;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v17_r14 = _metile_register_index______________ < 1009;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n half _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n half _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n half _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n half _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n half _metile_v20_r8 = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n half _metile_v20_r9 = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n half _metile_v20_r10 = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n half _metile_v20_r11 = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n half _metile_v20_r12 = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n half _metile_v20_r13 = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n half _metile_v20_r14 = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n half _metile_v20_r15 = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________ = _metile_register_sum____________ + _metile_register_sum_____________;\n threadgroup float _metile_register_reduction[2];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______________);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 2u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v33_r8 = _metile_register_index________ < 1009;\n bool _metile_v33_r9 = _metile_register_index_________ < 1009;\n bool _metile_v33_r10 = _metile_register_index__________ < 1009;\n bool _metile_v33_r11 = _metile_register_index___________ < 1009;\n bool _metile_v33_r12 = _metile_register_index____________ < 1009;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v33_r14 = _metile_register_index______________ < 1009;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n half _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n half _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n half _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n half _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n half _metile_v36_r8 = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n half _metile_v36_r9 = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n half _metile_v36_r10 = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n half _metile_v36_r11 = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n half _metile_v36_r12 = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n half _metile_v36_r13 = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n half _metile_v36_r14 = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n half _metile_v36_r15 = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v42_r8 = _metile_register_index________ < 1009;\n bool _metile_v42_r9 = _metile_register_index_________ < 1009;\n bool _metile_v42_r10 = _metile_register_index__________ < 1009;\n bool _metile_v42_r11 = _metile_register_index___________ < 1009;\n bool _metile_v42_r12 = _metile_register_index____________ < 1009;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v42_r14 = _metile_register_index______________ < 1009;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = _metile_v39_r8; }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = _metile_v39_r9; }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = _metile_v39_r10; }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = _metile_v39_r11; }\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = _metile_v39_r12; }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = _metile_v39_r13; }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = _metile_v39_r14; }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = _metile_v39_r15; }\n}", "source_sha256": "fabd6e8e22cb59371bb98555d949a21e2b779ed4e5b695612d2857b9566e1617", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 64, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 64, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 16 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 2, "bytes": 8 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 16, "threads": 64, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 416, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 302.60400000000004, "control": 306.2495, "speedup": 1.0120470978572655 }, "gpu_us": { "candidate": 7.583294063806534, "control": 6.916699931025505, "speedup": 0.9120970217992017 } } }, { "frozen_register4": { "pairs": 422, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 302.22900000000004, "control": 301.79200000000003, "speedup": 0.9985540765446068 }, "gpu_us": { "candidate": 7.583352271467447, "control": 6.916699931025505, "speedup": 0.9120900208011913 } } }, { "frozen_register4": { "pairs": 428, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 300.5205, "control": 298.271, "speedup": 0.9925146537424235 }, "gpu_us": { "candidate": 7.583352271467447, "control": 6.958318408578634, "speedup": 0.9175781579815936 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.001005384160744, "round_speedups": [ 1.0120470978572655, 0.9985540765446068, 0.9925146537424235 ], "candidate": 301.78313593663916, "control": 302.08654392148946 }, "gpu_us": { "speedup": 0.9139180812233229, "round_speedups": [ 0.9120970217992017, 0.9120900208011913, 0.9175781579815936 ], "candidate": 7.583332868864169, "control": 6.930545024790096 } } } }, { "name": "float16_1x1009", "dtype": "float16", "batches": 1, "width": 1009, "status": "measured", "variant": { "name": "register16_blocked4", "elements_per_thread": 16, "layout": "blocked4" }, "input_sha256": "20ffd5db614652b191eacaaeaec1d5949ec0b2eac97fa1cb02c0c6d776e088b5", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 63;\n int _metile_register_index = int((((_metile_bounded_thread >> 6) & 1u) << 0) | (((_metile_bounded_thread >> 7) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 8) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 64;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 6) & 1u) << 0) | (((_metile_register_packed_ >> 7) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 8) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 128;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 6) & 1u) << 0) | (((_metile_register_packed__ >> 7) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 8) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 192;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 6) & 1u) << 0) | (((_metile_register_packed___ >> 7) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 8) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 256;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 6) & 1u) << 0) | (((_metile_register_packed____ >> 7) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 5) & 1u) << 7) | (((_metile_register_packed____ >> 8) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 320;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 6) & 1u) << 0) | (((_metile_register_packed_____ >> 7) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 5) & 1u) << 7) | (((_metile_register_packed_____ >> 8) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 384;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 6) & 1u) << 0) | (((_metile_register_packed______ >> 7) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 5) & 1u) << 7) | (((_metile_register_packed______ >> 8) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 448;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 6) & 1u) << 0) | (((_metile_register_packed_______ >> 7) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 5) & 1u) << 7) | (((_metile_register_packed_______ >> 8) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n int _metile_register_packed________ = _metile_bounded_thread + 512;\n int _metile_register_index________ = int((((_metile_register_packed________ >> 6) & 1u) << 0) | (((_metile_register_packed________ >> 7) & 1u) << 1) | (((_metile_register_packed________ >> 0) & 1u) << 2) | (((_metile_register_packed________ >> 1) & 1u) << 3) | (((_metile_register_packed________ >> 2) & 1u) << 4) | (((_metile_register_packed________ >> 3) & 1u) << 5) | (((_metile_register_packed________ >> 4) & 1u) << 6) | (((_metile_register_packed________ >> 5) & 1u) << 7) | (((_metile_register_packed________ >> 8) & 1u) << 8) | (((_metile_register_packed________ >> 9) & 1u) << 9));\n int _metile_register_packed_________ = _metile_bounded_thread + 576;\n int _metile_register_index_________ = int((((_metile_register_packed_________ >> 6) & 1u) << 0) | (((_metile_register_packed_________ >> 7) & 1u) << 1) | (((_metile_register_packed_________ >> 0) & 1u) << 2) | (((_metile_register_packed_________ >> 1) & 1u) << 3) | (((_metile_register_packed_________ >> 2) & 1u) << 4) | (((_metile_register_packed_________ >> 3) & 1u) << 5) | (((_metile_register_packed_________ >> 4) & 1u) << 6) | (((_metile_register_packed_________ >> 5) & 1u) << 7) | (((_metile_register_packed_________ >> 8) & 1u) << 8) | (((_metile_register_packed_________ >> 9) & 1u) << 9));\n int _metile_register_packed__________ = _metile_bounded_thread + 640;\n int _metile_register_index__________ = int((((_metile_register_packed__________ >> 6) & 1u) << 0) | (((_metile_register_packed__________ >> 7) & 1u) << 1) | (((_metile_register_packed__________ >> 0) & 1u) << 2) | (((_metile_register_packed__________ >> 1) & 1u) << 3) | (((_metile_register_packed__________ >> 2) & 1u) << 4) | (((_metile_register_packed__________ >> 3) & 1u) << 5) | (((_metile_register_packed__________ >> 4) & 1u) << 6) | (((_metile_register_packed__________ >> 5) & 1u) << 7) | (((_metile_register_packed__________ >> 8) & 1u) << 8) | (((_metile_register_packed__________ >> 9) & 1u) << 9));\n int _metile_register_packed___________ = _metile_bounded_thread + 704;\n int _metile_register_index___________ = int((((_metile_register_packed___________ >> 6) & 1u) << 0) | (((_metile_register_packed___________ >> 7) & 1u) << 1) | (((_metile_register_packed___________ >> 0) & 1u) << 2) | (((_metile_register_packed___________ >> 1) & 1u) << 3) | (((_metile_register_packed___________ >> 2) & 1u) << 4) | (((_metile_register_packed___________ >> 3) & 1u) << 5) | (((_metile_register_packed___________ >> 4) & 1u) << 6) | (((_metile_register_packed___________ >> 5) & 1u) << 7) | (((_metile_register_packed___________ >> 8) & 1u) << 8) | (((_metile_register_packed___________ >> 9) & 1u) << 9));\n int _metile_register_packed____________ = _metile_bounded_thread + 768;\n int _metile_register_index____________ = int((((_metile_register_packed____________ >> 6) & 1u) << 0) | (((_metile_register_packed____________ >> 7) & 1u) << 1) | (((_metile_register_packed____________ >> 0) & 1u) << 2) | (((_metile_register_packed____________ >> 1) & 1u) << 3) | (((_metile_register_packed____________ >> 2) & 1u) << 4) | (((_metile_register_packed____________ >> 3) & 1u) << 5) | (((_metile_register_packed____________ >> 4) & 1u) << 6) | (((_metile_register_packed____________ >> 5) & 1u) << 7) | (((_metile_register_packed____________ >> 8) & 1u) << 8) | (((_metile_register_packed____________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________ = _metile_bounded_thread + 832;\n int _metile_register_index_____________ = int((((_metile_register_packed_____________ >> 6) & 1u) << 0) | (((_metile_register_packed_____________ >> 7) & 1u) << 1) | (((_metile_register_packed_____________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________ >> 5) & 1u) << 7) | (((_metile_register_packed_____________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________ >> 9) & 1u) << 9));\n int _metile_register_packed______________ = _metile_bounded_thread + 896;\n int _metile_register_index______________ = int((((_metile_register_packed______________ >> 6) & 1u) << 0) | (((_metile_register_packed______________ >> 7) & 1u) << 1) | (((_metile_register_packed______________ >> 0) & 1u) << 2) | (((_metile_register_packed______________ >> 1) & 1u) << 3) | (((_metile_register_packed______________ >> 2) & 1u) << 4) | (((_metile_register_packed______________ >> 3) & 1u) << 5) | (((_metile_register_packed______________ >> 4) & 1u) << 6) | (((_metile_register_packed______________ >> 5) & 1u) << 7) | (((_metile_register_packed______________ >> 8) & 1u) << 8) | (((_metile_register_packed______________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________ = _metile_bounded_thread + 960;\n int _metile_register_index_______________ = int((((_metile_register_packed_______________ >> 6) & 1u) << 0) | (((_metile_register_packed_______________ >> 7) & 1u) << 1) | (((_metile_register_packed_______________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________ >> 5) & 1u) << 7) | (((_metile_register_packed_______________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v17_r8 = _metile_register_index________ < 1009;\n bool _metile_v17_r9 = _metile_register_index_________ < 1009;\n bool _metile_v17_r10 = _metile_register_index__________ < 1009;\n bool _metile_v17_r11 = _metile_register_index___________ < 1009;\n bool _metile_v17_r12 = _metile_register_index____________ < 1009;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v17_r14 = _metile_register_index______________ < 1009;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n half4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = half4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n half _metile_v20_r0 = _metile_vector_load[0];\n half _metile_v20_r1 = _metile_vector_load[1];\n half _metile_v20_r2 = _metile_vector_load[2];\n half _metile_v20_r3 = _metile_vector_load[3];\n half4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = half4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n half _metile_v20_r4 = _metile_vector_load_[0];\n half _metile_v20_r5 = _metile_vector_load_[1];\n half _metile_v20_r6 = _metile_vector_load_[2];\n half _metile_v20_r7 = _metile_vector_load_[3];\n half4 _metile_vector_load__;\n if ((_metile_v18_r8) && (_metile_v18_r9) && (_metile_v18_r10) && (_metile_v18_r11) && (long(_off__metile_v19_r9) == long(_off__metile_v19_r8) + 1) && (long(_off__metile_v19_r10) == long(_off__metile_v19_r8) + 2) && (long(_off__metile_v19_r11) == long(_off__metile_v19_r8) + 3)) {\n _metile_vector_load__ = half4(*reinterpret_cast(X + _off__metile_v19_r8));\n } else {\n _metile_vector_load__[0] = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n _metile_vector_load__[1] = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n _metile_vector_load__[2] = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n _metile_vector_load__[3] = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n }\n half _metile_v20_r8 = _metile_vector_load__[0];\n half _metile_v20_r9 = _metile_vector_load__[1];\n half _metile_v20_r10 = _metile_vector_load__[2];\n half _metile_v20_r11 = _metile_vector_load__[3];\n half4 _metile_vector_load___;\n if ((_metile_v18_r12) && (_metile_v18_r13) && (_metile_v18_r14) && (_metile_v18_r15) && (long(_off__metile_v19_r13) == long(_off__metile_v19_r12) + 1) && (long(_off__metile_v19_r14) == long(_off__metile_v19_r12) + 2) && (long(_off__metile_v19_r15) == long(_off__metile_v19_r12) + 3)) {\n _metile_vector_load___ = half4(*reinterpret_cast(X + _off__metile_v19_r12));\n } else {\n _metile_vector_load___[0] = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n _metile_vector_load___[1] = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n _metile_vector_load___[2] = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n _metile_vector_load___[3] = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n }\n half _metile_v20_r12 = _metile_vector_load___[0];\n half _metile_v20_r13 = _metile_vector_load___[1];\n half _metile_v20_r14 = _metile_vector_load___[2];\n half _metile_v20_r15 = _metile_vector_load___[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________ = _metile_register_sum____________ + _metile_register_sum_____________;\n threadgroup float _metile_register_reduction[2];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______________);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 2u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v33_r8 = _metile_register_index________ < 1009;\n bool _metile_v33_r9 = _metile_register_index_________ < 1009;\n bool _metile_v33_r10 = _metile_register_index__________ < 1009;\n bool _metile_v33_r11 = _metile_register_index___________ < 1009;\n bool _metile_v33_r12 = _metile_register_index____________ < 1009;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v33_r14 = _metile_register_index______________ < 1009;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n half4 _metile_vector_load____;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load____ = half4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load____[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load____[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load____[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load____[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n half _metile_v36_r0 = _metile_vector_load____[0];\n half _metile_v36_r1 = _metile_vector_load____[1];\n half _metile_v36_r2 = _metile_vector_load____[2];\n half _metile_v36_r3 = _metile_vector_load____[3];\n half4 _metile_vector_load_____;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load_____ = half4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load_____[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load_____[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load_____[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load_____[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n half _metile_v36_r4 = _metile_vector_load_____[0];\n half _metile_v36_r5 = _metile_vector_load_____[1];\n half _metile_v36_r6 = _metile_vector_load_____[2];\n half _metile_v36_r7 = _metile_vector_load_____[3];\n half4 _metile_vector_load______;\n if ((_metile_v34_r8) && (_metile_v34_r9) && (_metile_v34_r10) && (_metile_v34_r11) && (long(_metile_register_index_________) == long(_metile_register_index________) + 1) && (long(_metile_register_index__________) == long(_metile_register_index________) + 2) && (long(_metile_register_index___________) == long(_metile_register_index________) + 3)) {\n _metile_vector_load______ = half4(*reinterpret_cast(W + _metile_register_index________));\n } else {\n _metile_vector_load______[0] = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n _metile_vector_load______[1] = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n _metile_vector_load______[2] = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n _metile_vector_load______[3] = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n }\n half _metile_v36_r8 = _metile_vector_load______[0];\n half _metile_v36_r9 = _metile_vector_load______[1];\n half _metile_v36_r10 = _metile_vector_load______[2];\n half _metile_v36_r11 = _metile_vector_load______[3];\n half4 _metile_vector_load_______;\n if ((_metile_v34_r12) && (_metile_v34_r13) && (_metile_v34_r14) && (_metile_v34_r15) && (long(_metile_register_index_____________) == long(_metile_register_index____________) + 1) && (long(_metile_register_index______________) == long(_metile_register_index____________) + 2) && (long(_metile_register_index_______________) == long(_metile_register_index____________) + 3)) {\n _metile_vector_load_______ = half4(*reinterpret_cast(W + _metile_register_index____________));\n } else {\n _metile_vector_load_______[0] = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n _metile_vector_load_______[1] = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n _metile_vector_load_______[2] = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n _metile_vector_load_______[3] = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n }\n half _metile_v36_r12 = _metile_vector_load_______[0];\n half _metile_v36_r13 = _metile_vector_load_______[1];\n half _metile_v36_r14 = _metile_vector_load_______[2];\n half _metile_v36_r15 = _metile_vector_load_______[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v42_r8 = _metile_register_index________ < 1009;\n bool _metile_v42_r9 = _metile_register_index_________ < 1009;\n bool _metile_v42_r10 = _metile_register_index__________ < 1009;\n bool _metile_v42_r11 = _metile_register_index___________ < 1009;\n bool _metile_v42_r12 = _metile_register_index____________ < 1009;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v42_r14 = _metile_register_index______________ < 1009;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_half4(half4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_half4(half4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n if ((_metile_v43_r8) && (_metile_v43_r9) && (_metile_v43_r10) && (_metile_v43_r11) && (long(_off__metile_v44_r9) == long(_off__metile_v44_r8) + 1) && (long(_off__metile_v44_r10) == long(_off__metile_v44_r8) + 2) && (long(_off__metile_v44_r11) == long(_off__metile_v44_r8) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r8) = packed_half4(half4(static_cast(_metile_v39_r8), static_cast(_metile_v39_r9), static_cast(_metile_v39_r10), static_cast(_metile_v39_r11)));\n } else {\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = static_cast(_metile_v39_r8); }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = static_cast(_metile_v39_r9); }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = static_cast(_metile_v39_r10); }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = static_cast(_metile_v39_r11); }\n }\n if ((_metile_v43_r12) && (_metile_v43_r13) && (_metile_v43_r14) && (_metile_v43_r15) && (long(_off__metile_v44_r13) == long(_off__metile_v44_r12) + 1) && (long(_off__metile_v44_r14) == long(_off__metile_v44_r12) + 2) && (long(_off__metile_v44_r15) == long(_off__metile_v44_r12) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r12) = packed_half4(half4(static_cast(_metile_v39_r12), static_cast(_metile_v39_r13), static_cast(_metile_v39_r14), static_cast(_metile_v39_r15)));\n } else {\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = static_cast(_metile_v39_r12); }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = static_cast(_metile_v39_r13); }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = static_cast(_metile_v39_r14); }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = static_cast(_metile_v39_r15); }\n }\n}", "source_sha256": "69ca6afa69b470e096587fff61d2aae73d540a3d5a9f5d7c7e10d9537062ec50", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 64, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 64, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 16 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 2, "bytes": 8 } ], "double_buffered": false, "vectorized_loads": 8, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 16, "threads": 64, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 8, "grouped_stores": 4 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 360, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 307.834, "control": 304.72900000000004, "speedup": 0.9899133948816571 }, "gpu_us": { "candidate": 12.166681699454784, "control": 6.916699931025505, "speedup": 0.5684951823253055 } } }, { "frozen_register4": { "pairs": 417, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 305.583, "control": 301.625, "speedup": 0.9870477088057908 }, "gpu_us": { "candidate": 12.166681699454784, "control": 6.916699931025505, "speedup": 0.5684951823253055 } } }, { "frozen_register4": { "pairs": 363, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 307.209, "control": 301.0, "speedup": 0.9797890035773691 }, "gpu_us": { "candidate": 12.166681699454784, "control": 6.916699931025505, "speedup": 0.5684951823253055 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.985574145591362, "round_speedups": [ 0.9899133948816571, 0.9870477088057908, 0.9797890035773691 ], "candidate": 306.8738651976534, "control": 302.446947496496 }, "gpu_us": { "speedup": 0.5684951823253055, "round_speedups": [ 0.5684951823253055, 0.5684951823253055, 0.5684951823253055 ], "candidate": 12.166681699454784, "control": 6.916699931025505 } } } }, { "name": "float16_1x1009", "dtype": "float16", "batches": 1, "width": 1009, "status": "measured", "variant": { "name": "register32_striped", "elements_per_thread": 32, "layout": "striped" }, "input_sha256": "20ffd5db614652b191eacaaeaec1d5949ec0b2eac97fa1cb02c0c6d776e088b5", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 31;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 32;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 64;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 96;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 128;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 160;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 192;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 224;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n int _metile_register_packed________ = _metile_bounded_thread + 256;\n int _metile_register_index________ = int(_metile_register_packed________);\n int _metile_register_packed_________ = _metile_bounded_thread + 288;\n int _metile_register_index_________ = int(_metile_register_packed_________);\n int _metile_register_packed__________ = _metile_bounded_thread + 320;\n int _metile_register_index__________ = int(_metile_register_packed__________);\n int _metile_register_packed___________ = _metile_bounded_thread + 352;\n int _metile_register_index___________ = int(_metile_register_packed___________);\n int _metile_register_packed____________ = _metile_bounded_thread + 384;\n int _metile_register_index____________ = int(_metile_register_packed____________);\n int _metile_register_packed_____________ = _metile_bounded_thread + 416;\n int _metile_register_index_____________ = int(_metile_register_packed_____________);\n int _metile_register_packed______________ = _metile_bounded_thread + 448;\n int _metile_register_index______________ = int(_metile_register_packed______________);\n int _metile_register_packed_______________ = _metile_bounded_thread + 480;\n int _metile_register_index_______________ = int(_metile_register_packed_______________);\n int _metile_register_packed________________ = _metile_bounded_thread + 512;\n int _metile_register_index________________ = int(_metile_register_packed________________);\n int _metile_register_packed_________________ = _metile_bounded_thread + 544;\n int _metile_register_index_________________ = int(_metile_register_packed_________________);\n int _metile_register_packed__________________ = _metile_bounded_thread + 576;\n int _metile_register_index__________________ = int(_metile_register_packed__________________);\n int _metile_register_packed___________________ = _metile_bounded_thread + 608;\n int _metile_register_index___________________ = int(_metile_register_packed___________________);\n int _metile_register_packed____________________ = _metile_bounded_thread + 640;\n int _metile_register_index____________________ = int(_metile_register_packed____________________);\n int _metile_register_packed_____________________ = _metile_bounded_thread + 672;\n int _metile_register_index_____________________ = int(_metile_register_packed_____________________);\n int _metile_register_packed______________________ = _metile_bounded_thread + 704;\n int _metile_register_index______________________ = int(_metile_register_packed______________________);\n int _metile_register_packed_______________________ = _metile_bounded_thread + 736;\n int _metile_register_index_______________________ = int(_metile_register_packed_______________________);\n int _metile_register_packed________________________ = _metile_bounded_thread + 768;\n int _metile_register_index________________________ = int(_metile_register_packed________________________);\n int _metile_register_packed_________________________ = _metile_bounded_thread + 800;\n int _metile_register_index_________________________ = int(_metile_register_packed_________________________);\n int _metile_register_packed__________________________ = _metile_bounded_thread + 832;\n int _metile_register_index__________________________ = int(_metile_register_packed__________________________);\n int _metile_register_packed___________________________ = _metile_bounded_thread + 864;\n int _metile_register_index___________________________ = int(_metile_register_packed___________________________);\n int _metile_register_packed____________________________ = _metile_bounded_thread + 896;\n int _metile_register_index____________________________ = int(_metile_register_packed____________________________);\n int _metile_register_packed_____________________________ = _metile_bounded_thread + 928;\n int _metile_register_index_____________________________ = int(_metile_register_packed_____________________________);\n int _metile_register_packed______________________________ = _metile_bounded_thread + 960;\n int _metile_register_index______________________________ = int(_metile_register_packed______________________________);\n int _metile_register_packed_______________________________ = _metile_bounded_thread + 992;\n int _metile_register_index_______________________________ = int(_metile_register_packed_______________________________);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v16_r16 = _metile_register_index________________ >= 0;\n bool _metile_v16_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v16_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v16_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v16_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v16_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v16_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v16_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v16_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v16_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v16_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v16_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v16_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v16_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v16_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v16_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v17_r8 = _metile_register_index________ < 1009;\n bool _metile_v17_r9 = _metile_register_index_________ < 1009;\n bool _metile_v17_r10 = _metile_register_index__________ < 1009;\n bool _metile_v17_r11 = _metile_register_index___________ < 1009;\n bool _metile_v17_r12 = _metile_register_index____________ < 1009;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v17_r14 = _metile_register_index______________ < 1009;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v17_r16 = _metile_register_index________________ < 1009;\n bool _metile_v17_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v17_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v17_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v17_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v17_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v17_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v17_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v17_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v17_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v17_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v17_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v17_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v17_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v17_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v17_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n bool _metile_v18_r16 = _metile_v16_r16 & _metile_v17_r16;\n bool _metile_v18_r17 = _metile_v16_r17 & _metile_v17_r17;\n bool _metile_v18_r18 = _metile_v16_r18 & _metile_v17_r18;\n bool _metile_v18_r19 = _metile_v16_r19 & _metile_v17_r19;\n bool _metile_v18_r20 = _metile_v16_r20 & _metile_v17_r20;\n bool _metile_v18_r21 = _metile_v16_r21 & _metile_v17_r21;\n bool _metile_v18_r22 = _metile_v16_r22 & _metile_v17_r22;\n bool _metile_v18_r23 = _metile_v16_r23 & _metile_v17_r23;\n bool _metile_v18_r24 = _metile_v16_r24 & _metile_v17_r24;\n bool _metile_v18_r25 = _metile_v16_r25 & _metile_v17_r25;\n bool _metile_v18_r26 = _metile_v16_r26 & _metile_v17_r26;\n bool _metile_v18_r27 = _metile_v16_r27 & _metile_v17_r27;\n bool _metile_v18_r28 = _metile_v16_r28 & _metile_v17_r28;\n bool _metile_v18_r29 = _metile_v16_r29 & _metile_v17_r29;\n bool _metile_v18_r30 = _metile_v16_r30 & _metile_v17_r30;\n bool _metile_v18_r31 = _metile_v16_r31 & _metile_v17_r31;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n int _off__metile_v19_r16 = v2 + _metile_register_index________________;\n int _off__metile_v19_r17 = v2 + _metile_register_index_________________;\n int _off__metile_v19_r18 = v2 + _metile_register_index__________________;\n int _off__metile_v19_r19 = v2 + _metile_register_index___________________;\n int _off__metile_v19_r20 = v2 + _metile_register_index____________________;\n int _off__metile_v19_r21 = v2 + _metile_register_index_____________________;\n int _off__metile_v19_r22 = v2 + _metile_register_index______________________;\n int _off__metile_v19_r23 = v2 + _metile_register_index_______________________;\n int _off__metile_v19_r24 = v2 + _metile_register_index________________________;\n int _off__metile_v19_r25 = v2 + _metile_register_index_________________________;\n int _off__metile_v19_r26 = v2 + _metile_register_index__________________________;\n int _off__metile_v19_r27 = v2 + _metile_register_index___________________________;\n int _off__metile_v19_r28 = v2 + _metile_register_index____________________________;\n int _off__metile_v19_r29 = v2 + _metile_register_index_____________________________;\n int _off__metile_v19_r30 = v2 + _metile_register_index______________________________;\n int _off__metile_v19_r31 = v2 + _metile_register_index_______________________________;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n half _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n half _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n half _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n half _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n half _metile_v20_r8 = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n half _metile_v20_r9 = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n half _metile_v20_r10 = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n half _metile_v20_r11 = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n half _metile_v20_r12 = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n half _metile_v20_r13 = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n half _metile_v20_r14 = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n half _metile_v20_r15 = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n half _metile_v20_r16 = _metile_v18_r16 ? X[_off__metile_v19_r16] : static_cast(0);\n half _metile_v20_r17 = _metile_v18_r17 ? X[_off__metile_v19_r17] : static_cast(0);\n half _metile_v20_r18 = _metile_v18_r18 ? X[_off__metile_v19_r18] : static_cast(0);\n half _metile_v20_r19 = _metile_v18_r19 ? X[_off__metile_v19_r19] : static_cast(0);\n half _metile_v20_r20 = _metile_v18_r20 ? X[_off__metile_v19_r20] : static_cast(0);\n half _metile_v20_r21 = _metile_v18_r21 ? X[_off__metile_v19_r21] : static_cast(0);\n half _metile_v20_r22 = _metile_v18_r22 ? X[_off__metile_v19_r22] : static_cast(0);\n half _metile_v20_r23 = _metile_v18_r23 ? X[_off__metile_v19_r23] : static_cast(0);\n half _metile_v20_r24 = _metile_v18_r24 ? X[_off__metile_v19_r24] : static_cast(0);\n half _metile_v20_r25 = _metile_v18_r25 ? X[_off__metile_v19_r25] : static_cast(0);\n half _metile_v20_r26 = _metile_v18_r26 ? X[_off__metile_v19_r26] : static_cast(0);\n half _metile_v20_r27 = _metile_v18_r27 ? X[_off__metile_v19_r27] : static_cast(0);\n half _metile_v20_r28 = _metile_v18_r28 ? X[_off__metile_v19_r28] : static_cast(0);\n half _metile_v20_r29 = _metile_v18_r29 ? X[_off__metile_v19_r29] : static_cast(0);\n half _metile_v20_r30 = _metile_v18_r30 ? X[_off__metile_v19_r30] : static_cast(0);\n half _metile_v20_r31 = _metile_v18_r31 ? X[_off__metile_v19_r31] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v21_r16 = static_cast(_metile_v20_r16);\n float _metile_v21_r17 = static_cast(_metile_v20_r17);\n float _metile_v21_r18 = static_cast(_metile_v20_r18);\n float _metile_v21_r19 = static_cast(_metile_v20_r19);\n float _metile_v21_r20 = static_cast(_metile_v20_r20);\n float _metile_v21_r21 = static_cast(_metile_v20_r21);\n float _metile_v21_r22 = static_cast(_metile_v20_r22);\n float _metile_v21_r23 = static_cast(_metile_v20_r23);\n float _metile_v21_r24 = static_cast(_metile_v20_r24);\n float _metile_v21_r25 = static_cast(_metile_v20_r25);\n float _metile_v21_r26 = static_cast(_metile_v20_r26);\n float _metile_v21_r27 = static_cast(_metile_v20_r27);\n float _metile_v21_r28 = static_cast(_metile_v20_r28);\n float _metile_v21_r29 = static_cast(_metile_v20_r29);\n float _metile_v21_r30 = static_cast(_metile_v20_r30);\n float _metile_v21_r31 = static_cast(_metile_v20_r31);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_v22_r16 = _metile_v21_r16 * _metile_v21_r16;\n float _metile_v22_r17 = _metile_v21_r17 * _metile_v21_r17;\n float _metile_v22_r18 = _metile_v21_r18 * _metile_v21_r18;\n float _metile_v22_r19 = _metile_v21_r19 * _metile_v21_r19;\n float _metile_v22_r20 = _metile_v21_r20 * _metile_v21_r20;\n float _metile_v22_r21 = _metile_v21_r21 * _metile_v21_r21;\n float _metile_v22_r22 = _metile_v21_r22 * _metile_v21_r22;\n float _metile_v22_r23 = _metile_v21_r23 * _metile_v21_r23;\n float _metile_v22_r24 = _metile_v21_r24 * _metile_v21_r24;\n float _metile_v22_r25 = _metile_v21_r25 * _metile_v21_r25;\n float _metile_v22_r26 = _metile_v21_r26 * _metile_v21_r26;\n float _metile_v22_r27 = _metile_v21_r27 * _metile_v21_r27;\n float _metile_v22_r28 = _metile_v21_r28 * _metile_v21_r28;\n float _metile_v22_r29 = _metile_v21_r29 * _metile_v21_r29;\n float _metile_v22_r30 = _metile_v21_r30 * _metile_v21_r30;\n float _metile_v22_r31 = _metile_v21_r31 * _metile_v21_r31;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_v22_r16 + _metile_v22_r17;\n float _metile_register_sum_________ = _metile_v22_r18 + _metile_v22_r19;\n float _metile_register_sum__________ = _metile_v22_r20 + _metile_v22_r21;\n float _metile_register_sum___________ = _metile_v22_r22 + _metile_v22_r23;\n float _metile_register_sum____________ = _metile_v22_r24 + _metile_v22_r25;\n float _metile_register_sum_____________ = _metile_v22_r26 + _metile_v22_r27;\n float _metile_register_sum______________ = _metile_v22_r28 + _metile_v22_r29;\n float _metile_register_sum_______________ = _metile_v22_r30 + _metile_v22_r31;\n float _metile_register_sum________________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________________ = _metile_register_sum____________ + _metile_register_sum_____________;\n float _metile_register_sum_______________________ = _metile_register_sum______________ + _metile_register_sum_______________;\n float _metile_register_sum________________________ = _metile_register_sum________________ + _metile_register_sum_________________;\n float _metile_register_sum_________________________ = _metile_register_sum__________________ + _metile_register_sum___________________;\n float _metile_register_sum__________________________ = _metile_register_sum____________________ + _metile_register_sum_____________________;\n float _metile_register_sum___________________________ = _metile_register_sum______________________ + _metile_register_sum_______________________;\n float _metile_register_sum____________________________ = _metile_register_sum________________________ + _metile_register_sum_________________________;\n float _metile_register_sum_____________________________ = _metile_register_sum__________________________ + _metile_register_sum___________________________;\n float _metile_register_sum______________________________ = _metile_register_sum____________________________ + _metile_register_sum_____________________________;\n float v23 = simd_sum(_metile_register_sum______________________________);\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v32_r16 = _metile_register_index________________ >= 0;\n bool _metile_v32_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v32_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v32_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v32_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v32_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v32_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v32_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v32_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v32_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v32_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v32_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v32_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v32_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v32_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v32_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v33_r8 = _metile_register_index________ < 1009;\n bool _metile_v33_r9 = _metile_register_index_________ < 1009;\n bool _metile_v33_r10 = _metile_register_index__________ < 1009;\n bool _metile_v33_r11 = _metile_register_index___________ < 1009;\n bool _metile_v33_r12 = _metile_register_index____________ < 1009;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v33_r14 = _metile_register_index______________ < 1009;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v33_r16 = _metile_register_index________________ < 1009;\n bool _metile_v33_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v33_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v33_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v33_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v33_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v33_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v33_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v33_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v33_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v33_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v33_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v33_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v33_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v33_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v33_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n bool _metile_v34_r16 = _metile_v32_r16 & _metile_v33_r16;\n bool _metile_v34_r17 = _metile_v32_r17 & _metile_v33_r17;\n bool _metile_v34_r18 = _metile_v32_r18 & _metile_v33_r18;\n bool _metile_v34_r19 = _metile_v32_r19 & _metile_v33_r19;\n bool _metile_v34_r20 = _metile_v32_r20 & _metile_v33_r20;\n bool _metile_v34_r21 = _metile_v32_r21 & _metile_v33_r21;\n bool _metile_v34_r22 = _metile_v32_r22 & _metile_v33_r22;\n bool _metile_v34_r23 = _metile_v32_r23 & _metile_v33_r23;\n bool _metile_v34_r24 = _metile_v32_r24 & _metile_v33_r24;\n bool _metile_v34_r25 = _metile_v32_r25 & _metile_v33_r25;\n bool _metile_v34_r26 = _metile_v32_r26 & _metile_v33_r26;\n bool _metile_v34_r27 = _metile_v32_r27 & _metile_v33_r27;\n bool _metile_v34_r28 = _metile_v32_r28 & _metile_v33_r28;\n bool _metile_v34_r29 = _metile_v32_r29 & _metile_v33_r29;\n bool _metile_v34_r30 = _metile_v32_r30 & _metile_v33_r30;\n bool _metile_v34_r31 = _metile_v32_r31 & _metile_v33_r31;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n half _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n half _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n half _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n half _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n half _metile_v36_r8 = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n half _metile_v36_r9 = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n half _metile_v36_r10 = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n half _metile_v36_r11 = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n half _metile_v36_r12 = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n half _metile_v36_r13 = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n half _metile_v36_r14 = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n half _metile_v36_r15 = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n half _metile_v36_r16 = _metile_v34_r16 ? W[_metile_register_index________________] : static_cast(0);\n half _metile_v36_r17 = _metile_v34_r17 ? W[_metile_register_index_________________] : static_cast(0);\n half _metile_v36_r18 = _metile_v34_r18 ? W[_metile_register_index__________________] : static_cast(0);\n half _metile_v36_r19 = _metile_v34_r19 ? W[_metile_register_index___________________] : static_cast(0);\n half _metile_v36_r20 = _metile_v34_r20 ? W[_metile_register_index____________________] : static_cast(0);\n half _metile_v36_r21 = _metile_v34_r21 ? W[_metile_register_index_____________________] : static_cast(0);\n half _metile_v36_r22 = _metile_v34_r22 ? W[_metile_register_index______________________] : static_cast(0);\n half _metile_v36_r23 = _metile_v34_r23 ? W[_metile_register_index_______________________] : static_cast(0);\n half _metile_v36_r24 = _metile_v34_r24 ? W[_metile_register_index________________________] : static_cast(0);\n half _metile_v36_r25 = _metile_v34_r25 ? W[_metile_register_index_________________________] : static_cast(0);\n half _metile_v36_r26 = _metile_v34_r26 ? W[_metile_register_index__________________________] : static_cast(0);\n half _metile_v36_r27 = _metile_v34_r27 ? W[_metile_register_index___________________________] : static_cast(0);\n half _metile_v36_r28 = _metile_v34_r28 ? W[_metile_register_index____________________________] : static_cast(0);\n half _metile_v36_r29 = _metile_v34_r29 ? W[_metile_register_index_____________________________] : static_cast(0);\n half _metile_v36_r30 = _metile_v34_r30 ? W[_metile_register_index______________________________] : static_cast(0);\n half _metile_v36_r31 = _metile_v34_r31 ? W[_metile_register_index_______________________________] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v37_r16 = static_cast(_metile_v36_r16);\n float _metile_v37_r17 = static_cast(_metile_v36_r17);\n float _metile_v37_r18 = static_cast(_metile_v36_r18);\n float _metile_v37_r19 = static_cast(_metile_v36_r19);\n float _metile_v37_r20 = static_cast(_metile_v36_r20);\n float _metile_v37_r21 = static_cast(_metile_v36_r21);\n float _metile_v37_r22 = static_cast(_metile_v36_r22);\n float _metile_v37_r23 = static_cast(_metile_v36_r23);\n float _metile_v37_r24 = static_cast(_metile_v36_r24);\n float _metile_v37_r25 = static_cast(_metile_v36_r25);\n float _metile_v37_r26 = static_cast(_metile_v36_r26);\n float _metile_v37_r27 = static_cast(_metile_v36_r27);\n float _metile_v37_r28 = static_cast(_metile_v36_r28);\n float _metile_v37_r29 = static_cast(_metile_v36_r29);\n float _metile_v37_r30 = static_cast(_metile_v36_r30);\n float _metile_v37_r31 = static_cast(_metile_v36_r31);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v38_r16 = _metile_v21_r16 * v29;\n float _metile_v38_r17 = _metile_v21_r17 * v29;\n float _metile_v38_r18 = _metile_v21_r18 * v29;\n float _metile_v38_r19 = _metile_v21_r19 * v29;\n float _metile_v38_r20 = _metile_v21_r20 * v29;\n float _metile_v38_r21 = _metile_v21_r21 * v29;\n float _metile_v38_r22 = _metile_v21_r22 * v29;\n float _metile_v38_r23 = _metile_v21_r23 * v29;\n float _metile_v38_r24 = _metile_v21_r24 * v29;\n float _metile_v38_r25 = _metile_v21_r25 * v29;\n float _metile_v38_r26 = _metile_v21_r26 * v29;\n float _metile_v38_r27 = _metile_v21_r27 * v29;\n float _metile_v38_r28 = _metile_v21_r28 * v29;\n float _metile_v38_r29 = _metile_v21_r29 * v29;\n float _metile_v38_r30 = _metile_v21_r30 * v29;\n float _metile_v38_r31 = _metile_v21_r31 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n float _metile_v39_r16 = _metile_v38_r16 * _metile_v37_r16;\n float _metile_v39_r17 = _metile_v38_r17 * _metile_v37_r17;\n float _metile_v39_r18 = _metile_v38_r18 * _metile_v37_r18;\n float _metile_v39_r19 = _metile_v38_r19 * _metile_v37_r19;\n float _metile_v39_r20 = _metile_v38_r20 * _metile_v37_r20;\n float _metile_v39_r21 = _metile_v38_r21 * _metile_v37_r21;\n float _metile_v39_r22 = _metile_v38_r22 * _metile_v37_r22;\n float _metile_v39_r23 = _metile_v38_r23 * _metile_v37_r23;\n float _metile_v39_r24 = _metile_v38_r24 * _metile_v37_r24;\n float _metile_v39_r25 = _metile_v38_r25 * _metile_v37_r25;\n float _metile_v39_r26 = _metile_v38_r26 * _metile_v37_r26;\n float _metile_v39_r27 = _metile_v38_r27 * _metile_v37_r27;\n float _metile_v39_r28 = _metile_v38_r28 * _metile_v37_r28;\n float _metile_v39_r29 = _metile_v38_r29 * _metile_v37_r29;\n float _metile_v39_r30 = _metile_v38_r30 * _metile_v37_r30;\n float _metile_v39_r31 = _metile_v38_r31 * _metile_v37_r31;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v41_r16 = _metile_register_index________________ >= 0;\n bool _metile_v41_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v41_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v41_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v41_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v41_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v41_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v41_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v41_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v41_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v41_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v41_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v41_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v41_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v41_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v41_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v42_r8 = _metile_register_index________ < 1009;\n bool _metile_v42_r9 = _metile_register_index_________ < 1009;\n bool _metile_v42_r10 = _metile_register_index__________ < 1009;\n bool _metile_v42_r11 = _metile_register_index___________ < 1009;\n bool _metile_v42_r12 = _metile_register_index____________ < 1009;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v42_r14 = _metile_register_index______________ < 1009;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v42_r16 = _metile_register_index________________ < 1009;\n bool _metile_v42_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v42_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v42_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v42_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v42_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v42_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v42_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v42_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v42_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v42_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v42_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v42_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v42_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v42_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v42_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n bool _metile_v43_r16 = _metile_v41_r16 & _metile_v42_r16;\n bool _metile_v43_r17 = _metile_v41_r17 & _metile_v42_r17;\n bool _metile_v43_r18 = _metile_v41_r18 & _metile_v42_r18;\n bool _metile_v43_r19 = _metile_v41_r19 & _metile_v42_r19;\n bool _metile_v43_r20 = _metile_v41_r20 & _metile_v42_r20;\n bool _metile_v43_r21 = _metile_v41_r21 & _metile_v42_r21;\n bool _metile_v43_r22 = _metile_v41_r22 & _metile_v42_r22;\n bool _metile_v43_r23 = _metile_v41_r23 & _metile_v42_r23;\n bool _metile_v43_r24 = _metile_v41_r24 & _metile_v42_r24;\n bool _metile_v43_r25 = _metile_v41_r25 & _metile_v42_r25;\n bool _metile_v43_r26 = _metile_v41_r26 & _metile_v42_r26;\n bool _metile_v43_r27 = _metile_v41_r27 & _metile_v42_r27;\n bool _metile_v43_r28 = _metile_v41_r28 & _metile_v42_r28;\n bool _metile_v43_r29 = _metile_v41_r29 & _metile_v42_r29;\n bool _metile_v43_r30 = _metile_v41_r30 & _metile_v42_r30;\n bool _metile_v43_r31 = _metile_v41_r31 & _metile_v42_r31;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n int _off__metile_v44_r16 = v9 + _metile_register_index________________;\n int _off__metile_v44_r17 = v9 + _metile_register_index_________________;\n int _off__metile_v44_r18 = v9 + _metile_register_index__________________;\n int _off__metile_v44_r19 = v9 + _metile_register_index___________________;\n int _off__metile_v44_r20 = v9 + _metile_register_index____________________;\n int _off__metile_v44_r21 = v9 + _metile_register_index_____________________;\n int _off__metile_v44_r22 = v9 + _metile_register_index______________________;\n int _off__metile_v44_r23 = v9 + _metile_register_index_______________________;\n int _off__metile_v44_r24 = v9 + _metile_register_index________________________;\n int _off__metile_v44_r25 = v9 + _metile_register_index_________________________;\n int _off__metile_v44_r26 = v9 + _metile_register_index__________________________;\n int _off__metile_v44_r27 = v9 + _metile_register_index___________________________;\n int _off__metile_v44_r28 = v9 + _metile_register_index____________________________;\n int _off__metile_v44_r29 = v9 + _metile_register_index_____________________________;\n int _off__metile_v44_r30 = v9 + _metile_register_index______________________________;\n int _off__metile_v44_r31 = v9 + _metile_register_index_______________________________;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = _metile_v39_r8; }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = _metile_v39_r9; }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = _metile_v39_r10; }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = _metile_v39_r11; }\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = _metile_v39_r12; }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = _metile_v39_r13; }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = _metile_v39_r14; }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = _metile_v39_r15; }\n if (_metile_v43_r16) { Out[_off__metile_v44_r16] = _metile_v39_r16; }\n if (_metile_v43_r17) { Out[_off__metile_v44_r17] = _metile_v39_r17; }\n if (_metile_v43_r18) { Out[_off__metile_v44_r18] = _metile_v39_r18; }\n if (_metile_v43_r19) { Out[_off__metile_v44_r19] = _metile_v39_r19; }\n if (_metile_v43_r20) { Out[_off__metile_v44_r20] = _metile_v39_r20; }\n if (_metile_v43_r21) { Out[_off__metile_v44_r21] = _metile_v39_r21; }\n if (_metile_v43_r22) { Out[_off__metile_v44_r22] = _metile_v39_r22; }\n if (_metile_v43_r23) { Out[_off__metile_v44_r23] = _metile_v39_r23; }\n if (_metile_v43_r24) { Out[_off__metile_v44_r24] = _metile_v39_r24; }\n if (_metile_v43_r25) { Out[_off__metile_v44_r25] = _metile_v39_r25; }\n if (_metile_v43_r26) { Out[_off__metile_v44_r26] = _metile_v39_r26; }\n if (_metile_v43_r27) { Out[_off__metile_v44_r27] = _metile_v39_r27; }\n if (_metile_v43_r28) { Out[_off__metile_v44_r28] = _metile_v39_r28; }\n if (_metile_v43_r29) { Out[_off__metile_v44_r29] = _metile_v39_r29; }\n if (_metile_v43_r30) { Out[_off__metile_v44_r30] = _metile_v39_r30; }\n if (_metile_v43_r31) { Out[_off__metile_v44_r31] = _metile_v39_r31; }\n}", "source_sha256": "d5c41916120b99fb67bf8cd3981daa7226ce2516e5cb14fd030515e31ba811e0", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 32, 1, 1 ], "is_gemm": false, "prefer_ordered": false, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 32, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 32 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 32, "threads": 32, "scratch": null, "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 416, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 303.54150000000004, "control": 302.146, "speedup": 0.995402605574526 }, "gpu_us": { "candidate": 9.333307389169931, "control": 6.916699931025505, "speedup": 0.7410770526053198 } } }, { "frozen_register4": { "pairs": 414, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 305.66700000000003, "control": 304.60400000000004, "speedup": 0.9965223592994992 }, "gpu_us": { "candidate": 9.333307389169931, "control": 6.916699931025505, "speedup": 0.7410770526053198 } } }, { "frozen_register4": { "pairs": 414, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 308.16650000000004, "control": 306.27049999999997, "speedup": 0.9938474817996114 }, "gpu_us": { "candidate": 9.333365596830845, "control": 6.958318408578634, "speedup": 0.7455315380489691 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.995256877758135, "round_speedups": [ 0.995402605574526, 0.9965223592994992, 0.9938474817996114 ], "candidate": 305.7858269213981, "control": 304.33544736448044 }, "gpu_us": { "speedup": 0.7425589159661465, "round_speedups": [ 0.7410770526053198, 0.7410770526053198, 0.7455315380489691 ], "candidate": 9.333326791683234, "control": 6.930545024790096 } } } }, { "name": "float16_1x1009", "dtype": "float16", "batches": 1, "width": 1009, "status": "measured", "variant": { "name": "register32_blocked4", "elements_per_thread": 32, "layout": "blocked4" }, "input_sha256": "20ffd5db614652b191eacaaeaec1d5949ec0b2eac97fa1cb02c0c6d776e088b5", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 31;\n int _metile_register_index = int((((_metile_bounded_thread >> 5) & 1u) << 0) | (((_metile_bounded_thread >> 6) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 7) & 1u) << 7) | (((_metile_bounded_thread >> 8) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 32;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 5) & 1u) << 0) | (((_metile_register_packed_ >> 6) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 7) & 1u) << 7) | (((_metile_register_packed_ >> 8) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 64;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 5) & 1u) << 0) | (((_metile_register_packed__ >> 6) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 7) & 1u) << 7) | (((_metile_register_packed__ >> 8) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 96;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 5) & 1u) << 0) | (((_metile_register_packed___ >> 6) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 7) & 1u) << 7) | (((_metile_register_packed___ >> 8) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 128;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 5) & 1u) << 0) | (((_metile_register_packed____ >> 6) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 7) & 1u) << 7) | (((_metile_register_packed____ >> 8) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 160;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 5) & 1u) << 0) | (((_metile_register_packed_____ >> 6) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 7) & 1u) << 7) | (((_metile_register_packed_____ >> 8) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 192;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 5) & 1u) << 0) | (((_metile_register_packed______ >> 6) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 7) & 1u) << 7) | (((_metile_register_packed______ >> 8) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 224;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 5) & 1u) << 0) | (((_metile_register_packed_______ >> 6) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 7) & 1u) << 7) | (((_metile_register_packed_______ >> 8) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n int _metile_register_packed________ = _metile_bounded_thread + 256;\n int _metile_register_index________ = int((((_metile_register_packed________ >> 5) & 1u) << 0) | (((_metile_register_packed________ >> 6) & 1u) << 1) | (((_metile_register_packed________ >> 0) & 1u) << 2) | (((_metile_register_packed________ >> 1) & 1u) << 3) | (((_metile_register_packed________ >> 2) & 1u) << 4) | (((_metile_register_packed________ >> 3) & 1u) << 5) | (((_metile_register_packed________ >> 4) & 1u) << 6) | (((_metile_register_packed________ >> 7) & 1u) << 7) | (((_metile_register_packed________ >> 8) & 1u) << 8) | (((_metile_register_packed________ >> 9) & 1u) << 9));\n int _metile_register_packed_________ = _metile_bounded_thread + 288;\n int _metile_register_index_________ = int((((_metile_register_packed_________ >> 5) & 1u) << 0) | (((_metile_register_packed_________ >> 6) & 1u) << 1) | (((_metile_register_packed_________ >> 0) & 1u) << 2) | (((_metile_register_packed_________ >> 1) & 1u) << 3) | (((_metile_register_packed_________ >> 2) & 1u) << 4) | (((_metile_register_packed_________ >> 3) & 1u) << 5) | (((_metile_register_packed_________ >> 4) & 1u) << 6) | (((_metile_register_packed_________ >> 7) & 1u) << 7) | (((_metile_register_packed_________ >> 8) & 1u) << 8) | (((_metile_register_packed_________ >> 9) & 1u) << 9));\n int _metile_register_packed__________ = _metile_bounded_thread + 320;\n int _metile_register_index__________ = int((((_metile_register_packed__________ >> 5) & 1u) << 0) | (((_metile_register_packed__________ >> 6) & 1u) << 1) | (((_metile_register_packed__________ >> 0) & 1u) << 2) | (((_metile_register_packed__________ >> 1) & 1u) << 3) | (((_metile_register_packed__________ >> 2) & 1u) << 4) | (((_metile_register_packed__________ >> 3) & 1u) << 5) | (((_metile_register_packed__________ >> 4) & 1u) << 6) | (((_metile_register_packed__________ >> 7) & 1u) << 7) | (((_metile_register_packed__________ >> 8) & 1u) << 8) | (((_metile_register_packed__________ >> 9) & 1u) << 9));\n int _metile_register_packed___________ = _metile_bounded_thread + 352;\n int _metile_register_index___________ = int((((_metile_register_packed___________ >> 5) & 1u) << 0) | (((_metile_register_packed___________ >> 6) & 1u) << 1) | (((_metile_register_packed___________ >> 0) & 1u) << 2) | (((_metile_register_packed___________ >> 1) & 1u) << 3) | (((_metile_register_packed___________ >> 2) & 1u) << 4) | (((_metile_register_packed___________ >> 3) & 1u) << 5) | (((_metile_register_packed___________ >> 4) & 1u) << 6) | (((_metile_register_packed___________ >> 7) & 1u) << 7) | (((_metile_register_packed___________ >> 8) & 1u) << 8) | (((_metile_register_packed___________ >> 9) & 1u) << 9));\n int _metile_register_packed____________ = _metile_bounded_thread + 384;\n int _metile_register_index____________ = int((((_metile_register_packed____________ >> 5) & 1u) << 0) | (((_metile_register_packed____________ >> 6) & 1u) << 1) | (((_metile_register_packed____________ >> 0) & 1u) << 2) | (((_metile_register_packed____________ >> 1) & 1u) << 3) | (((_metile_register_packed____________ >> 2) & 1u) << 4) | (((_metile_register_packed____________ >> 3) & 1u) << 5) | (((_metile_register_packed____________ >> 4) & 1u) << 6) | (((_metile_register_packed____________ >> 7) & 1u) << 7) | (((_metile_register_packed____________ >> 8) & 1u) << 8) | (((_metile_register_packed____________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________ = _metile_bounded_thread + 416;\n int _metile_register_index_____________ = int((((_metile_register_packed_____________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________ >> 9) & 1u) << 9));\n int _metile_register_packed______________ = _metile_bounded_thread + 448;\n int _metile_register_index______________ = int((((_metile_register_packed______________ >> 5) & 1u) << 0) | (((_metile_register_packed______________ >> 6) & 1u) << 1) | (((_metile_register_packed______________ >> 0) & 1u) << 2) | (((_metile_register_packed______________ >> 1) & 1u) << 3) | (((_metile_register_packed______________ >> 2) & 1u) << 4) | (((_metile_register_packed______________ >> 3) & 1u) << 5) | (((_metile_register_packed______________ >> 4) & 1u) << 6) | (((_metile_register_packed______________ >> 7) & 1u) << 7) | (((_metile_register_packed______________ >> 8) & 1u) << 8) | (((_metile_register_packed______________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________ = _metile_bounded_thread + 480;\n int _metile_register_index_______________ = int((((_metile_register_packed_______________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________ >> 9) & 1u) << 9));\n int _metile_register_packed________________ = _metile_bounded_thread + 512;\n int _metile_register_index________________ = int((((_metile_register_packed________________ >> 5) & 1u) << 0) | (((_metile_register_packed________________ >> 6) & 1u) << 1) | (((_metile_register_packed________________ >> 0) & 1u) << 2) | (((_metile_register_packed________________ >> 1) & 1u) << 3) | (((_metile_register_packed________________ >> 2) & 1u) << 4) | (((_metile_register_packed________________ >> 3) & 1u) << 5) | (((_metile_register_packed________________ >> 4) & 1u) << 6) | (((_metile_register_packed________________ >> 7) & 1u) << 7) | (((_metile_register_packed________________ >> 8) & 1u) << 8) | (((_metile_register_packed________________ >> 9) & 1u) << 9));\n int _metile_register_packed_________________ = _metile_bounded_thread + 544;\n int _metile_register_index_________________ = int((((_metile_register_packed_________________ >> 5) & 1u) << 0) | (((_metile_register_packed_________________ >> 6) & 1u) << 1) | (((_metile_register_packed_________________ >> 0) & 1u) << 2) | (((_metile_register_packed_________________ >> 1) & 1u) << 3) | (((_metile_register_packed_________________ >> 2) & 1u) << 4) | (((_metile_register_packed_________________ >> 3) & 1u) << 5) | (((_metile_register_packed_________________ >> 4) & 1u) << 6) | (((_metile_register_packed_________________ >> 7) & 1u) << 7) | (((_metile_register_packed_________________ >> 8) & 1u) << 8) | (((_metile_register_packed_________________ >> 9) & 1u) << 9));\n int _metile_register_packed__________________ = _metile_bounded_thread + 576;\n int _metile_register_index__________________ = int((((_metile_register_packed__________________ >> 5) & 1u) << 0) | (((_metile_register_packed__________________ >> 6) & 1u) << 1) | (((_metile_register_packed__________________ >> 0) & 1u) << 2) | (((_metile_register_packed__________________ >> 1) & 1u) << 3) | (((_metile_register_packed__________________ >> 2) & 1u) << 4) | (((_metile_register_packed__________________ >> 3) & 1u) << 5) | (((_metile_register_packed__________________ >> 4) & 1u) << 6) | (((_metile_register_packed__________________ >> 7) & 1u) << 7) | (((_metile_register_packed__________________ >> 8) & 1u) << 8) | (((_metile_register_packed__________________ >> 9) & 1u) << 9));\n int _metile_register_packed___________________ = _metile_bounded_thread + 608;\n int _metile_register_index___________________ = int((((_metile_register_packed___________________ >> 5) & 1u) << 0) | (((_metile_register_packed___________________ >> 6) & 1u) << 1) | (((_metile_register_packed___________________ >> 0) & 1u) << 2) | (((_metile_register_packed___________________ >> 1) & 1u) << 3) | (((_metile_register_packed___________________ >> 2) & 1u) << 4) | (((_metile_register_packed___________________ >> 3) & 1u) << 5) | (((_metile_register_packed___________________ >> 4) & 1u) << 6) | (((_metile_register_packed___________________ >> 7) & 1u) << 7) | (((_metile_register_packed___________________ >> 8) & 1u) << 8) | (((_metile_register_packed___________________ >> 9) & 1u) << 9));\n int _metile_register_packed____________________ = _metile_bounded_thread + 640;\n int _metile_register_index____________________ = int((((_metile_register_packed____________________ >> 5) & 1u) << 0) | (((_metile_register_packed____________________ >> 6) & 1u) << 1) | (((_metile_register_packed____________________ >> 0) & 1u) << 2) | (((_metile_register_packed____________________ >> 1) & 1u) << 3) | (((_metile_register_packed____________________ >> 2) & 1u) << 4) | (((_metile_register_packed____________________ >> 3) & 1u) << 5) | (((_metile_register_packed____________________ >> 4) & 1u) << 6) | (((_metile_register_packed____________________ >> 7) & 1u) << 7) | (((_metile_register_packed____________________ >> 8) & 1u) << 8) | (((_metile_register_packed____________________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________________ = _metile_bounded_thread + 672;\n int _metile_register_index_____________________ = int((((_metile_register_packed_____________________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________________ >> 9) & 1u) << 9));\n int _metile_register_packed______________________ = _metile_bounded_thread + 704;\n int _metile_register_index______________________ = int((((_metile_register_packed______________________ >> 5) & 1u) << 0) | (((_metile_register_packed______________________ >> 6) & 1u) << 1) | (((_metile_register_packed______________________ >> 0) & 1u) << 2) | (((_metile_register_packed______________________ >> 1) & 1u) << 3) | (((_metile_register_packed______________________ >> 2) & 1u) << 4) | (((_metile_register_packed______________________ >> 3) & 1u) << 5) | (((_metile_register_packed______________________ >> 4) & 1u) << 6) | (((_metile_register_packed______________________ >> 7) & 1u) << 7) | (((_metile_register_packed______________________ >> 8) & 1u) << 8) | (((_metile_register_packed______________________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________________ = _metile_bounded_thread + 736;\n int _metile_register_index_______________________ = int((((_metile_register_packed_______________________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________________ >> 9) & 1u) << 9));\n int _metile_register_packed________________________ = _metile_bounded_thread + 768;\n int _metile_register_index________________________ = int((((_metile_register_packed________________________ >> 5) & 1u) << 0) | (((_metile_register_packed________________________ >> 6) & 1u) << 1) | (((_metile_register_packed________________________ >> 0) & 1u) << 2) | (((_metile_register_packed________________________ >> 1) & 1u) << 3) | (((_metile_register_packed________________________ >> 2) & 1u) << 4) | (((_metile_register_packed________________________ >> 3) & 1u) << 5) | (((_metile_register_packed________________________ >> 4) & 1u) << 6) | (((_metile_register_packed________________________ >> 7) & 1u) << 7) | (((_metile_register_packed________________________ >> 8) & 1u) << 8) | (((_metile_register_packed________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_________________________ = _metile_bounded_thread + 800;\n int _metile_register_index_________________________ = int((((_metile_register_packed_________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_________________________ >> 9) & 1u) << 9));\n int _metile_register_packed__________________________ = _metile_bounded_thread + 832;\n int _metile_register_index__________________________ = int((((_metile_register_packed__________________________ >> 5) & 1u) << 0) | (((_metile_register_packed__________________________ >> 6) & 1u) << 1) | (((_metile_register_packed__________________________ >> 0) & 1u) << 2) | (((_metile_register_packed__________________________ >> 1) & 1u) << 3) | (((_metile_register_packed__________________________ >> 2) & 1u) << 4) | (((_metile_register_packed__________________________ >> 3) & 1u) << 5) | (((_metile_register_packed__________________________ >> 4) & 1u) << 6) | (((_metile_register_packed__________________________ >> 7) & 1u) << 7) | (((_metile_register_packed__________________________ >> 8) & 1u) << 8) | (((_metile_register_packed__________________________ >> 9) & 1u) << 9));\n int _metile_register_packed___________________________ = _metile_bounded_thread + 864;\n int _metile_register_index___________________________ = int((((_metile_register_packed___________________________ >> 5) & 1u) << 0) | (((_metile_register_packed___________________________ >> 6) & 1u) << 1) | (((_metile_register_packed___________________________ >> 0) & 1u) << 2) | (((_metile_register_packed___________________________ >> 1) & 1u) << 3) | (((_metile_register_packed___________________________ >> 2) & 1u) << 4) | (((_metile_register_packed___________________________ >> 3) & 1u) << 5) | (((_metile_register_packed___________________________ >> 4) & 1u) << 6) | (((_metile_register_packed___________________________ >> 7) & 1u) << 7) | (((_metile_register_packed___________________________ >> 8) & 1u) << 8) | (((_metile_register_packed___________________________ >> 9) & 1u) << 9));\n int _metile_register_packed____________________________ = _metile_bounded_thread + 896;\n int _metile_register_index____________________________ = int((((_metile_register_packed____________________________ >> 5) & 1u) << 0) | (((_metile_register_packed____________________________ >> 6) & 1u) << 1) | (((_metile_register_packed____________________________ >> 0) & 1u) << 2) | (((_metile_register_packed____________________________ >> 1) & 1u) << 3) | (((_metile_register_packed____________________________ >> 2) & 1u) << 4) | (((_metile_register_packed____________________________ >> 3) & 1u) << 5) | (((_metile_register_packed____________________________ >> 4) & 1u) << 6) | (((_metile_register_packed____________________________ >> 7) & 1u) << 7) | (((_metile_register_packed____________________________ >> 8) & 1u) << 8) | (((_metile_register_packed____________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________________________ = _metile_bounded_thread + 928;\n int _metile_register_index_____________________________ = int((((_metile_register_packed_____________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________________________ >> 9) & 1u) << 9));\n int _metile_register_packed______________________________ = _metile_bounded_thread + 960;\n int _metile_register_index______________________________ = int((((_metile_register_packed______________________________ >> 5) & 1u) << 0) | (((_metile_register_packed______________________________ >> 6) & 1u) << 1) | (((_metile_register_packed______________________________ >> 0) & 1u) << 2) | (((_metile_register_packed______________________________ >> 1) & 1u) << 3) | (((_metile_register_packed______________________________ >> 2) & 1u) << 4) | (((_metile_register_packed______________________________ >> 3) & 1u) << 5) | (((_metile_register_packed______________________________ >> 4) & 1u) << 6) | (((_metile_register_packed______________________________ >> 7) & 1u) << 7) | (((_metile_register_packed______________________________ >> 8) & 1u) << 8) | (((_metile_register_packed______________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________________________ = _metile_bounded_thread + 992;\n int _metile_register_index_______________________________ = int((((_metile_register_packed_______________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________________________ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v16_r16 = _metile_register_index________________ >= 0;\n bool _metile_v16_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v16_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v16_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v16_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v16_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v16_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v16_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v16_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v16_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v16_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v16_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v16_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v16_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v16_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v16_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v17_r8 = _metile_register_index________ < 1009;\n bool _metile_v17_r9 = _metile_register_index_________ < 1009;\n bool _metile_v17_r10 = _metile_register_index__________ < 1009;\n bool _metile_v17_r11 = _metile_register_index___________ < 1009;\n bool _metile_v17_r12 = _metile_register_index____________ < 1009;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v17_r14 = _metile_register_index______________ < 1009;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v17_r16 = _metile_register_index________________ < 1009;\n bool _metile_v17_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v17_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v17_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v17_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v17_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v17_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v17_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v17_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v17_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v17_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v17_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v17_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v17_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v17_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v17_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n bool _metile_v18_r16 = _metile_v16_r16 & _metile_v17_r16;\n bool _metile_v18_r17 = _metile_v16_r17 & _metile_v17_r17;\n bool _metile_v18_r18 = _metile_v16_r18 & _metile_v17_r18;\n bool _metile_v18_r19 = _metile_v16_r19 & _metile_v17_r19;\n bool _metile_v18_r20 = _metile_v16_r20 & _metile_v17_r20;\n bool _metile_v18_r21 = _metile_v16_r21 & _metile_v17_r21;\n bool _metile_v18_r22 = _metile_v16_r22 & _metile_v17_r22;\n bool _metile_v18_r23 = _metile_v16_r23 & _metile_v17_r23;\n bool _metile_v18_r24 = _metile_v16_r24 & _metile_v17_r24;\n bool _metile_v18_r25 = _metile_v16_r25 & _metile_v17_r25;\n bool _metile_v18_r26 = _metile_v16_r26 & _metile_v17_r26;\n bool _metile_v18_r27 = _metile_v16_r27 & _metile_v17_r27;\n bool _metile_v18_r28 = _metile_v16_r28 & _metile_v17_r28;\n bool _metile_v18_r29 = _metile_v16_r29 & _metile_v17_r29;\n bool _metile_v18_r30 = _metile_v16_r30 & _metile_v17_r30;\n bool _metile_v18_r31 = _metile_v16_r31 & _metile_v17_r31;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n int _off__metile_v19_r16 = v2 + _metile_register_index________________;\n int _off__metile_v19_r17 = v2 + _metile_register_index_________________;\n int _off__metile_v19_r18 = v2 + _metile_register_index__________________;\n int _off__metile_v19_r19 = v2 + _metile_register_index___________________;\n int _off__metile_v19_r20 = v2 + _metile_register_index____________________;\n int _off__metile_v19_r21 = v2 + _metile_register_index_____________________;\n int _off__metile_v19_r22 = v2 + _metile_register_index______________________;\n int _off__metile_v19_r23 = v2 + _metile_register_index_______________________;\n int _off__metile_v19_r24 = v2 + _metile_register_index________________________;\n int _off__metile_v19_r25 = v2 + _metile_register_index_________________________;\n int _off__metile_v19_r26 = v2 + _metile_register_index__________________________;\n int _off__metile_v19_r27 = v2 + _metile_register_index___________________________;\n int _off__metile_v19_r28 = v2 + _metile_register_index____________________________;\n int _off__metile_v19_r29 = v2 + _metile_register_index_____________________________;\n int _off__metile_v19_r30 = v2 + _metile_register_index______________________________;\n int _off__metile_v19_r31 = v2 + _metile_register_index_______________________________;\n half4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = half4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n half _metile_v20_r0 = _metile_vector_load[0];\n half _metile_v20_r1 = _metile_vector_load[1];\n half _metile_v20_r2 = _metile_vector_load[2];\n half _metile_v20_r3 = _metile_vector_load[3];\n half4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = half4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n half _metile_v20_r4 = _metile_vector_load_[0];\n half _metile_v20_r5 = _metile_vector_load_[1];\n half _metile_v20_r6 = _metile_vector_load_[2];\n half _metile_v20_r7 = _metile_vector_load_[3];\n half4 _metile_vector_load__;\n if ((_metile_v18_r8) && (_metile_v18_r9) && (_metile_v18_r10) && (_metile_v18_r11) && (long(_off__metile_v19_r9) == long(_off__metile_v19_r8) + 1) && (long(_off__metile_v19_r10) == long(_off__metile_v19_r8) + 2) && (long(_off__metile_v19_r11) == long(_off__metile_v19_r8) + 3)) {\n _metile_vector_load__ = half4(*reinterpret_cast(X + _off__metile_v19_r8));\n } else {\n _metile_vector_load__[0] = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n _metile_vector_load__[1] = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n _metile_vector_load__[2] = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n _metile_vector_load__[3] = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n }\n half _metile_v20_r8 = _metile_vector_load__[0];\n half _metile_v20_r9 = _metile_vector_load__[1];\n half _metile_v20_r10 = _metile_vector_load__[2];\n half _metile_v20_r11 = _metile_vector_load__[3];\n half4 _metile_vector_load___;\n if ((_metile_v18_r12) && (_metile_v18_r13) && (_metile_v18_r14) && (_metile_v18_r15) && (long(_off__metile_v19_r13) == long(_off__metile_v19_r12) + 1) && (long(_off__metile_v19_r14) == long(_off__metile_v19_r12) + 2) && (long(_off__metile_v19_r15) == long(_off__metile_v19_r12) + 3)) {\n _metile_vector_load___ = half4(*reinterpret_cast(X + _off__metile_v19_r12));\n } else {\n _metile_vector_load___[0] = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n _metile_vector_load___[1] = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n _metile_vector_load___[2] = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n _metile_vector_load___[3] = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n }\n half _metile_v20_r12 = _metile_vector_load___[0];\n half _metile_v20_r13 = _metile_vector_load___[1];\n half _metile_v20_r14 = _metile_vector_load___[2];\n half _metile_v20_r15 = _metile_vector_load___[3];\n half4 _metile_vector_load____;\n if ((_metile_v18_r16) && (_metile_v18_r17) && (_metile_v18_r18) && (_metile_v18_r19) && (long(_off__metile_v19_r17) == long(_off__metile_v19_r16) + 1) && (long(_off__metile_v19_r18) == long(_off__metile_v19_r16) + 2) && (long(_off__metile_v19_r19) == long(_off__metile_v19_r16) + 3)) {\n _metile_vector_load____ = half4(*reinterpret_cast(X + _off__metile_v19_r16));\n } else {\n _metile_vector_load____[0] = _metile_v18_r16 ? X[_off__metile_v19_r16] : static_cast(0);\n _metile_vector_load____[1] = _metile_v18_r17 ? X[_off__metile_v19_r17] : static_cast(0);\n _metile_vector_load____[2] = _metile_v18_r18 ? X[_off__metile_v19_r18] : static_cast(0);\n _metile_vector_load____[3] = _metile_v18_r19 ? X[_off__metile_v19_r19] : static_cast(0);\n }\n half _metile_v20_r16 = _metile_vector_load____[0];\n half _metile_v20_r17 = _metile_vector_load____[1];\n half _metile_v20_r18 = _metile_vector_load____[2];\n half _metile_v20_r19 = _metile_vector_load____[3];\n half4 _metile_vector_load_____;\n if ((_metile_v18_r20) && (_metile_v18_r21) && (_metile_v18_r22) && (_metile_v18_r23) && (long(_off__metile_v19_r21) == long(_off__metile_v19_r20) + 1) && (long(_off__metile_v19_r22) == long(_off__metile_v19_r20) + 2) && (long(_off__metile_v19_r23) == long(_off__metile_v19_r20) + 3)) {\n _metile_vector_load_____ = half4(*reinterpret_cast(X + _off__metile_v19_r20));\n } else {\n _metile_vector_load_____[0] = _metile_v18_r20 ? X[_off__metile_v19_r20] : static_cast(0);\n _metile_vector_load_____[1] = _metile_v18_r21 ? X[_off__metile_v19_r21] : static_cast(0);\n _metile_vector_load_____[2] = _metile_v18_r22 ? X[_off__metile_v19_r22] : static_cast(0);\n _metile_vector_load_____[3] = _metile_v18_r23 ? X[_off__metile_v19_r23] : static_cast(0);\n }\n half _metile_v20_r20 = _metile_vector_load_____[0];\n half _metile_v20_r21 = _metile_vector_load_____[1];\n half _metile_v20_r22 = _metile_vector_load_____[2];\n half _metile_v20_r23 = _metile_vector_load_____[3];\n half4 _metile_vector_load______;\n if ((_metile_v18_r24) && (_metile_v18_r25) && (_metile_v18_r26) && (_metile_v18_r27) && (long(_off__metile_v19_r25) == long(_off__metile_v19_r24) + 1) && (long(_off__metile_v19_r26) == long(_off__metile_v19_r24) + 2) && (long(_off__metile_v19_r27) == long(_off__metile_v19_r24) + 3)) {\n _metile_vector_load______ = half4(*reinterpret_cast(X + _off__metile_v19_r24));\n } else {\n _metile_vector_load______[0] = _metile_v18_r24 ? X[_off__metile_v19_r24] : static_cast(0);\n _metile_vector_load______[1] = _metile_v18_r25 ? X[_off__metile_v19_r25] : static_cast(0);\n _metile_vector_load______[2] = _metile_v18_r26 ? X[_off__metile_v19_r26] : static_cast(0);\n _metile_vector_load______[3] = _metile_v18_r27 ? X[_off__metile_v19_r27] : static_cast(0);\n }\n half _metile_v20_r24 = _metile_vector_load______[0];\n half _metile_v20_r25 = _metile_vector_load______[1];\n half _metile_v20_r26 = _metile_vector_load______[2];\n half _metile_v20_r27 = _metile_vector_load______[3];\n half4 _metile_vector_load_______;\n if ((_metile_v18_r28) && (_metile_v18_r29) && (_metile_v18_r30) && (_metile_v18_r31) && (long(_off__metile_v19_r29) == long(_off__metile_v19_r28) + 1) && (long(_off__metile_v19_r30) == long(_off__metile_v19_r28) + 2) && (long(_off__metile_v19_r31) == long(_off__metile_v19_r28) + 3)) {\n _metile_vector_load_______ = half4(*reinterpret_cast(X + _off__metile_v19_r28));\n } else {\n _metile_vector_load_______[0] = _metile_v18_r28 ? X[_off__metile_v19_r28] : static_cast(0);\n _metile_vector_load_______[1] = _metile_v18_r29 ? X[_off__metile_v19_r29] : static_cast(0);\n _metile_vector_load_______[2] = _metile_v18_r30 ? X[_off__metile_v19_r30] : static_cast(0);\n _metile_vector_load_______[3] = _metile_v18_r31 ? X[_off__metile_v19_r31] : static_cast(0);\n }\n half _metile_v20_r28 = _metile_vector_load_______[0];\n half _metile_v20_r29 = _metile_vector_load_______[1];\n half _metile_v20_r30 = _metile_vector_load_______[2];\n half _metile_v20_r31 = _metile_vector_load_______[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v21_r16 = static_cast(_metile_v20_r16);\n float _metile_v21_r17 = static_cast(_metile_v20_r17);\n float _metile_v21_r18 = static_cast(_metile_v20_r18);\n float _metile_v21_r19 = static_cast(_metile_v20_r19);\n float _metile_v21_r20 = static_cast(_metile_v20_r20);\n float _metile_v21_r21 = static_cast(_metile_v20_r21);\n float _metile_v21_r22 = static_cast(_metile_v20_r22);\n float _metile_v21_r23 = static_cast(_metile_v20_r23);\n float _metile_v21_r24 = static_cast(_metile_v20_r24);\n float _metile_v21_r25 = static_cast(_metile_v20_r25);\n float _metile_v21_r26 = static_cast(_metile_v20_r26);\n float _metile_v21_r27 = static_cast(_metile_v20_r27);\n float _metile_v21_r28 = static_cast(_metile_v20_r28);\n float _metile_v21_r29 = static_cast(_metile_v20_r29);\n float _metile_v21_r30 = static_cast(_metile_v20_r30);\n float _metile_v21_r31 = static_cast(_metile_v20_r31);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_v22_r16 = _metile_v21_r16 * _metile_v21_r16;\n float _metile_v22_r17 = _metile_v21_r17 * _metile_v21_r17;\n float _metile_v22_r18 = _metile_v21_r18 * _metile_v21_r18;\n float _metile_v22_r19 = _metile_v21_r19 * _metile_v21_r19;\n float _metile_v22_r20 = _metile_v21_r20 * _metile_v21_r20;\n float _metile_v22_r21 = _metile_v21_r21 * _metile_v21_r21;\n float _metile_v22_r22 = _metile_v21_r22 * _metile_v21_r22;\n float _metile_v22_r23 = _metile_v21_r23 * _metile_v21_r23;\n float _metile_v22_r24 = _metile_v21_r24 * _metile_v21_r24;\n float _metile_v22_r25 = _metile_v21_r25 * _metile_v21_r25;\n float _metile_v22_r26 = _metile_v21_r26 * _metile_v21_r26;\n float _metile_v22_r27 = _metile_v21_r27 * _metile_v21_r27;\n float _metile_v22_r28 = _metile_v21_r28 * _metile_v21_r28;\n float _metile_v22_r29 = _metile_v21_r29 * _metile_v21_r29;\n float _metile_v22_r30 = _metile_v21_r30 * _metile_v21_r30;\n float _metile_v22_r31 = _metile_v21_r31 * _metile_v21_r31;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_v22_r16 + _metile_v22_r17;\n float _metile_register_sum_________ = _metile_v22_r18 + _metile_v22_r19;\n float _metile_register_sum__________ = _metile_v22_r20 + _metile_v22_r21;\n float _metile_register_sum___________ = _metile_v22_r22 + _metile_v22_r23;\n float _metile_register_sum____________ = _metile_v22_r24 + _metile_v22_r25;\n float _metile_register_sum_____________ = _metile_v22_r26 + _metile_v22_r27;\n float _metile_register_sum______________ = _metile_v22_r28 + _metile_v22_r29;\n float _metile_register_sum_______________ = _metile_v22_r30 + _metile_v22_r31;\n float _metile_register_sum________________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________________ = _metile_register_sum____________ + _metile_register_sum_____________;\n float _metile_register_sum_______________________ = _metile_register_sum______________ + _metile_register_sum_______________;\n float _metile_register_sum________________________ = _metile_register_sum________________ + _metile_register_sum_________________;\n float _metile_register_sum_________________________ = _metile_register_sum__________________ + _metile_register_sum___________________;\n float _metile_register_sum__________________________ = _metile_register_sum____________________ + _metile_register_sum_____________________;\n float _metile_register_sum___________________________ = _metile_register_sum______________________ + _metile_register_sum_______________________;\n float _metile_register_sum____________________________ = _metile_register_sum________________________ + _metile_register_sum_________________________;\n float _metile_register_sum_____________________________ = _metile_register_sum__________________________ + _metile_register_sum___________________________;\n float _metile_register_sum______________________________ = _metile_register_sum____________________________ + _metile_register_sum_____________________________;\n float v23 = simd_sum(_metile_register_sum______________________________);\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v32_r16 = _metile_register_index________________ >= 0;\n bool _metile_v32_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v32_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v32_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v32_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v32_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v32_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v32_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v32_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v32_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v32_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v32_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v32_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v32_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v32_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v32_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v33_r8 = _metile_register_index________ < 1009;\n bool _metile_v33_r9 = _metile_register_index_________ < 1009;\n bool _metile_v33_r10 = _metile_register_index__________ < 1009;\n bool _metile_v33_r11 = _metile_register_index___________ < 1009;\n bool _metile_v33_r12 = _metile_register_index____________ < 1009;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v33_r14 = _metile_register_index______________ < 1009;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v33_r16 = _metile_register_index________________ < 1009;\n bool _metile_v33_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v33_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v33_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v33_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v33_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v33_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v33_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v33_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v33_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v33_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v33_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v33_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v33_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v33_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v33_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n bool _metile_v34_r16 = _metile_v32_r16 & _metile_v33_r16;\n bool _metile_v34_r17 = _metile_v32_r17 & _metile_v33_r17;\n bool _metile_v34_r18 = _metile_v32_r18 & _metile_v33_r18;\n bool _metile_v34_r19 = _metile_v32_r19 & _metile_v33_r19;\n bool _metile_v34_r20 = _metile_v32_r20 & _metile_v33_r20;\n bool _metile_v34_r21 = _metile_v32_r21 & _metile_v33_r21;\n bool _metile_v34_r22 = _metile_v32_r22 & _metile_v33_r22;\n bool _metile_v34_r23 = _metile_v32_r23 & _metile_v33_r23;\n bool _metile_v34_r24 = _metile_v32_r24 & _metile_v33_r24;\n bool _metile_v34_r25 = _metile_v32_r25 & _metile_v33_r25;\n bool _metile_v34_r26 = _metile_v32_r26 & _metile_v33_r26;\n bool _metile_v34_r27 = _metile_v32_r27 & _metile_v33_r27;\n bool _metile_v34_r28 = _metile_v32_r28 & _metile_v33_r28;\n bool _metile_v34_r29 = _metile_v32_r29 & _metile_v33_r29;\n bool _metile_v34_r30 = _metile_v32_r30 & _metile_v33_r30;\n bool _metile_v34_r31 = _metile_v32_r31 & _metile_v33_r31;\n half4 _metile_vector_load________;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load________ = half4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load________[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load________[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load________[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load________[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n half _metile_v36_r0 = _metile_vector_load________[0];\n half _metile_v36_r1 = _metile_vector_load________[1];\n half _metile_v36_r2 = _metile_vector_load________[2];\n half _metile_v36_r3 = _metile_vector_load________[3];\n half4 _metile_vector_load_________;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load_________ = half4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load_________[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load_________[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load_________[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load_________[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n half _metile_v36_r4 = _metile_vector_load_________[0];\n half _metile_v36_r5 = _metile_vector_load_________[1];\n half _metile_v36_r6 = _metile_vector_load_________[2];\n half _metile_v36_r7 = _metile_vector_load_________[3];\n half4 _metile_vector_load__________;\n if ((_metile_v34_r8) && (_metile_v34_r9) && (_metile_v34_r10) && (_metile_v34_r11) && (long(_metile_register_index_________) == long(_metile_register_index________) + 1) && (long(_metile_register_index__________) == long(_metile_register_index________) + 2) && (long(_metile_register_index___________) == long(_metile_register_index________) + 3)) {\n _metile_vector_load__________ = half4(*reinterpret_cast(W + _metile_register_index________));\n } else {\n _metile_vector_load__________[0] = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n _metile_vector_load__________[1] = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n _metile_vector_load__________[2] = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n _metile_vector_load__________[3] = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n }\n half _metile_v36_r8 = _metile_vector_load__________[0];\n half _metile_v36_r9 = _metile_vector_load__________[1];\n half _metile_v36_r10 = _metile_vector_load__________[2];\n half _metile_v36_r11 = _metile_vector_load__________[3];\n half4 _metile_vector_load___________;\n if ((_metile_v34_r12) && (_metile_v34_r13) && (_metile_v34_r14) && (_metile_v34_r15) && (long(_metile_register_index_____________) == long(_metile_register_index____________) + 1) && (long(_metile_register_index______________) == long(_metile_register_index____________) + 2) && (long(_metile_register_index_______________) == long(_metile_register_index____________) + 3)) {\n _metile_vector_load___________ = half4(*reinterpret_cast(W + _metile_register_index____________));\n } else {\n _metile_vector_load___________[0] = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n _metile_vector_load___________[1] = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n _metile_vector_load___________[2] = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n _metile_vector_load___________[3] = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n }\n half _metile_v36_r12 = _metile_vector_load___________[0];\n half _metile_v36_r13 = _metile_vector_load___________[1];\n half _metile_v36_r14 = _metile_vector_load___________[2];\n half _metile_v36_r15 = _metile_vector_load___________[3];\n half4 _metile_vector_load____________;\n if ((_metile_v34_r16) && (_metile_v34_r17) && (_metile_v34_r18) && (_metile_v34_r19) && (long(_metile_register_index_________________) == long(_metile_register_index________________) + 1) && (long(_metile_register_index__________________) == long(_metile_register_index________________) + 2) && (long(_metile_register_index___________________) == long(_metile_register_index________________) + 3)) {\n _metile_vector_load____________ = half4(*reinterpret_cast(W + _metile_register_index________________));\n } else {\n _metile_vector_load____________[0] = _metile_v34_r16 ? W[_metile_register_index________________] : static_cast(0);\n _metile_vector_load____________[1] = _metile_v34_r17 ? W[_metile_register_index_________________] : static_cast(0);\n _metile_vector_load____________[2] = _metile_v34_r18 ? W[_metile_register_index__________________] : static_cast(0);\n _metile_vector_load____________[3] = _metile_v34_r19 ? W[_metile_register_index___________________] : static_cast(0);\n }\n half _metile_v36_r16 = _metile_vector_load____________[0];\n half _metile_v36_r17 = _metile_vector_load____________[1];\n half _metile_v36_r18 = _metile_vector_load____________[2];\n half _metile_v36_r19 = _metile_vector_load____________[3];\n half4 _metile_vector_load_____________;\n if ((_metile_v34_r20) && (_metile_v34_r21) && (_metile_v34_r22) && (_metile_v34_r23) && (long(_metile_register_index_____________________) == long(_metile_register_index____________________) + 1) && (long(_metile_register_index______________________) == long(_metile_register_index____________________) + 2) && (long(_metile_register_index_______________________) == long(_metile_register_index____________________) + 3)) {\n _metile_vector_load_____________ = half4(*reinterpret_cast(W + _metile_register_index____________________));\n } else {\n _metile_vector_load_____________[0] = _metile_v34_r20 ? W[_metile_register_index____________________] : static_cast(0);\n _metile_vector_load_____________[1] = _metile_v34_r21 ? W[_metile_register_index_____________________] : static_cast(0);\n _metile_vector_load_____________[2] = _metile_v34_r22 ? W[_metile_register_index______________________] : static_cast(0);\n _metile_vector_load_____________[3] = _metile_v34_r23 ? W[_metile_register_index_______________________] : static_cast(0);\n }\n half _metile_v36_r20 = _metile_vector_load_____________[0];\n half _metile_v36_r21 = _metile_vector_load_____________[1];\n half _metile_v36_r22 = _metile_vector_load_____________[2];\n half _metile_v36_r23 = _metile_vector_load_____________[3];\n half4 _metile_vector_load______________;\n if ((_metile_v34_r24) && (_metile_v34_r25) && (_metile_v34_r26) && (_metile_v34_r27) && (long(_metile_register_index_________________________) == long(_metile_register_index________________________) + 1) && (long(_metile_register_index__________________________) == long(_metile_register_index________________________) + 2) && (long(_metile_register_index___________________________) == long(_metile_register_index________________________) + 3)) {\n _metile_vector_load______________ = half4(*reinterpret_cast(W + _metile_register_index________________________));\n } else {\n _metile_vector_load______________[0] = _metile_v34_r24 ? W[_metile_register_index________________________] : static_cast(0);\n _metile_vector_load______________[1] = _metile_v34_r25 ? W[_metile_register_index_________________________] : static_cast(0);\n _metile_vector_load______________[2] = _metile_v34_r26 ? W[_metile_register_index__________________________] : static_cast(0);\n _metile_vector_load______________[3] = _metile_v34_r27 ? W[_metile_register_index___________________________] : static_cast(0);\n }\n half _metile_v36_r24 = _metile_vector_load______________[0];\n half _metile_v36_r25 = _metile_vector_load______________[1];\n half _metile_v36_r26 = _metile_vector_load______________[2];\n half _metile_v36_r27 = _metile_vector_load______________[3];\n half4 _metile_vector_load_______________;\n if ((_metile_v34_r28) && (_metile_v34_r29) && (_metile_v34_r30) && (_metile_v34_r31) && (long(_metile_register_index_____________________________) == long(_metile_register_index____________________________) + 1) && (long(_metile_register_index______________________________) == long(_metile_register_index____________________________) + 2) && (long(_metile_register_index_______________________________) == long(_metile_register_index____________________________) + 3)) {\n _metile_vector_load_______________ = half4(*reinterpret_cast(W + _metile_register_index____________________________));\n } else {\n _metile_vector_load_______________[0] = _metile_v34_r28 ? W[_metile_register_index____________________________] : static_cast(0);\n _metile_vector_load_______________[1] = _metile_v34_r29 ? W[_metile_register_index_____________________________] : static_cast(0);\n _metile_vector_load_______________[2] = _metile_v34_r30 ? W[_metile_register_index______________________________] : static_cast(0);\n _metile_vector_load_______________[3] = _metile_v34_r31 ? W[_metile_register_index_______________________________] : static_cast(0);\n }\n half _metile_v36_r28 = _metile_vector_load_______________[0];\n half _metile_v36_r29 = _metile_vector_load_______________[1];\n half _metile_v36_r30 = _metile_vector_load_______________[2];\n half _metile_v36_r31 = _metile_vector_load_______________[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v37_r16 = static_cast(_metile_v36_r16);\n float _metile_v37_r17 = static_cast(_metile_v36_r17);\n float _metile_v37_r18 = static_cast(_metile_v36_r18);\n float _metile_v37_r19 = static_cast(_metile_v36_r19);\n float _metile_v37_r20 = static_cast(_metile_v36_r20);\n float _metile_v37_r21 = static_cast(_metile_v36_r21);\n float _metile_v37_r22 = static_cast(_metile_v36_r22);\n float _metile_v37_r23 = static_cast(_metile_v36_r23);\n float _metile_v37_r24 = static_cast(_metile_v36_r24);\n float _metile_v37_r25 = static_cast(_metile_v36_r25);\n float _metile_v37_r26 = static_cast(_metile_v36_r26);\n float _metile_v37_r27 = static_cast(_metile_v36_r27);\n float _metile_v37_r28 = static_cast(_metile_v36_r28);\n float _metile_v37_r29 = static_cast(_metile_v36_r29);\n float _metile_v37_r30 = static_cast(_metile_v36_r30);\n float _metile_v37_r31 = static_cast(_metile_v36_r31);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v38_r16 = _metile_v21_r16 * v29;\n float _metile_v38_r17 = _metile_v21_r17 * v29;\n float _metile_v38_r18 = _metile_v21_r18 * v29;\n float _metile_v38_r19 = _metile_v21_r19 * v29;\n float _metile_v38_r20 = _metile_v21_r20 * v29;\n float _metile_v38_r21 = _metile_v21_r21 * v29;\n float _metile_v38_r22 = _metile_v21_r22 * v29;\n float _metile_v38_r23 = _metile_v21_r23 * v29;\n float _metile_v38_r24 = _metile_v21_r24 * v29;\n float _metile_v38_r25 = _metile_v21_r25 * v29;\n float _metile_v38_r26 = _metile_v21_r26 * v29;\n float _metile_v38_r27 = _metile_v21_r27 * v29;\n float _metile_v38_r28 = _metile_v21_r28 * v29;\n float _metile_v38_r29 = _metile_v21_r29 * v29;\n float _metile_v38_r30 = _metile_v21_r30 * v29;\n float _metile_v38_r31 = _metile_v21_r31 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n float _metile_v39_r16 = _metile_v38_r16 * _metile_v37_r16;\n float _metile_v39_r17 = _metile_v38_r17 * _metile_v37_r17;\n float _metile_v39_r18 = _metile_v38_r18 * _metile_v37_r18;\n float _metile_v39_r19 = _metile_v38_r19 * _metile_v37_r19;\n float _metile_v39_r20 = _metile_v38_r20 * _metile_v37_r20;\n float _metile_v39_r21 = _metile_v38_r21 * _metile_v37_r21;\n float _metile_v39_r22 = _metile_v38_r22 * _metile_v37_r22;\n float _metile_v39_r23 = _metile_v38_r23 * _metile_v37_r23;\n float _metile_v39_r24 = _metile_v38_r24 * _metile_v37_r24;\n float _metile_v39_r25 = _metile_v38_r25 * _metile_v37_r25;\n float _metile_v39_r26 = _metile_v38_r26 * _metile_v37_r26;\n float _metile_v39_r27 = _metile_v38_r27 * _metile_v37_r27;\n float _metile_v39_r28 = _metile_v38_r28 * _metile_v37_r28;\n float _metile_v39_r29 = _metile_v38_r29 * _metile_v37_r29;\n float _metile_v39_r30 = _metile_v38_r30 * _metile_v37_r30;\n float _metile_v39_r31 = _metile_v38_r31 * _metile_v37_r31;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v41_r16 = _metile_register_index________________ >= 0;\n bool _metile_v41_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v41_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v41_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v41_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v41_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v41_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v41_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v41_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v41_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v41_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v41_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v41_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v41_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v41_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v41_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v42_r8 = _metile_register_index________ < 1009;\n bool _metile_v42_r9 = _metile_register_index_________ < 1009;\n bool _metile_v42_r10 = _metile_register_index__________ < 1009;\n bool _metile_v42_r11 = _metile_register_index___________ < 1009;\n bool _metile_v42_r12 = _metile_register_index____________ < 1009;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v42_r14 = _metile_register_index______________ < 1009;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v42_r16 = _metile_register_index________________ < 1009;\n bool _metile_v42_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v42_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v42_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v42_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v42_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v42_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v42_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v42_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v42_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v42_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v42_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v42_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v42_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v42_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v42_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n bool _metile_v43_r16 = _metile_v41_r16 & _metile_v42_r16;\n bool _metile_v43_r17 = _metile_v41_r17 & _metile_v42_r17;\n bool _metile_v43_r18 = _metile_v41_r18 & _metile_v42_r18;\n bool _metile_v43_r19 = _metile_v41_r19 & _metile_v42_r19;\n bool _metile_v43_r20 = _metile_v41_r20 & _metile_v42_r20;\n bool _metile_v43_r21 = _metile_v41_r21 & _metile_v42_r21;\n bool _metile_v43_r22 = _metile_v41_r22 & _metile_v42_r22;\n bool _metile_v43_r23 = _metile_v41_r23 & _metile_v42_r23;\n bool _metile_v43_r24 = _metile_v41_r24 & _metile_v42_r24;\n bool _metile_v43_r25 = _metile_v41_r25 & _metile_v42_r25;\n bool _metile_v43_r26 = _metile_v41_r26 & _metile_v42_r26;\n bool _metile_v43_r27 = _metile_v41_r27 & _metile_v42_r27;\n bool _metile_v43_r28 = _metile_v41_r28 & _metile_v42_r28;\n bool _metile_v43_r29 = _metile_v41_r29 & _metile_v42_r29;\n bool _metile_v43_r30 = _metile_v41_r30 & _metile_v42_r30;\n bool _metile_v43_r31 = _metile_v41_r31 & _metile_v42_r31;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n int _off__metile_v44_r16 = v9 + _metile_register_index________________;\n int _off__metile_v44_r17 = v9 + _metile_register_index_________________;\n int _off__metile_v44_r18 = v9 + _metile_register_index__________________;\n int _off__metile_v44_r19 = v9 + _metile_register_index___________________;\n int _off__metile_v44_r20 = v9 + _metile_register_index____________________;\n int _off__metile_v44_r21 = v9 + _metile_register_index_____________________;\n int _off__metile_v44_r22 = v9 + _metile_register_index______________________;\n int _off__metile_v44_r23 = v9 + _metile_register_index_______________________;\n int _off__metile_v44_r24 = v9 + _metile_register_index________________________;\n int _off__metile_v44_r25 = v9 + _metile_register_index_________________________;\n int _off__metile_v44_r26 = v9 + _metile_register_index__________________________;\n int _off__metile_v44_r27 = v9 + _metile_register_index___________________________;\n int _off__metile_v44_r28 = v9 + _metile_register_index____________________________;\n int _off__metile_v44_r29 = v9 + _metile_register_index_____________________________;\n int _off__metile_v44_r30 = v9 + _metile_register_index______________________________;\n int _off__metile_v44_r31 = v9 + _metile_register_index_______________________________;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_half4(half4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_half4(half4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n if ((_metile_v43_r8) && (_metile_v43_r9) && (_metile_v43_r10) && (_metile_v43_r11) && (long(_off__metile_v44_r9) == long(_off__metile_v44_r8) + 1) && (long(_off__metile_v44_r10) == long(_off__metile_v44_r8) + 2) && (long(_off__metile_v44_r11) == long(_off__metile_v44_r8) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r8) = packed_half4(half4(static_cast(_metile_v39_r8), static_cast(_metile_v39_r9), static_cast(_metile_v39_r10), static_cast(_metile_v39_r11)));\n } else {\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = static_cast(_metile_v39_r8); }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = static_cast(_metile_v39_r9); }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = static_cast(_metile_v39_r10); }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = static_cast(_metile_v39_r11); }\n }\n if ((_metile_v43_r12) && (_metile_v43_r13) && (_metile_v43_r14) && (_metile_v43_r15) && (long(_off__metile_v44_r13) == long(_off__metile_v44_r12) + 1) && (long(_off__metile_v44_r14) == long(_off__metile_v44_r12) + 2) && (long(_off__metile_v44_r15) == long(_off__metile_v44_r12) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r12) = packed_half4(half4(static_cast(_metile_v39_r12), static_cast(_metile_v39_r13), static_cast(_metile_v39_r14), static_cast(_metile_v39_r15)));\n } else {\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = static_cast(_metile_v39_r12); }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = static_cast(_metile_v39_r13); }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = static_cast(_metile_v39_r14); }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = static_cast(_metile_v39_r15); }\n }\n if ((_metile_v43_r16) && (_metile_v43_r17) && (_metile_v43_r18) && (_metile_v43_r19) && (long(_off__metile_v44_r17) == long(_off__metile_v44_r16) + 1) && (long(_off__metile_v44_r18) == long(_off__metile_v44_r16) + 2) && (long(_off__metile_v44_r19) == long(_off__metile_v44_r16) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r16) = packed_half4(half4(static_cast(_metile_v39_r16), static_cast(_metile_v39_r17), static_cast(_metile_v39_r18), static_cast(_metile_v39_r19)));\n } else {\n if (_metile_v43_r16) { Out[_off__metile_v44_r16] = static_cast(_metile_v39_r16); }\n if (_metile_v43_r17) { Out[_off__metile_v44_r17] = static_cast(_metile_v39_r17); }\n if (_metile_v43_r18) { Out[_off__metile_v44_r18] = static_cast(_metile_v39_r18); }\n if (_metile_v43_r19) { Out[_off__metile_v44_r19] = static_cast(_metile_v39_r19); }\n }\n if ((_metile_v43_r20) && (_metile_v43_r21) && (_metile_v43_r22) && (_metile_v43_r23) && (long(_off__metile_v44_r21) == long(_off__metile_v44_r20) + 1) && (long(_off__metile_v44_r22) == long(_off__metile_v44_r20) + 2) && (long(_off__metile_v44_r23) == long(_off__metile_v44_r20) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r20) = packed_half4(half4(static_cast(_metile_v39_r20), static_cast(_metile_v39_r21), static_cast(_metile_v39_r22), static_cast(_metile_v39_r23)));\n } else {\n if (_metile_v43_r20) { Out[_off__metile_v44_r20] = static_cast(_metile_v39_r20); }\n if (_metile_v43_r21) { Out[_off__metile_v44_r21] = static_cast(_metile_v39_r21); }\n if (_metile_v43_r22) { Out[_off__metile_v44_r22] = static_cast(_metile_v39_r22); }\n if (_metile_v43_r23) { Out[_off__metile_v44_r23] = static_cast(_metile_v39_r23); }\n }\n if ((_metile_v43_r24) && (_metile_v43_r25) && (_metile_v43_r26) && (_metile_v43_r27) && (long(_off__metile_v44_r25) == long(_off__metile_v44_r24) + 1) && (long(_off__metile_v44_r26) == long(_off__metile_v44_r24) + 2) && (long(_off__metile_v44_r27) == long(_off__metile_v44_r24) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r24) = packed_half4(half4(static_cast(_metile_v39_r24), static_cast(_metile_v39_r25), static_cast(_metile_v39_r26), static_cast(_metile_v39_r27)));\n } else {\n if (_metile_v43_r24) { Out[_off__metile_v44_r24] = static_cast(_metile_v39_r24); }\n if (_metile_v43_r25) { Out[_off__metile_v44_r25] = static_cast(_metile_v39_r25); }\n if (_metile_v43_r26) { Out[_off__metile_v44_r26] = static_cast(_metile_v39_r26); }\n if (_metile_v43_r27) { Out[_off__metile_v44_r27] = static_cast(_metile_v39_r27); }\n }\n if ((_metile_v43_r28) && (_metile_v43_r29) && (_metile_v43_r30) && (_metile_v43_r31) && (long(_off__metile_v44_r29) == long(_off__metile_v44_r28) + 1) && (long(_off__metile_v44_r30) == long(_off__metile_v44_r28) + 2) && (long(_off__metile_v44_r31) == long(_off__metile_v44_r28) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r28) = packed_half4(half4(static_cast(_metile_v39_r28), static_cast(_metile_v39_r29), static_cast(_metile_v39_r30), static_cast(_metile_v39_r31)));\n } else {\n if (_metile_v43_r28) { Out[_off__metile_v44_r28] = static_cast(_metile_v39_r28); }\n if (_metile_v43_r29) { Out[_off__metile_v44_r29] = static_cast(_metile_v39_r29); }\n if (_metile_v43_r30) { Out[_off__metile_v44_r30] = static_cast(_metile_v39_r30); }\n if (_metile_v43_r31) { Out[_off__metile_v44_r31] = static_cast(_metile_v39_r31); }\n }\n}", "source_sha256": "56609b88a4b5b52c4d86d853e94eea93cb604868c18edef7efe33f8c98978f8f", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 32, 1, 1 ], "is_gemm": false, "prefer_ordered": false, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 32, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 32 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [], "double_buffered": false, "vectorized_loads": 16, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 32, "threads": 32, "scratch": null, "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 16, "grouped_stores": 8 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 407, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 318.54200000000003, "control": 305.875, "speedup": 0.9602344431817468 }, "gpu_us": { "candidate": 17.75001874193549, "control": 6.958318408578634, "speedup": 0.3920175245865621 } } }, { "frozen_register4": { "pairs": 407, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 316.5, "control": 305.375, "speedup": 0.9648499210110585 }, "gpu_us": { "candidate": 17.75001874193549, "control": 6.958318408578634, "speedup": 0.3920175245865621 } } }, { "frozen_register4": { "pairs": 408, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 317.8335, "control": 305.708, "speedup": 0.961849521840838 }, "gpu_us": { "candidate": 17.75001874193549, "control": 6.958318408578634, "speedup": 0.3920175245865621 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9623093960749318, "round_speedups": [ 0.9602344431817468, 0.9648499210110585, 0.961849521840838 ], "candidate": 317.62403779564835, "control": 305.6525959900116 }, "gpu_us": { "speedup": 0.392017524586562, "round_speedups": [ 0.3920175245865621, 0.3920175245865621, 0.3920175245865621 ], "candidate": 17.750018741935495, "control": 6.958318408578635 } } } }, { "name": "float16_1x1009", "dtype": "float16", "batches": 1, "width": 1009, "status": "measured", "variant": { "name": "register2_striped", "elements_per_thread": 2, "layout": "striped" }, "input_sha256": "20ffd5db614652b191eacaaeaec1d5949ec0b2eac97fa1cb02c0c6d776e088b5", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 511;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 512;\n int _metile_register_index_ = int(_metile_register_packed_);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n threadgroup float _metile_register_reduction[16];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 16u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n}", "source_sha256": "6b537a48d161d28743d3b80a917a7b5c4532cf32e542d68bd7d3a3e00bbe03ab", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 512, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 512, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 2 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 16, "bytes": 64 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 2, "threads": 512, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 416, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 305.54150000000004, "control": 306.27049999999997, "speedup": 1.0023859279345029 }, "gpu_us": { "candidate": 6.749993190169334, "control": 6.916699931025505, "speedup": 1.024697319857887 } } }, { "frozen_register4": { "pairs": 492, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 242.2705, "control": 247.667, "speedup": 1.0222746888292218 }, "gpu_us": { "candidate": 3.708351869136095, "control": 3.8333237171173096, "speedup": 1.0337001051656751 } } }, { "frozen_register4": { "pairs": 555, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 203.75, "control": 202.417, "speedup": 0.9934576687116564 }, "gpu_us": { "candidate": 1.5416881069540977, "control": 1.5833647921681404, "speedup": 1.027033149588462 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0059675658707736, "round_speedups": [ 1.0023859279345029, 1.0222746888292218, 0.9934576687116564 ], "candidate": 247.07157656191754, "control": 248.54599246984648 }, "gpu_us": { "speedup": 1.0284697933246711, "round_speedups": [ 1.024697319857887, 1.0337001051656751, 1.027033149588462 ], "candidate": 3.379301420273711, "control": 3.4755094332906697 } } } }, { "name": "float16_32x1009", "dtype": "float16", "batches": 32, "width": 1009, "status": "measured", "variant": { "name": "register4_blocked4", "elements_per_thread": 4, "layout": "blocked4" }, "input_sha256": "e6d696cff86bdf9ec8254c3438c13725f24b2b1f6073b44660a256dcea0488a8", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int((((_metile_bounded_thread >> 8) & 1u) << 0) | (((_metile_bounded_thread >> 9) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 6) & 1u) << 8) | (((_metile_bounded_thread >> 7) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 8) & 1u) << 0) | (((_metile_register_packed_ >> 9) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 6) & 1u) << 8) | (((_metile_register_packed_ >> 7) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 8) & 1u) << 0) | (((_metile_register_packed__ >> 9) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 6) & 1u) << 8) | (((_metile_register_packed__ >> 7) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 8) & 1u) << 0) | (((_metile_register_packed___ >> 9) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 6) & 1u) << 8) | (((_metile_register_packed___ >> 7) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = half4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n half _metile_v20_r0 = _metile_vector_load[0];\n half _metile_v20_r1 = _metile_vector_load[1];\n half _metile_v20_r2 = _metile_vector_load[2];\n half _metile_v20_r3 = _metile_vector_load[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half4 _metile_vector_load_;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load_ = half4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load_[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load_[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load_[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load_[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n half _metile_v36_r0 = _metile_vector_load_[0];\n half _metile_v36_r1 = _metile_vector_load_[1];\n half _metile_v36_r2 = _metile_vector_load_[2];\n half _metile_v36_r3 = _metile_vector_load_[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_half4(half4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n}", "source_sha256": "32e68c0449ebffcd9bddb41f7a561299b60a076baf9a7d4067b0b3e1392256c7", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 2, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 2, "grouped_stores": 1 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 613, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.5, "control": 201.0, "speedup": 1.0075187969924813 }, "gpu_us": { "candidate": 2.291635610163212, "control": 2.0416919142007828, "speedup": 0.8909321818643637 } } }, { "frozen_register4": { "pairs": 611, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.875, "control": 200.125, "speedup": 0.9962663347853142 }, "gpu_us": { "candidate": 2.2500171326100826, "control": 2.0416919142007828, "speedup": 0.9074117190531626 } } }, { "frozen_register4": { "pairs": 622, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.79149999999998, "control": 197.8955, "speedup": 1.0005258062151305 }, "gpu_us": { "candidate": 2.291635610163212, "control": 2.0416919142007828, "speedup": 0.8909321818643637 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0014262451268168, "round_speedups": [ 1.0075187969924813, 0.9962663347853142, 1.0005258062151305 ], "candidate": 199.38484174751144, "control": 199.66921340641494 }, "gpu_us": { "speedup": 0.8963918356958074, "round_speedups": [ 0.8909321818643637, 0.9074117190531626, 0.8909321818643637 ], "candidate": 2.277677944953568, "control": 2.0416919142007828 } } } }, { "name": "float16_32x1009", "dtype": "float16", "batches": 32, "width": 1009, "status": "measured", "variant": { "name": "register8_striped", "elements_per_thread": 8, "layout": "striped" }, "input_sha256": "e6d696cff86bdf9ec8254c3438c13725f24b2b1f6073b44660a256dcea0488a8", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 127;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 128;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 256;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 384;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 512;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 640;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 768;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 896;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n half _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n half _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n half _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n half _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_____ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum______ = _metile_register_sum____ + _metile_register_sum_____;\n threadgroup float _metile_register_reduction[4];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 4u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n half _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n half _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n half _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n half _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n}", "source_sha256": "b4460a3d9f572d27169c13ec23164de0b27d29f07cf7c168c5a7763c87c06b01", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 128, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 128, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 8 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 4, "bytes": 16 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 8, "threads": 128, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 617, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.417, "control": 198.375, "speedup": 0.9898112435571833 }, "gpu_us": { "candidate": 2.0416919142007828, "control": 2.00001522898674, "speedup": 0.9795871821188277 } } }, { "frozen_register4": { "pairs": 615, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.25, "control": 198.959, "speedup": 0.9985395232120452 }, "gpu_us": { "candidate": 2.0416919142007828, "control": 2.00001522898674, "speedup": 0.9795871821188277 } } }, { "frozen_register4": { "pairs": 614, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.4995, "control": 199.313, "speedup": 0.9940822795069313 }, "gpu_us": { "candidate": 2.0416919142007828, "control": 2.00001522898674, "speedup": 0.9795871821188277 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.994137962181422, "round_speedups": [ 0.9898112435571833, 0.9985395232120452, 0.9940822795069313 ], "candidate": 200.05468527192056, "control": 198.8819571410728 }, "gpu_us": { "speedup": 0.9795871821188277, "round_speedups": [ 0.9795871821188277, 0.9795871821188277, 0.9795871821188277 ], "candidate": 2.0416919142007828, "control": 2.00001522898674 } } } }, { "name": "float16_32x1009", "dtype": "float16", "batches": 32, "width": 1009, "status": "measured", "variant": { "name": "register8_blocked4", "elements_per_thread": 8, "layout": "blocked4" }, "input_sha256": "e6d696cff86bdf9ec8254c3438c13725f24b2b1f6073b44660a256dcea0488a8", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 127;\n int _metile_register_index = int((((_metile_bounded_thread >> 7) & 1u) << 0) | (((_metile_bounded_thread >> 8) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 6) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 128;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 7) & 1u) << 0) | (((_metile_register_packed_ >> 8) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 6) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 256;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 7) & 1u) << 0) | (((_metile_register_packed__ >> 8) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 6) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 384;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 7) & 1u) << 0) | (((_metile_register_packed___ >> 8) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 6) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 512;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 7) & 1u) << 0) | (((_metile_register_packed____ >> 8) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 5) & 1u) << 7) | (((_metile_register_packed____ >> 6) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 640;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 7) & 1u) << 0) | (((_metile_register_packed_____ >> 8) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 5) & 1u) << 7) | (((_metile_register_packed_____ >> 6) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 768;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 7) & 1u) << 0) | (((_metile_register_packed______ >> 8) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 5) & 1u) << 7) | (((_metile_register_packed______ >> 6) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 896;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 7) & 1u) << 0) | (((_metile_register_packed_______ >> 8) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 5) & 1u) << 7) | (((_metile_register_packed_______ >> 6) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n half4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = half4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n half _metile_v20_r0 = _metile_vector_load[0];\n half _metile_v20_r1 = _metile_vector_load[1];\n half _metile_v20_r2 = _metile_vector_load[2];\n half _metile_v20_r3 = _metile_vector_load[3];\n half4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = half4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n half _metile_v20_r4 = _metile_vector_load_[0];\n half _metile_v20_r5 = _metile_vector_load_[1];\n half _metile_v20_r6 = _metile_vector_load_[2];\n half _metile_v20_r7 = _metile_vector_load_[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_____ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum______ = _metile_register_sum____ + _metile_register_sum_____;\n threadgroup float _metile_register_reduction[4];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 4u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n half4 _metile_vector_load__;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load__ = half4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load__[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load__[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load__[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load__[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n half _metile_v36_r0 = _metile_vector_load__[0];\n half _metile_v36_r1 = _metile_vector_load__[1];\n half _metile_v36_r2 = _metile_vector_load__[2];\n half _metile_v36_r3 = _metile_vector_load__[3];\n half4 _metile_vector_load___;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load___ = half4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load___[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load___[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load___[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load___[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n half _metile_v36_r4 = _metile_vector_load___[0];\n half _metile_v36_r5 = _metile_vector_load___[1];\n half _metile_v36_r6 = _metile_vector_load___[2];\n half _metile_v36_r7 = _metile_vector_load___[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_half4(half4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_half4(half4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n}", "source_sha256": "4aeb4ec992d7174b6182b507a2b9a716bd1f0d8ebc18857adde04ecf0d617fd7", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 128, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 128, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 8 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 4, "bytes": 16 } ], "double_buffered": false, "vectorized_loads": 4, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 8, "threads": 128, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 4, "grouped_stores": 2 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 615, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.959, "control": 200.917, "speedup": 0.9997910021447161 }, "gpu_us": { "candidate": 2.374988980591297, "control": 2.00001522898674, "speedup": 0.8421155825694819 } } }, { "frozen_register4": { "pairs": 616, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.25, "control": 199.5205, "speedup": 1.001357590966123 }, "gpu_us": { "candidate": 2.374988980591297, "control": 2.00001522898674, "speedup": 0.8421155825694819 } } }, { "frozen_register4": { "pairs": 617, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.833, "control": 199.583, "speedup": 1.0037720096764622 }, "gpu_us": { "candidate": 2.374988980591297, "control": 2.00001522898674, "speedup": 0.8421155825694819 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0016388628239805, "round_speedups": [ 0.9997910021447161, 1.001357590966123, 1.0037720096764622 ], "candidate": 199.67855203920573, "control": 200.00579779488905 }, "gpu_us": { "speedup": 0.8421155825694819, "round_speedups": [ 0.8421155825694819, 0.8421155825694819, 0.8421155825694819 ], "candidate": 2.374988980591297, "control": 2.00001522898674 } } } }, { "name": "float16_32x1009", "dtype": "float16", "batches": 32, "width": 1009, "status": "measured", "variant": { "name": "register16_striped", "elements_per_thread": 16, "layout": "striped" }, "input_sha256": "e6d696cff86bdf9ec8254c3438c13725f24b2b1f6073b44660a256dcea0488a8", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 63;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 64;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 128;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 192;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 256;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 320;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 384;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 448;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n int _metile_register_packed________ = _metile_bounded_thread + 512;\n int _metile_register_index________ = int(_metile_register_packed________);\n int _metile_register_packed_________ = _metile_bounded_thread + 576;\n int _metile_register_index_________ = int(_metile_register_packed_________);\n int _metile_register_packed__________ = _metile_bounded_thread + 640;\n int _metile_register_index__________ = int(_metile_register_packed__________);\n int _metile_register_packed___________ = _metile_bounded_thread + 704;\n int _metile_register_index___________ = int(_metile_register_packed___________);\n int _metile_register_packed____________ = _metile_bounded_thread + 768;\n int _metile_register_index____________ = int(_metile_register_packed____________);\n int _metile_register_packed_____________ = _metile_bounded_thread + 832;\n int _metile_register_index_____________ = int(_metile_register_packed_____________);\n int _metile_register_packed______________ = _metile_bounded_thread + 896;\n int _metile_register_index______________ = int(_metile_register_packed______________);\n int _metile_register_packed_______________ = _metile_bounded_thread + 960;\n int _metile_register_index_______________ = int(_metile_register_packed_______________);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v17_r8 = _metile_register_index________ < 1009;\n bool _metile_v17_r9 = _metile_register_index_________ < 1009;\n bool _metile_v17_r10 = _metile_register_index__________ < 1009;\n bool _metile_v17_r11 = _metile_register_index___________ < 1009;\n bool _metile_v17_r12 = _metile_register_index____________ < 1009;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v17_r14 = _metile_register_index______________ < 1009;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n half _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n half _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n half _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n half _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n half _metile_v20_r8 = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n half _metile_v20_r9 = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n half _metile_v20_r10 = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n half _metile_v20_r11 = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n half _metile_v20_r12 = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n half _metile_v20_r13 = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n half _metile_v20_r14 = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n half _metile_v20_r15 = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________ = _metile_register_sum____________ + _metile_register_sum_____________;\n threadgroup float _metile_register_reduction[2];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______________);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 2u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v33_r8 = _metile_register_index________ < 1009;\n bool _metile_v33_r9 = _metile_register_index_________ < 1009;\n bool _metile_v33_r10 = _metile_register_index__________ < 1009;\n bool _metile_v33_r11 = _metile_register_index___________ < 1009;\n bool _metile_v33_r12 = _metile_register_index____________ < 1009;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v33_r14 = _metile_register_index______________ < 1009;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n half _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n half _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n half _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n half _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n half _metile_v36_r8 = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n half _metile_v36_r9 = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n half _metile_v36_r10 = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n half _metile_v36_r11 = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n half _metile_v36_r12 = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n half _metile_v36_r13 = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n half _metile_v36_r14 = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n half _metile_v36_r15 = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v42_r8 = _metile_register_index________ < 1009;\n bool _metile_v42_r9 = _metile_register_index_________ < 1009;\n bool _metile_v42_r10 = _metile_register_index__________ < 1009;\n bool _metile_v42_r11 = _metile_register_index___________ < 1009;\n bool _metile_v42_r12 = _metile_register_index____________ < 1009;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v42_r14 = _metile_register_index______________ < 1009;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = _metile_v39_r8; }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = _metile_v39_r9; }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = _metile_v39_r10; }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = _metile_v39_r11; }\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = _metile_v39_r12; }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = _metile_v39_r13; }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = _metile_v39_r14; }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = _metile_v39_r15; }\n}", "source_sha256": "fabd6e8e22cb59371bb98555d949a21e2b779ed4e5b695612d2857b9566e1617", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 64, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 64, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 16 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 2, "bytes": 8 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 16, "threads": 64, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 599, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.625, "control": 199.042, "speedup": 0.9921096573208723 }, "gpu_us": { "candidate": 2.1249870769679546, "control": 2.00001522898674, "speedup": 0.9411893609444764 } } }, { "frozen_register4": { "pairs": 617, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.459, "control": 199.375, "speedup": 0.9995788608185141 }, "gpu_us": { "candidate": 2.1249870769679546, "control": 2.00001522898674, "speedup": 0.9411893609444764 } } }, { "frozen_register4": { "pairs": 547, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 205.625, "control": 204.875, "speedup": 0.9963525835866262 }, "gpu_us": { "candidate": 2.1249870769679546, "control": 2.0416337065398693, "speedup": 0.9607746459583094 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9960090024527658, "round_speedups": [ 0.9921096573208723, 0.9995788608185141, 0.9963525835866262 ], "candidate": 201.88537899012633, "control": 201.07965493775438 }, "gpu_us": { "speedup": 0.9476730221039344, "round_speedups": [ 0.9411893609444764, 0.9411893609444764, 0.9607746459583094 ], "candidate": 2.1249870769679546, "control": 2.0137929251620275 } } } }, { "name": "float16_32x1009", "dtype": "float16", "batches": 32, "width": 1009, "status": "measured", "variant": { "name": "register16_blocked4", "elements_per_thread": 16, "layout": "blocked4" }, "input_sha256": "e6d696cff86bdf9ec8254c3438c13725f24b2b1f6073b44660a256dcea0488a8", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 63;\n int _metile_register_index = int((((_metile_bounded_thread >> 6) & 1u) << 0) | (((_metile_bounded_thread >> 7) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 8) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 64;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 6) & 1u) << 0) | (((_metile_register_packed_ >> 7) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 8) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 128;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 6) & 1u) << 0) | (((_metile_register_packed__ >> 7) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 8) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 192;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 6) & 1u) << 0) | (((_metile_register_packed___ >> 7) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 8) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 256;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 6) & 1u) << 0) | (((_metile_register_packed____ >> 7) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 5) & 1u) << 7) | (((_metile_register_packed____ >> 8) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 320;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 6) & 1u) << 0) | (((_metile_register_packed_____ >> 7) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 5) & 1u) << 7) | (((_metile_register_packed_____ >> 8) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 384;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 6) & 1u) << 0) | (((_metile_register_packed______ >> 7) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 5) & 1u) << 7) | (((_metile_register_packed______ >> 8) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 448;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 6) & 1u) << 0) | (((_metile_register_packed_______ >> 7) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 5) & 1u) << 7) | (((_metile_register_packed_______ >> 8) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n int _metile_register_packed________ = _metile_bounded_thread + 512;\n int _metile_register_index________ = int((((_metile_register_packed________ >> 6) & 1u) << 0) | (((_metile_register_packed________ >> 7) & 1u) << 1) | (((_metile_register_packed________ >> 0) & 1u) << 2) | (((_metile_register_packed________ >> 1) & 1u) << 3) | (((_metile_register_packed________ >> 2) & 1u) << 4) | (((_metile_register_packed________ >> 3) & 1u) << 5) | (((_metile_register_packed________ >> 4) & 1u) << 6) | (((_metile_register_packed________ >> 5) & 1u) << 7) | (((_metile_register_packed________ >> 8) & 1u) << 8) | (((_metile_register_packed________ >> 9) & 1u) << 9));\n int _metile_register_packed_________ = _metile_bounded_thread + 576;\n int _metile_register_index_________ = int((((_metile_register_packed_________ >> 6) & 1u) << 0) | (((_metile_register_packed_________ >> 7) & 1u) << 1) | (((_metile_register_packed_________ >> 0) & 1u) << 2) | (((_metile_register_packed_________ >> 1) & 1u) << 3) | (((_metile_register_packed_________ >> 2) & 1u) << 4) | (((_metile_register_packed_________ >> 3) & 1u) << 5) | (((_metile_register_packed_________ >> 4) & 1u) << 6) | (((_metile_register_packed_________ >> 5) & 1u) << 7) | (((_metile_register_packed_________ >> 8) & 1u) << 8) | (((_metile_register_packed_________ >> 9) & 1u) << 9));\n int _metile_register_packed__________ = _metile_bounded_thread + 640;\n int _metile_register_index__________ = int((((_metile_register_packed__________ >> 6) & 1u) << 0) | (((_metile_register_packed__________ >> 7) & 1u) << 1) | (((_metile_register_packed__________ >> 0) & 1u) << 2) | (((_metile_register_packed__________ >> 1) & 1u) << 3) | (((_metile_register_packed__________ >> 2) & 1u) << 4) | (((_metile_register_packed__________ >> 3) & 1u) << 5) | (((_metile_register_packed__________ >> 4) & 1u) << 6) | (((_metile_register_packed__________ >> 5) & 1u) << 7) | (((_metile_register_packed__________ >> 8) & 1u) << 8) | (((_metile_register_packed__________ >> 9) & 1u) << 9));\n int _metile_register_packed___________ = _metile_bounded_thread + 704;\n int _metile_register_index___________ = int((((_metile_register_packed___________ >> 6) & 1u) << 0) | (((_metile_register_packed___________ >> 7) & 1u) << 1) | (((_metile_register_packed___________ >> 0) & 1u) << 2) | (((_metile_register_packed___________ >> 1) & 1u) << 3) | (((_metile_register_packed___________ >> 2) & 1u) << 4) | (((_metile_register_packed___________ >> 3) & 1u) << 5) | (((_metile_register_packed___________ >> 4) & 1u) << 6) | (((_metile_register_packed___________ >> 5) & 1u) << 7) | (((_metile_register_packed___________ >> 8) & 1u) << 8) | (((_metile_register_packed___________ >> 9) & 1u) << 9));\n int _metile_register_packed____________ = _metile_bounded_thread + 768;\n int _metile_register_index____________ = int((((_metile_register_packed____________ >> 6) & 1u) << 0) | (((_metile_register_packed____________ >> 7) & 1u) << 1) | (((_metile_register_packed____________ >> 0) & 1u) << 2) | (((_metile_register_packed____________ >> 1) & 1u) << 3) | (((_metile_register_packed____________ >> 2) & 1u) << 4) | (((_metile_register_packed____________ >> 3) & 1u) << 5) | (((_metile_register_packed____________ >> 4) & 1u) << 6) | (((_metile_register_packed____________ >> 5) & 1u) << 7) | (((_metile_register_packed____________ >> 8) & 1u) << 8) | (((_metile_register_packed____________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________ = _metile_bounded_thread + 832;\n int _metile_register_index_____________ = int((((_metile_register_packed_____________ >> 6) & 1u) << 0) | (((_metile_register_packed_____________ >> 7) & 1u) << 1) | (((_metile_register_packed_____________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________ >> 5) & 1u) << 7) | (((_metile_register_packed_____________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________ >> 9) & 1u) << 9));\n int _metile_register_packed______________ = _metile_bounded_thread + 896;\n int _metile_register_index______________ = int((((_metile_register_packed______________ >> 6) & 1u) << 0) | (((_metile_register_packed______________ >> 7) & 1u) << 1) | (((_metile_register_packed______________ >> 0) & 1u) << 2) | (((_metile_register_packed______________ >> 1) & 1u) << 3) | (((_metile_register_packed______________ >> 2) & 1u) << 4) | (((_metile_register_packed______________ >> 3) & 1u) << 5) | (((_metile_register_packed______________ >> 4) & 1u) << 6) | (((_metile_register_packed______________ >> 5) & 1u) << 7) | (((_metile_register_packed______________ >> 8) & 1u) << 8) | (((_metile_register_packed______________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________ = _metile_bounded_thread + 960;\n int _metile_register_index_______________ = int((((_metile_register_packed_______________ >> 6) & 1u) << 0) | (((_metile_register_packed_______________ >> 7) & 1u) << 1) | (((_metile_register_packed_______________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________ >> 5) & 1u) << 7) | (((_metile_register_packed_______________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v17_r8 = _metile_register_index________ < 1009;\n bool _metile_v17_r9 = _metile_register_index_________ < 1009;\n bool _metile_v17_r10 = _metile_register_index__________ < 1009;\n bool _metile_v17_r11 = _metile_register_index___________ < 1009;\n bool _metile_v17_r12 = _metile_register_index____________ < 1009;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v17_r14 = _metile_register_index______________ < 1009;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n half4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = half4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n half _metile_v20_r0 = _metile_vector_load[0];\n half _metile_v20_r1 = _metile_vector_load[1];\n half _metile_v20_r2 = _metile_vector_load[2];\n half _metile_v20_r3 = _metile_vector_load[3];\n half4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = half4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n half _metile_v20_r4 = _metile_vector_load_[0];\n half _metile_v20_r5 = _metile_vector_load_[1];\n half _metile_v20_r6 = _metile_vector_load_[2];\n half _metile_v20_r7 = _metile_vector_load_[3];\n half4 _metile_vector_load__;\n if ((_metile_v18_r8) && (_metile_v18_r9) && (_metile_v18_r10) && (_metile_v18_r11) && (long(_off__metile_v19_r9) == long(_off__metile_v19_r8) + 1) && (long(_off__metile_v19_r10) == long(_off__metile_v19_r8) + 2) && (long(_off__metile_v19_r11) == long(_off__metile_v19_r8) + 3)) {\n _metile_vector_load__ = half4(*reinterpret_cast(X + _off__metile_v19_r8));\n } else {\n _metile_vector_load__[0] = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n _metile_vector_load__[1] = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n _metile_vector_load__[2] = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n _metile_vector_load__[3] = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n }\n half _metile_v20_r8 = _metile_vector_load__[0];\n half _metile_v20_r9 = _metile_vector_load__[1];\n half _metile_v20_r10 = _metile_vector_load__[2];\n half _metile_v20_r11 = _metile_vector_load__[3];\n half4 _metile_vector_load___;\n if ((_metile_v18_r12) && (_metile_v18_r13) && (_metile_v18_r14) && (_metile_v18_r15) && (long(_off__metile_v19_r13) == long(_off__metile_v19_r12) + 1) && (long(_off__metile_v19_r14) == long(_off__metile_v19_r12) + 2) && (long(_off__metile_v19_r15) == long(_off__metile_v19_r12) + 3)) {\n _metile_vector_load___ = half4(*reinterpret_cast(X + _off__metile_v19_r12));\n } else {\n _metile_vector_load___[0] = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n _metile_vector_load___[1] = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n _metile_vector_load___[2] = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n _metile_vector_load___[3] = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n }\n half _metile_v20_r12 = _metile_vector_load___[0];\n half _metile_v20_r13 = _metile_vector_load___[1];\n half _metile_v20_r14 = _metile_vector_load___[2];\n half _metile_v20_r15 = _metile_vector_load___[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________ = _metile_register_sum____________ + _metile_register_sum_____________;\n threadgroup float _metile_register_reduction[2];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______________);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 2u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v33_r8 = _metile_register_index________ < 1009;\n bool _metile_v33_r9 = _metile_register_index_________ < 1009;\n bool _metile_v33_r10 = _metile_register_index__________ < 1009;\n bool _metile_v33_r11 = _metile_register_index___________ < 1009;\n bool _metile_v33_r12 = _metile_register_index____________ < 1009;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v33_r14 = _metile_register_index______________ < 1009;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n half4 _metile_vector_load____;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load____ = half4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load____[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load____[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load____[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load____[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n half _metile_v36_r0 = _metile_vector_load____[0];\n half _metile_v36_r1 = _metile_vector_load____[1];\n half _metile_v36_r2 = _metile_vector_load____[2];\n half _metile_v36_r3 = _metile_vector_load____[3];\n half4 _metile_vector_load_____;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load_____ = half4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load_____[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load_____[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load_____[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load_____[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n half _metile_v36_r4 = _metile_vector_load_____[0];\n half _metile_v36_r5 = _metile_vector_load_____[1];\n half _metile_v36_r6 = _metile_vector_load_____[2];\n half _metile_v36_r7 = _metile_vector_load_____[3];\n half4 _metile_vector_load______;\n if ((_metile_v34_r8) && (_metile_v34_r9) && (_metile_v34_r10) && (_metile_v34_r11) && (long(_metile_register_index_________) == long(_metile_register_index________) + 1) && (long(_metile_register_index__________) == long(_metile_register_index________) + 2) && (long(_metile_register_index___________) == long(_metile_register_index________) + 3)) {\n _metile_vector_load______ = half4(*reinterpret_cast(W + _metile_register_index________));\n } else {\n _metile_vector_load______[0] = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n _metile_vector_load______[1] = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n _metile_vector_load______[2] = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n _metile_vector_load______[3] = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n }\n half _metile_v36_r8 = _metile_vector_load______[0];\n half _metile_v36_r9 = _metile_vector_load______[1];\n half _metile_v36_r10 = _metile_vector_load______[2];\n half _metile_v36_r11 = _metile_vector_load______[3];\n half4 _metile_vector_load_______;\n if ((_metile_v34_r12) && (_metile_v34_r13) && (_metile_v34_r14) && (_metile_v34_r15) && (long(_metile_register_index_____________) == long(_metile_register_index____________) + 1) && (long(_metile_register_index______________) == long(_metile_register_index____________) + 2) && (long(_metile_register_index_______________) == long(_metile_register_index____________) + 3)) {\n _metile_vector_load_______ = half4(*reinterpret_cast(W + _metile_register_index____________));\n } else {\n _metile_vector_load_______[0] = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n _metile_vector_load_______[1] = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n _metile_vector_load_______[2] = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n _metile_vector_load_______[3] = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n }\n half _metile_v36_r12 = _metile_vector_load_______[0];\n half _metile_v36_r13 = _metile_vector_load_______[1];\n half _metile_v36_r14 = _metile_vector_load_______[2];\n half _metile_v36_r15 = _metile_vector_load_______[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v42_r8 = _metile_register_index________ < 1009;\n bool _metile_v42_r9 = _metile_register_index_________ < 1009;\n bool _metile_v42_r10 = _metile_register_index__________ < 1009;\n bool _metile_v42_r11 = _metile_register_index___________ < 1009;\n bool _metile_v42_r12 = _metile_register_index____________ < 1009;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v42_r14 = _metile_register_index______________ < 1009;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_half4(half4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_half4(half4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n if ((_metile_v43_r8) && (_metile_v43_r9) && (_metile_v43_r10) && (_metile_v43_r11) && (long(_off__metile_v44_r9) == long(_off__metile_v44_r8) + 1) && (long(_off__metile_v44_r10) == long(_off__metile_v44_r8) + 2) && (long(_off__metile_v44_r11) == long(_off__metile_v44_r8) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r8) = packed_half4(half4(static_cast(_metile_v39_r8), static_cast(_metile_v39_r9), static_cast(_metile_v39_r10), static_cast(_metile_v39_r11)));\n } else {\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = static_cast(_metile_v39_r8); }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = static_cast(_metile_v39_r9); }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = static_cast(_metile_v39_r10); }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = static_cast(_metile_v39_r11); }\n }\n if ((_metile_v43_r12) && (_metile_v43_r13) && (_metile_v43_r14) && (_metile_v43_r15) && (long(_off__metile_v44_r13) == long(_off__metile_v44_r12) + 1) && (long(_off__metile_v44_r14) == long(_off__metile_v44_r12) + 2) && (long(_off__metile_v44_r15) == long(_off__metile_v44_r12) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r12) = packed_half4(half4(static_cast(_metile_v39_r12), static_cast(_metile_v39_r13), static_cast(_metile_v39_r14), static_cast(_metile_v39_r15)));\n } else {\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = static_cast(_metile_v39_r12); }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = static_cast(_metile_v39_r13); }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = static_cast(_metile_v39_r14); }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = static_cast(_metile_v39_r15); }\n }\n}", "source_sha256": "69ca6afa69b470e096587fff61d2aae73d540a3d5a9f5d7c7e10d9537062ec50", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 64, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 64, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 16 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 2, "bytes": 8 } ], "double_buffered": false, "vectorized_loads": 8, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 16, "threads": 64, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 8, "grouped_stores": 4 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 617, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.208, "control": 199.334, "speedup": 1.000632504718686 }, "gpu_us": { "candidate": 3.00002284348011, "control": 2.00001522898674, "speedup": 0.6666666666666666 } } }, { "frozen_register4": { "pairs": 621, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.833, "control": 198.625, "speedup": 1.0040033765853018 }, "gpu_us": { "candidate": 3.041699528694153, "control": 2.0416337065398693, "speedup": 0.6712147887323944 } } }, { "frozen_register4": { "pairs": 589, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.583, "control": 198.792, "speedup": 1.0061189474802994 }, "gpu_us": { "candidate": 3.041699528694153, "control": 2.0416337065398693, "speedup": 0.6712147887323944 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0035823988095052, "round_speedups": [ 1.000632504718686, 1.0040033765853018, 1.0061189474802994 ], "candidate": 198.20671440189366, "control": 198.91676989960297 }, "gpu_us": { "speedup": 0.6696953108866625, "round_speedups": [ 0.6666666666666666, 0.6712147887323944, 0.6712147887323944 ], "candidate": 3.0277433634498254, "control": 2.0276655330705595 } } } }, { "name": "float16_32x1009", "dtype": "float16", "batches": 32, "width": 1009, "status": "measured", "variant": { "name": "register32_striped", "elements_per_thread": 32, "layout": "striped" }, "input_sha256": "e6d696cff86bdf9ec8254c3438c13725f24b2b1f6073b44660a256dcea0488a8", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 31;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 32;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 64;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 96;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 128;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 160;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 192;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 224;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n int _metile_register_packed________ = _metile_bounded_thread + 256;\n int _metile_register_index________ = int(_metile_register_packed________);\n int _metile_register_packed_________ = _metile_bounded_thread + 288;\n int _metile_register_index_________ = int(_metile_register_packed_________);\n int _metile_register_packed__________ = _metile_bounded_thread + 320;\n int _metile_register_index__________ = int(_metile_register_packed__________);\n int _metile_register_packed___________ = _metile_bounded_thread + 352;\n int _metile_register_index___________ = int(_metile_register_packed___________);\n int _metile_register_packed____________ = _metile_bounded_thread + 384;\n int _metile_register_index____________ = int(_metile_register_packed____________);\n int _metile_register_packed_____________ = _metile_bounded_thread + 416;\n int _metile_register_index_____________ = int(_metile_register_packed_____________);\n int _metile_register_packed______________ = _metile_bounded_thread + 448;\n int _metile_register_index______________ = int(_metile_register_packed______________);\n int _metile_register_packed_______________ = _metile_bounded_thread + 480;\n int _metile_register_index_______________ = int(_metile_register_packed_______________);\n int _metile_register_packed________________ = _metile_bounded_thread + 512;\n int _metile_register_index________________ = int(_metile_register_packed________________);\n int _metile_register_packed_________________ = _metile_bounded_thread + 544;\n int _metile_register_index_________________ = int(_metile_register_packed_________________);\n int _metile_register_packed__________________ = _metile_bounded_thread + 576;\n int _metile_register_index__________________ = int(_metile_register_packed__________________);\n int _metile_register_packed___________________ = _metile_bounded_thread + 608;\n int _metile_register_index___________________ = int(_metile_register_packed___________________);\n int _metile_register_packed____________________ = _metile_bounded_thread + 640;\n int _metile_register_index____________________ = int(_metile_register_packed____________________);\n int _metile_register_packed_____________________ = _metile_bounded_thread + 672;\n int _metile_register_index_____________________ = int(_metile_register_packed_____________________);\n int _metile_register_packed______________________ = _metile_bounded_thread + 704;\n int _metile_register_index______________________ = int(_metile_register_packed______________________);\n int _metile_register_packed_______________________ = _metile_bounded_thread + 736;\n int _metile_register_index_______________________ = int(_metile_register_packed_______________________);\n int _metile_register_packed________________________ = _metile_bounded_thread + 768;\n int _metile_register_index________________________ = int(_metile_register_packed________________________);\n int _metile_register_packed_________________________ = _metile_bounded_thread + 800;\n int _metile_register_index_________________________ = int(_metile_register_packed_________________________);\n int _metile_register_packed__________________________ = _metile_bounded_thread + 832;\n int _metile_register_index__________________________ = int(_metile_register_packed__________________________);\n int _metile_register_packed___________________________ = _metile_bounded_thread + 864;\n int _metile_register_index___________________________ = int(_metile_register_packed___________________________);\n int _metile_register_packed____________________________ = _metile_bounded_thread + 896;\n int _metile_register_index____________________________ = int(_metile_register_packed____________________________);\n int _metile_register_packed_____________________________ = _metile_bounded_thread + 928;\n int _metile_register_index_____________________________ = int(_metile_register_packed_____________________________);\n int _metile_register_packed______________________________ = _metile_bounded_thread + 960;\n int _metile_register_index______________________________ = int(_metile_register_packed______________________________);\n int _metile_register_packed_______________________________ = _metile_bounded_thread + 992;\n int _metile_register_index_______________________________ = int(_metile_register_packed_______________________________);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v16_r16 = _metile_register_index________________ >= 0;\n bool _metile_v16_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v16_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v16_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v16_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v16_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v16_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v16_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v16_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v16_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v16_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v16_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v16_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v16_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v16_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v16_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v17_r8 = _metile_register_index________ < 1009;\n bool _metile_v17_r9 = _metile_register_index_________ < 1009;\n bool _metile_v17_r10 = _metile_register_index__________ < 1009;\n bool _metile_v17_r11 = _metile_register_index___________ < 1009;\n bool _metile_v17_r12 = _metile_register_index____________ < 1009;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v17_r14 = _metile_register_index______________ < 1009;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v17_r16 = _metile_register_index________________ < 1009;\n bool _metile_v17_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v17_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v17_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v17_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v17_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v17_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v17_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v17_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v17_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v17_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v17_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v17_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v17_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v17_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v17_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n bool _metile_v18_r16 = _metile_v16_r16 & _metile_v17_r16;\n bool _metile_v18_r17 = _metile_v16_r17 & _metile_v17_r17;\n bool _metile_v18_r18 = _metile_v16_r18 & _metile_v17_r18;\n bool _metile_v18_r19 = _metile_v16_r19 & _metile_v17_r19;\n bool _metile_v18_r20 = _metile_v16_r20 & _metile_v17_r20;\n bool _metile_v18_r21 = _metile_v16_r21 & _metile_v17_r21;\n bool _metile_v18_r22 = _metile_v16_r22 & _metile_v17_r22;\n bool _metile_v18_r23 = _metile_v16_r23 & _metile_v17_r23;\n bool _metile_v18_r24 = _metile_v16_r24 & _metile_v17_r24;\n bool _metile_v18_r25 = _metile_v16_r25 & _metile_v17_r25;\n bool _metile_v18_r26 = _metile_v16_r26 & _metile_v17_r26;\n bool _metile_v18_r27 = _metile_v16_r27 & _metile_v17_r27;\n bool _metile_v18_r28 = _metile_v16_r28 & _metile_v17_r28;\n bool _metile_v18_r29 = _metile_v16_r29 & _metile_v17_r29;\n bool _metile_v18_r30 = _metile_v16_r30 & _metile_v17_r30;\n bool _metile_v18_r31 = _metile_v16_r31 & _metile_v17_r31;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n int _off__metile_v19_r16 = v2 + _metile_register_index________________;\n int _off__metile_v19_r17 = v2 + _metile_register_index_________________;\n int _off__metile_v19_r18 = v2 + _metile_register_index__________________;\n int _off__metile_v19_r19 = v2 + _metile_register_index___________________;\n int _off__metile_v19_r20 = v2 + _metile_register_index____________________;\n int _off__metile_v19_r21 = v2 + _metile_register_index_____________________;\n int _off__metile_v19_r22 = v2 + _metile_register_index______________________;\n int _off__metile_v19_r23 = v2 + _metile_register_index_______________________;\n int _off__metile_v19_r24 = v2 + _metile_register_index________________________;\n int _off__metile_v19_r25 = v2 + _metile_register_index_________________________;\n int _off__metile_v19_r26 = v2 + _metile_register_index__________________________;\n int _off__metile_v19_r27 = v2 + _metile_register_index___________________________;\n int _off__metile_v19_r28 = v2 + _metile_register_index____________________________;\n int _off__metile_v19_r29 = v2 + _metile_register_index_____________________________;\n int _off__metile_v19_r30 = v2 + _metile_register_index______________________________;\n int _off__metile_v19_r31 = v2 + _metile_register_index_______________________________;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n half _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n half _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n half _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n half _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n half _metile_v20_r8 = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n half _metile_v20_r9 = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n half _metile_v20_r10 = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n half _metile_v20_r11 = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n half _metile_v20_r12 = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n half _metile_v20_r13 = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n half _metile_v20_r14 = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n half _metile_v20_r15 = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n half _metile_v20_r16 = _metile_v18_r16 ? X[_off__metile_v19_r16] : static_cast(0);\n half _metile_v20_r17 = _metile_v18_r17 ? X[_off__metile_v19_r17] : static_cast(0);\n half _metile_v20_r18 = _metile_v18_r18 ? X[_off__metile_v19_r18] : static_cast(0);\n half _metile_v20_r19 = _metile_v18_r19 ? X[_off__metile_v19_r19] : static_cast(0);\n half _metile_v20_r20 = _metile_v18_r20 ? X[_off__metile_v19_r20] : static_cast(0);\n half _metile_v20_r21 = _metile_v18_r21 ? X[_off__metile_v19_r21] : static_cast(0);\n half _metile_v20_r22 = _metile_v18_r22 ? X[_off__metile_v19_r22] : static_cast(0);\n half _metile_v20_r23 = _metile_v18_r23 ? X[_off__metile_v19_r23] : static_cast(0);\n half _metile_v20_r24 = _metile_v18_r24 ? X[_off__metile_v19_r24] : static_cast(0);\n half _metile_v20_r25 = _metile_v18_r25 ? X[_off__metile_v19_r25] : static_cast(0);\n half _metile_v20_r26 = _metile_v18_r26 ? X[_off__metile_v19_r26] : static_cast(0);\n half _metile_v20_r27 = _metile_v18_r27 ? X[_off__metile_v19_r27] : static_cast(0);\n half _metile_v20_r28 = _metile_v18_r28 ? X[_off__metile_v19_r28] : static_cast(0);\n half _metile_v20_r29 = _metile_v18_r29 ? X[_off__metile_v19_r29] : static_cast(0);\n half _metile_v20_r30 = _metile_v18_r30 ? X[_off__metile_v19_r30] : static_cast(0);\n half _metile_v20_r31 = _metile_v18_r31 ? X[_off__metile_v19_r31] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v21_r16 = static_cast(_metile_v20_r16);\n float _metile_v21_r17 = static_cast(_metile_v20_r17);\n float _metile_v21_r18 = static_cast(_metile_v20_r18);\n float _metile_v21_r19 = static_cast(_metile_v20_r19);\n float _metile_v21_r20 = static_cast(_metile_v20_r20);\n float _metile_v21_r21 = static_cast(_metile_v20_r21);\n float _metile_v21_r22 = static_cast(_metile_v20_r22);\n float _metile_v21_r23 = static_cast(_metile_v20_r23);\n float _metile_v21_r24 = static_cast(_metile_v20_r24);\n float _metile_v21_r25 = static_cast(_metile_v20_r25);\n float _metile_v21_r26 = static_cast(_metile_v20_r26);\n float _metile_v21_r27 = static_cast(_metile_v20_r27);\n float _metile_v21_r28 = static_cast(_metile_v20_r28);\n float _metile_v21_r29 = static_cast(_metile_v20_r29);\n float _metile_v21_r30 = static_cast(_metile_v20_r30);\n float _metile_v21_r31 = static_cast(_metile_v20_r31);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_v22_r16 = _metile_v21_r16 * _metile_v21_r16;\n float _metile_v22_r17 = _metile_v21_r17 * _metile_v21_r17;\n float _metile_v22_r18 = _metile_v21_r18 * _metile_v21_r18;\n float _metile_v22_r19 = _metile_v21_r19 * _metile_v21_r19;\n float _metile_v22_r20 = _metile_v21_r20 * _metile_v21_r20;\n float _metile_v22_r21 = _metile_v21_r21 * _metile_v21_r21;\n float _metile_v22_r22 = _metile_v21_r22 * _metile_v21_r22;\n float _metile_v22_r23 = _metile_v21_r23 * _metile_v21_r23;\n float _metile_v22_r24 = _metile_v21_r24 * _metile_v21_r24;\n float _metile_v22_r25 = _metile_v21_r25 * _metile_v21_r25;\n float _metile_v22_r26 = _metile_v21_r26 * _metile_v21_r26;\n float _metile_v22_r27 = _metile_v21_r27 * _metile_v21_r27;\n float _metile_v22_r28 = _metile_v21_r28 * _metile_v21_r28;\n float _metile_v22_r29 = _metile_v21_r29 * _metile_v21_r29;\n float _metile_v22_r30 = _metile_v21_r30 * _metile_v21_r30;\n float _metile_v22_r31 = _metile_v21_r31 * _metile_v21_r31;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_v22_r16 + _metile_v22_r17;\n float _metile_register_sum_________ = _metile_v22_r18 + _metile_v22_r19;\n float _metile_register_sum__________ = _metile_v22_r20 + _metile_v22_r21;\n float _metile_register_sum___________ = _metile_v22_r22 + _metile_v22_r23;\n float _metile_register_sum____________ = _metile_v22_r24 + _metile_v22_r25;\n float _metile_register_sum_____________ = _metile_v22_r26 + _metile_v22_r27;\n float _metile_register_sum______________ = _metile_v22_r28 + _metile_v22_r29;\n float _metile_register_sum_______________ = _metile_v22_r30 + _metile_v22_r31;\n float _metile_register_sum________________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________________ = _metile_register_sum____________ + _metile_register_sum_____________;\n float _metile_register_sum_______________________ = _metile_register_sum______________ + _metile_register_sum_______________;\n float _metile_register_sum________________________ = _metile_register_sum________________ + _metile_register_sum_________________;\n float _metile_register_sum_________________________ = _metile_register_sum__________________ + _metile_register_sum___________________;\n float _metile_register_sum__________________________ = _metile_register_sum____________________ + _metile_register_sum_____________________;\n float _metile_register_sum___________________________ = _metile_register_sum______________________ + _metile_register_sum_______________________;\n float _metile_register_sum____________________________ = _metile_register_sum________________________ + _metile_register_sum_________________________;\n float _metile_register_sum_____________________________ = _metile_register_sum__________________________ + _metile_register_sum___________________________;\n float _metile_register_sum______________________________ = _metile_register_sum____________________________ + _metile_register_sum_____________________________;\n float v23 = simd_sum(_metile_register_sum______________________________);\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v32_r16 = _metile_register_index________________ >= 0;\n bool _metile_v32_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v32_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v32_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v32_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v32_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v32_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v32_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v32_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v32_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v32_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v32_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v32_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v32_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v32_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v32_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v33_r8 = _metile_register_index________ < 1009;\n bool _metile_v33_r9 = _metile_register_index_________ < 1009;\n bool _metile_v33_r10 = _metile_register_index__________ < 1009;\n bool _metile_v33_r11 = _metile_register_index___________ < 1009;\n bool _metile_v33_r12 = _metile_register_index____________ < 1009;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v33_r14 = _metile_register_index______________ < 1009;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v33_r16 = _metile_register_index________________ < 1009;\n bool _metile_v33_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v33_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v33_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v33_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v33_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v33_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v33_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v33_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v33_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v33_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v33_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v33_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v33_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v33_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v33_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n bool _metile_v34_r16 = _metile_v32_r16 & _metile_v33_r16;\n bool _metile_v34_r17 = _metile_v32_r17 & _metile_v33_r17;\n bool _metile_v34_r18 = _metile_v32_r18 & _metile_v33_r18;\n bool _metile_v34_r19 = _metile_v32_r19 & _metile_v33_r19;\n bool _metile_v34_r20 = _metile_v32_r20 & _metile_v33_r20;\n bool _metile_v34_r21 = _metile_v32_r21 & _metile_v33_r21;\n bool _metile_v34_r22 = _metile_v32_r22 & _metile_v33_r22;\n bool _metile_v34_r23 = _metile_v32_r23 & _metile_v33_r23;\n bool _metile_v34_r24 = _metile_v32_r24 & _metile_v33_r24;\n bool _metile_v34_r25 = _metile_v32_r25 & _metile_v33_r25;\n bool _metile_v34_r26 = _metile_v32_r26 & _metile_v33_r26;\n bool _metile_v34_r27 = _metile_v32_r27 & _metile_v33_r27;\n bool _metile_v34_r28 = _metile_v32_r28 & _metile_v33_r28;\n bool _metile_v34_r29 = _metile_v32_r29 & _metile_v33_r29;\n bool _metile_v34_r30 = _metile_v32_r30 & _metile_v33_r30;\n bool _metile_v34_r31 = _metile_v32_r31 & _metile_v33_r31;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n half _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n half _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n half _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n half _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n half _metile_v36_r8 = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n half _metile_v36_r9 = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n half _metile_v36_r10 = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n half _metile_v36_r11 = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n half _metile_v36_r12 = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n half _metile_v36_r13 = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n half _metile_v36_r14 = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n half _metile_v36_r15 = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n half _metile_v36_r16 = _metile_v34_r16 ? W[_metile_register_index________________] : static_cast(0);\n half _metile_v36_r17 = _metile_v34_r17 ? W[_metile_register_index_________________] : static_cast(0);\n half _metile_v36_r18 = _metile_v34_r18 ? W[_metile_register_index__________________] : static_cast(0);\n half _metile_v36_r19 = _metile_v34_r19 ? W[_metile_register_index___________________] : static_cast(0);\n half _metile_v36_r20 = _metile_v34_r20 ? W[_metile_register_index____________________] : static_cast(0);\n half _metile_v36_r21 = _metile_v34_r21 ? W[_metile_register_index_____________________] : static_cast(0);\n half _metile_v36_r22 = _metile_v34_r22 ? W[_metile_register_index______________________] : static_cast(0);\n half _metile_v36_r23 = _metile_v34_r23 ? W[_metile_register_index_______________________] : static_cast(0);\n half _metile_v36_r24 = _metile_v34_r24 ? W[_metile_register_index________________________] : static_cast(0);\n half _metile_v36_r25 = _metile_v34_r25 ? W[_metile_register_index_________________________] : static_cast(0);\n half _metile_v36_r26 = _metile_v34_r26 ? W[_metile_register_index__________________________] : static_cast(0);\n half _metile_v36_r27 = _metile_v34_r27 ? W[_metile_register_index___________________________] : static_cast(0);\n half _metile_v36_r28 = _metile_v34_r28 ? W[_metile_register_index____________________________] : static_cast(0);\n half _metile_v36_r29 = _metile_v34_r29 ? W[_metile_register_index_____________________________] : static_cast(0);\n half _metile_v36_r30 = _metile_v34_r30 ? W[_metile_register_index______________________________] : static_cast(0);\n half _metile_v36_r31 = _metile_v34_r31 ? W[_metile_register_index_______________________________] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v37_r16 = static_cast(_metile_v36_r16);\n float _metile_v37_r17 = static_cast(_metile_v36_r17);\n float _metile_v37_r18 = static_cast(_metile_v36_r18);\n float _metile_v37_r19 = static_cast(_metile_v36_r19);\n float _metile_v37_r20 = static_cast(_metile_v36_r20);\n float _metile_v37_r21 = static_cast(_metile_v36_r21);\n float _metile_v37_r22 = static_cast(_metile_v36_r22);\n float _metile_v37_r23 = static_cast(_metile_v36_r23);\n float _metile_v37_r24 = static_cast(_metile_v36_r24);\n float _metile_v37_r25 = static_cast(_metile_v36_r25);\n float _metile_v37_r26 = static_cast(_metile_v36_r26);\n float _metile_v37_r27 = static_cast(_metile_v36_r27);\n float _metile_v37_r28 = static_cast(_metile_v36_r28);\n float _metile_v37_r29 = static_cast(_metile_v36_r29);\n float _metile_v37_r30 = static_cast(_metile_v36_r30);\n float _metile_v37_r31 = static_cast(_metile_v36_r31);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v38_r16 = _metile_v21_r16 * v29;\n float _metile_v38_r17 = _metile_v21_r17 * v29;\n float _metile_v38_r18 = _metile_v21_r18 * v29;\n float _metile_v38_r19 = _metile_v21_r19 * v29;\n float _metile_v38_r20 = _metile_v21_r20 * v29;\n float _metile_v38_r21 = _metile_v21_r21 * v29;\n float _metile_v38_r22 = _metile_v21_r22 * v29;\n float _metile_v38_r23 = _metile_v21_r23 * v29;\n float _metile_v38_r24 = _metile_v21_r24 * v29;\n float _metile_v38_r25 = _metile_v21_r25 * v29;\n float _metile_v38_r26 = _metile_v21_r26 * v29;\n float _metile_v38_r27 = _metile_v21_r27 * v29;\n float _metile_v38_r28 = _metile_v21_r28 * v29;\n float _metile_v38_r29 = _metile_v21_r29 * v29;\n float _metile_v38_r30 = _metile_v21_r30 * v29;\n float _metile_v38_r31 = _metile_v21_r31 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n float _metile_v39_r16 = _metile_v38_r16 * _metile_v37_r16;\n float _metile_v39_r17 = _metile_v38_r17 * _metile_v37_r17;\n float _metile_v39_r18 = _metile_v38_r18 * _metile_v37_r18;\n float _metile_v39_r19 = _metile_v38_r19 * _metile_v37_r19;\n float _metile_v39_r20 = _metile_v38_r20 * _metile_v37_r20;\n float _metile_v39_r21 = _metile_v38_r21 * _metile_v37_r21;\n float _metile_v39_r22 = _metile_v38_r22 * _metile_v37_r22;\n float _metile_v39_r23 = _metile_v38_r23 * _metile_v37_r23;\n float _metile_v39_r24 = _metile_v38_r24 * _metile_v37_r24;\n float _metile_v39_r25 = _metile_v38_r25 * _metile_v37_r25;\n float _metile_v39_r26 = _metile_v38_r26 * _metile_v37_r26;\n float _metile_v39_r27 = _metile_v38_r27 * _metile_v37_r27;\n float _metile_v39_r28 = _metile_v38_r28 * _metile_v37_r28;\n float _metile_v39_r29 = _metile_v38_r29 * _metile_v37_r29;\n float _metile_v39_r30 = _metile_v38_r30 * _metile_v37_r30;\n float _metile_v39_r31 = _metile_v38_r31 * _metile_v37_r31;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v41_r16 = _metile_register_index________________ >= 0;\n bool _metile_v41_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v41_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v41_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v41_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v41_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v41_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v41_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v41_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v41_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v41_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v41_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v41_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v41_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v41_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v41_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v42_r8 = _metile_register_index________ < 1009;\n bool _metile_v42_r9 = _metile_register_index_________ < 1009;\n bool _metile_v42_r10 = _metile_register_index__________ < 1009;\n bool _metile_v42_r11 = _metile_register_index___________ < 1009;\n bool _metile_v42_r12 = _metile_register_index____________ < 1009;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v42_r14 = _metile_register_index______________ < 1009;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v42_r16 = _metile_register_index________________ < 1009;\n bool _metile_v42_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v42_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v42_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v42_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v42_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v42_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v42_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v42_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v42_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v42_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v42_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v42_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v42_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v42_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v42_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n bool _metile_v43_r16 = _metile_v41_r16 & _metile_v42_r16;\n bool _metile_v43_r17 = _metile_v41_r17 & _metile_v42_r17;\n bool _metile_v43_r18 = _metile_v41_r18 & _metile_v42_r18;\n bool _metile_v43_r19 = _metile_v41_r19 & _metile_v42_r19;\n bool _metile_v43_r20 = _metile_v41_r20 & _metile_v42_r20;\n bool _metile_v43_r21 = _metile_v41_r21 & _metile_v42_r21;\n bool _metile_v43_r22 = _metile_v41_r22 & _metile_v42_r22;\n bool _metile_v43_r23 = _metile_v41_r23 & _metile_v42_r23;\n bool _metile_v43_r24 = _metile_v41_r24 & _metile_v42_r24;\n bool _metile_v43_r25 = _metile_v41_r25 & _metile_v42_r25;\n bool _metile_v43_r26 = _metile_v41_r26 & _metile_v42_r26;\n bool _metile_v43_r27 = _metile_v41_r27 & _metile_v42_r27;\n bool _metile_v43_r28 = _metile_v41_r28 & _metile_v42_r28;\n bool _metile_v43_r29 = _metile_v41_r29 & _metile_v42_r29;\n bool _metile_v43_r30 = _metile_v41_r30 & _metile_v42_r30;\n bool _metile_v43_r31 = _metile_v41_r31 & _metile_v42_r31;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n int _off__metile_v44_r16 = v9 + _metile_register_index________________;\n int _off__metile_v44_r17 = v9 + _metile_register_index_________________;\n int _off__metile_v44_r18 = v9 + _metile_register_index__________________;\n int _off__metile_v44_r19 = v9 + _metile_register_index___________________;\n int _off__metile_v44_r20 = v9 + _metile_register_index____________________;\n int _off__metile_v44_r21 = v9 + _metile_register_index_____________________;\n int _off__metile_v44_r22 = v9 + _metile_register_index______________________;\n int _off__metile_v44_r23 = v9 + _metile_register_index_______________________;\n int _off__metile_v44_r24 = v9 + _metile_register_index________________________;\n int _off__metile_v44_r25 = v9 + _metile_register_index_________________________;\n int _off__metile_v44_r26 = v9 + _metile_register_index__________________________;\n int _off__metile_v44_r27 = v9 + _metile_register_index___________________________;\n int _off__metile_v44_r28 = v9 + _metile_register_index____________________________;\n int _off__metile_v44_r29 = v9 + _metile_register_index_____________________________;\n int _off__metile_v44_r30 = v9 + _metile_register_index______________________________;\n int _off__metile_v44_r31 = v9 + _metile_register_index_______________________________;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = _metile_v39_r8; }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = _metile_v39_r9; }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = _metile_v39_r10; }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = _metile_v39_r11; }\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = _metile_v39_r12; }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = _metile_v39_r13; }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = _metile_v39_r14; }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = _metile_v39_r15; }\n if (_metile_v43_r16) { Out[_off__metile_v44_r16] = _metile_v39_r16; }\n if (_metile_v43_r17) { Out[_off__metile_v44_r17] = _metile_v39_r17; }\n if (_metile_v43_r18) { Out[_off__metile_v44_r18] = _metile_v39_r18; }\n if (_metile_v43_r19) { Out[_off__metile_v44_r19] = _metile_v39_r19; }\n if (_metile_v43_r20) { Out[_off__metile_v44_r20] = _metile_v39_r20; }\n if (_metile_v43_r21) { Out[_off__metile_v44_r21] = _metile_v39_r21; }\n if (_metile_v43_r22) { Out[_off__metile_v44_r22] = _metile_v39_r22; }\n if (_metile_v43_r23) { Out[_off__metile_v44_r23] = _metile_v39_r23; }\n if (_metile_v43_r24) { Out[_off__metile_v44_r24] = _metile_v39_r24; }\n if (_metile_v43_r25) { Out[_off__metile_v44_r25] = _metile_v39_r25; }\n if (_metile_v43_r26) { Out[_off__metile_v44_r26] = _metile_v39_r26; }\n if (_metile_v43_r27) { Out[_off__metile_v44_r27] = _metile_v39_r27; }\n if (_metile_v43_r28) { Out[_off__metile_v44_r28] = _metile_v39_r28; }\n if (_metile_v43_r29) { Out[_off__metile_v44_r29] = _metile_v39_r29; }\n if (_metile_v43_r30) { Out[_off__metile_v44_r30] = _metile_v39_r30; }\n if (_metile_v43_r31) { Out[_off__metile_v44_r31] = _metile_v39_r31; }\n}", "source_sha256": "d5c41916120b99fb67bf8cd3981daa7226ce2516e5cb14fd030515e31ba811e0", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 32, 1, 1 ], "is_gemm": false, "prefer_ordered": false, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 32, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 32 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 32, "threads": 32, "scratch": null, "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 597, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.917, "control": 199.375, "speedup": 0.9972888748830765 }, "gpu_us": { "candidate": 2.500019036233425, "control": 2.00001522898674, "speedup": 0.8 } } }, { "frozen_register4": { "pairs": 551, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 206.208, "control": 204.333, "speedup": 0.990907239292365 }, "gpu_us": { "candidate": 2.500019036233425, "control": 2.0416919142007828, "speedup": 0.8166705471478464 } } }, { "frozen_register4": { "pairs": 578, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 205.75, "control": 205.04149999999998, "speedup": 0.9965565006075333 }, "gpu_us": { "candidate": 2.500019036233425, "control": 2.0416337065398693, "speedup": 0.8166472642607684 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9949134469060452, "round_speedups": [ 0.9972888748830765, 0.990907239292365, 0.9965565006075333 ], "candidate": 203.93809583981076, "control": 202.90075388744145 }, "gpu_us": { "speedup": 0.8110677452081524, "round_speedups": [ 0.8, 0.8166705471478464, 0.8166472642607684 ], "candidate": 2.500019036233425, "control": 2.0276848026953025 } } } }, { "name": "float16_32x1009", "dtype": "float16", "batches": 32, "width": 1009, "status": "measured", "variant": { "name": "register32_blocked4", "elements_per_thread": 32, "layout": "blocked4" }, "input_sha256": "e6d696cff86bdf9ec8254c3438c13725f24b2b1f6073b44660a256dcea0488a8", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 31;\n int _metile_register_index = int((((_metile_bounded_thread >> 5) & 1u) << 0) | (((_metile_bounded_thread >> 6) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 7) & 1u) << 7) | (((_metile_bounded_thread >> 8) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 32;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 5) & 1u) << 0) | (((_metile_register_packed_ >> 6) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 7) & 1u) << 7) | (((_metile_register_packed_ >> 8) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 64;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 5) & 1u) << 0) | (((_metile_register_packed__ >> 6) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 7) & 1u) << 7) | (((_metile_register_packed__ >> 8) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 96;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 5) & 1u) << 0) | (((_metile_register_packed___ >> 6) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 7) & 1u) << 7) | (((_metile_register_packed___ >> 8) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 128;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 5) & 1u) << 0) | (((_metile_register_packed____ >> 6) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 7) & 1u) << 7) | (((_metile_register_packed____ >> 8) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 160;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 5) & 1u) << 0) | (((_metile_register_packed_____ >> 6) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 7) & 1u) << 7) | (((_metile_register_packed_____ >> 8) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 192;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 5) & 1u) << 0) | (((_metile_register_packed______ >> 6) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 7) & 1u) << 7) | (((_metile_register_packed______ >> 8) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 224;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 5) & 1u) << 0) | (((_metile_register_packed_______ >> 6) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 7) & 1u) << 7) | (((_metile_register_packed_______ >> 8) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n int _metile_register_packed________ = _metile_bounded_thread + 256;\n int _metile_register_index________ = int((((_metile_register_packed________ >> 5) & 1u) << 0) | (((_metile_register_packed________ >> 6) & 1u) << 1) | (((_metile_register_packed________ >> 0) & 1u) << 2) | (((_metile_register_packed________ >> 1) & 1u) << 3) | (((_metile_register_packed________ >> 2) & 1u) << 4) | (((_metile_register_packed________ >> 3) & 1u) << 5) | (((_metile_register_packed________ >> 4) & 1u) << 6) | (((_metile_register_packed________ >> 7) & 1u) << 7) | (((_metile_register_packed________ >> 8) & 1u) << 8) | (((_metile_register_packed________ >> 9) & 1u) << 9));\n int _metile_register_packed_________ = _metile_bounded_thread + 288;\n int _metile_register_index_________ = int((((_metile_register_packed_________ >> 5) & 1u) << 0) | (((_metile_register_packed_________ >> 6) & 1u) << 1) | (((_metile_register_packed_________ >> 0) & 1u) << 2) | (((_metile_register_packed_________ >> 1) & 1u) << 3) | (((_metile_register_packed_________ >> 2) & 1u) << 4) | (((_metile_register_packed_________ >> 3) & 1u) << 5) | (((_metile_register_packed_________ >> 4) & 1u) << 6) | (((_metile_register_packed_________ >> 7) & 1u) << 7) | (((_metile_register_packed_________ >> 8) & 1u) << 8) | (((_metile_register_packed_________ >> 9) & 1u) << 9));\n int _metile_register_packed__________ = _metile_bounded_thread + 320;\n int _metile_register_index__________ = int((((_metile_register_packed__________ >> 5) & 1u) << 0) | (((_metile_register_packed__________ >> 6) & 1u) << 1) | (((_metile_register_packed__________ >> 0) & 1u) << 2) | (((_metile_register_packed__________ >> 1) & 1u) << 3) | (((_metile_register_packed__________ >> 2) & 1u) << 4) | (((_metile_register_packed__________ >> 3) & 1u) << 5) | (((_metile_register_packed__________ >> 4) & 1u) << 6) | (((_metile_register_packed__________ >> 7) & 1u) << 7) | (((_metile_register_packed__________ >> 8) & 1u) << 8) | (((_metile_register_packed__________ >> 9) & 1u) << 9));\n int _metile_register_packed___________ = _metile_bounded_thread + 352;\n int _metile_register_index___________ = int((((_metile_register_packed___________ >> 5) & 1u) << 0) | (((_metile_register_packed___________ >> 6) & 1u) << 1) | (((_metile_register_packed___________ >> 0) & 1u) << 2) | (((_metile_register_packed___________ >> 1) & 1u) << 3) | (((_metile_register_packed___________ >> 2) & 1u) << 4) | (((_metile_register_packed___________ >> 3) & 1u) << 5) | (((_metile_register_packed___________ >> 4) & 1u) << 6) | (((_metile_register_packed___________ >> 7) & 1u) << 7) | (((_metile_register_packed___________ >> 8) & 1u) << 8) | (((_metile_register_packed___________ >> 9) & 1u) << 9));\n int _metile_register_packed____________ = _metile_bounded_thread + 384;\n int _metile_register_index____________ = int((((_metile_register_packed____________ >> 5) & 1u) << 0) | (((_metile_register_packed____________ >> 6) & 1u) << 1) | (((_metile_register_packed____________ >> 0) & 1u) << 2) | (((_metile_register_packed____________ >> 1) & 1u) << 3) | (((_metile_register_packed____________ >> 2) & 1u) << 4) | (((_metile_register_packed____________ >> 3) & 1u) << 5) | (((_metile_register_packed____________ >> 4) & 1u) << 6) | (((_metile_register_packed____________ >> 7) & 1u) << 7) | (((_metile_register_packed____________ >> 8) & 1u) << 8) | (((_metile_register_packed____________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________ = _metile_bounded_thread + 416;\n int _metile_register_index_____________ = int((((_metile_register_packed_____________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________ >> 9) & 1u) << 9));\n int _metile_register_packed______________ = _metile_bounded_thread + 448;\n int _metile_register_index______________ = int((((_metile_register_packed______________ >> 5) & 1u) << 0) | (((_metile_register_packed______________ >> 6) & 1u) << 1) | (((_metile_register_packed______________ >> 0) & 1u) << 2) | (((_metile_register_packed______________ >> 1) & 1u) << 3) | (((_metile_register_packed______________ >> 2) & 1u) << 4) | (((_metile_register_packed______________ >> 3) & 1u) << 5) | (((_metile_register_packed______________ >> 4) & 1u) << 6) | (((_metile_register_packed______________ >> 7) & 1u) << 7) | (((_metile_register_packed______________ >> 8) & 1u) << 8) | (((_metile_register_packed______________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________ = _metile_bounded_thread + 480;\n int _metile_register_index_______________ = int((((_metile_register_packed_______________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________ >> 9) & 1u) << 9));\n int _metile_register_packed________________ = _metile_bounded_thread + 512;\n int _metile_register_index________________ = int((((_metile_register_packed________________ >> 5) & 1u) << 0) | (((_metile_register_packed________________ >> 6) & 1u) << 1) | (((_metile_register_packed________________ >> 0) & 1u) << 2) | (((_metile_register_packed________________ >> 1) & 1u) << 3) | (((_metile_register_packed________________ >> 2) & 1u) << 4) | (((_metile_register_packed________________ >> 3) & 1u) << 5) | (((_metile_register_packed________________ >> 4) & 1u) << 6) | (((_metile_register_packed________________ >> 7) & 1u) << 7) | (((_metile_register_packed________________ >> 8) & 1u) << 8) | (((_metile_register_packed________________ >> 9) & 1u) << 9));\n int _metile_register_packed_________________ = _metile_bounded_thread + 544;\n int _metile_register_index_________________ = int((((_metile_register_packed_________________ >> 5) & 1u) << 0) | (((_metile_register_packed_________________ >> 6) & 1u) << 1) | (((_metile_register_packed_________________ >> 0) & 1u) << 2) | (((_metile_register_packed_________________ >> 1) & 1u) << 3) | (((_metile_register_packed_________________ >> 2) & 1u) << 4) | (((_metile_register_packed_________________ >> 3) & 1u) << 5) | (((_metile_register_packed_________________ >> 4) & 1u) << 6) | (((_metile_register_packed_________________ >> 7) & 1u) << 7) | (((_metile_register_packed_________________ >> 8) & 1u) << 8) | (((_metile_register_packed_________________ >> 9) & 1u) << 9));\n int _metile_register_packed__________________ = _metile_bounded_thread + 576;\n int _metile_register_index__________________ = int((((_metile_register_packed__________________ >> 5) & 1u) << 0) | (((_metile_register_packed__________________ >> 6) & 1u) << 1) | (((_metile_register_packed__________________ >> 0) & 1u) << 2) | (((_metile_register_packed__________________ >> 1) & 1u) << 3) | (((_metile_register_packed__________________ >> 2) & 1u) << 4) | (((_metile_register_packed__________________ >> 3) & 1u) << 5) | (((_metile_register_packed__________________ >> 4) & 1u) << 6) | (((_metile_register_packed__________________ >> 7) & 1u) << 7) | (((_metile_register_packed__________________ >> 8) & 1u) << 8) | (((_metile_register_packed__________________ >> 9) & 1u) << 9));\n int _metile_register_packed___________________ = _metile_bounded_thread + 608;\n int _metile_register_index___________________ = int((((_metile_register_packed___________________ >> 5) & 1u) << 0) | (((_metile_register_packed___________________ >> 6) & 1u) << 1) | (((_metile_register_packed___________________ >> 0) & 1u) << 2) | (((_metile_register_packed___________________ >> 1) & 1u) << 3) | (((_metile_register_packed___________________ >> 2) & 1u) << 4) | (((_metile_register_packed___________________ >> 3) & 1u) << 5) | (((_metile_register_packed___________________ >> 4) & 1u) << 6) | (((_metile_register_packed___________________ >> 7) & 1u) << 7) | (((_metile_register_packed___________________ >> 8) & 1u) << 8) | (((_metile_register_packed___________________ >> 9) & 1u) << 9));\n int _metile_register_packed____________________ = _metile_bounded_thread + 640;\n int _metile_register_index____________________ = int((((_metile_register_packed____________________ >> 5) & 1u) << 0) | (((_metile_register_packed____________________ >> 6) & 1u) << 1) | (((_metile_register_packed____________________ >> 0) & 1u) << 2) | (((_metile_register_packed____________________ >> 1) & 1u) << 3) | (((_metile_register_packed____________________ >> 2) & 1u) << 4) | (((_metile_register_packed____________________ >> 3) & 1u) << 5) | (((_metile_register_packed____________________ >> 4) & 1u) << 6) | (((_metile_register_packed____________________ >> 7) & 1u) << 7) | (((_metile_register_packed____________________ >> 8) & 1u) << 8) | (((_metile_register_packed____________________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________________ = _metile_bounded_thread + 672;\n int _metile_register_index_____________________ = int((((_metile_register_packed_____________________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________________ >> 9) & 1u) << 9));\n int _metile_register_packed______________________ = _metile_bounded_thread + 704;\n int _metile_register_index______________________ = int((((_metile_register_packed______________________ >> 5) & 1u) << 0) | (((_metile_register_packed______________________ >> 6) & 1u) << 1) | (((_metile_register_packed______________________ >> 0) & 1u) << 2) | (((_metile_register_packed______________________ >> 1) & 1u) << 3) | (((_metile_register_packed______________________ >> 2) & 1u) << 4) | (((_metile_register_packed______________________ >> 3) & 1u) << 5) | (((_metile_register_packed______________________ >> 4) & 1u) << 6) | (((_metile_register_packed______________________ >> 7) & 1u) << 7) | (((_metile_register_packed______________________ >> 8) & 1u) << 8) | (((_metile_register_packed______________________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________________ = _metile_bounded_thread + 736;\n int _metile_register_index_______________________ = int((((_metile_register_packed_______________________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________________ >> 9) & 1u) << 9));\n int _metile_register_packed________________________ = _metile_bounded_thread + 768;\n int _metile_register_index________________________ = int((((_metile_register_packed________________________ >> 5) & 1u) << 0) | (((_metile_register_packed________________________ >> 6) & 1u) << 1) | (((_metile_register_packed________________________ >> 0) & 1u) << 2) | (((_metile_register_packed________________________ >> 1) & 1u) << 3) | (((_metile_register_packed________________________ >> 2) & 1u) << 4) | (((_metile_register_packed________________________ >> 3) & 1u) << 5) | (((_metile_register_packed________________________ >> 4) & 1u) << 6) | (((_metile_register_packed________________________ >> 7) & 1u) << 7) | (((_metile_register_packed________________________ >> 8) & 1u) << 8) | (((_metile_register_packed________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_________________________ = _metile_bounded_thread + 800;\n int _metile_register_index_________________________ = int((((_metile_register_packed_________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_________________________ >> 9) & 1u) << 9));\n int _metile_register_packed__________________________ = _metile_bounded_thread + 832;\n int _metile_register_index__________________________ = int((((_metile_register_packed__________________________ >> 5) & 1u) << 0) | (((_metile_register_packed__________________________ >> 6) & 1u) << 1) | (((_metile_register_packed__________________________ >> 0) & 1u) << 2) | (((_metile_register_packed__________________________ >> 1) & 1u) << 3) | (((_metile_register_packed__________________________ >> 2) & 1u) << 4) | (((_metile_register_packed__________________________ >> 3) & 1u) << 5) | (((_metile_register_packed__________________________ >> 4) & 1u) << 6) | (((_metile_register_packed__________________________ >> 7) & 1u) << 7) | (((_metile_register_packed__________________________ >> 8) & 1u) << 8) | (((_metile_register_packed__________________________ >> 9) & 1u) << 9));\n int _metile_register_packed___________________________ = _metile_bounded_thread + 864;\n int _metile_register_index___________________________ = int((((_metile_register_packed___________________________ >> 5) & 1u) << 0) | (((_metile_register_packed___________________________ >> 6) & 1u) << 1) | (((_metile_register_packed___________________________ >> 0) & 1u) << 2) | (((_metile_register_packed___________________________ >> 1) & 1u) << 3) | (((_metile_register_packed___________________________ >> 2) & 1u) << 4) | (((_metile_register_packed___________________________ >> 3) & 1u) << 5) | (((_metile_register_packed___________________________ >> 4) & 1u) << 6) | (((_metile_register_packed___________________________ >> 7) & 1u) << 7) | (((_metile_register_packed___________________________ >> 8) & 1u) << 8) | (((_metile_register_packed___________________________ >> 9) & 1u) << 9));\n int _metile_register_packed____________________________ = _metile_bounded_thread + 896;\n int _metile_register_index____________________________ = int((((_metile_register_packed____________________________ >> 5) & 1u) << 0) | (((_metile_register_packed____________________________ >> 6) & 1u) << 1) | (((_metile_register_packed____________________________ >> 0) & 1u) << 2) | (((_metile_register_packed____________________________ >> 1) & 1u) << 3) | (((_metile_register_packed____________________________ >> 2) & 1u) << 4) | (((_metile_register_packed____________________________ >> 3) & 1u) << 5) | (((_metile_register_packed____________________________ >> 4) & 1u) << 6) | (((_metile_register_packed____________________________ >> 7) & 1u) << 7) | (((_metile_register_packed____________________________ >> 8) & 1u) << 8) | (((_metile_register_packed____________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________________________ = _metile_bounded_thread + 928;\n int _metile_register_index_____________________________ = int((((_metile_register_packed_____________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________________________ >> 9) & 1u) << 9));\n int _metile_register_packed______________________________ = _metile_bounded_thread + 960;\n int _metile_register_index______________________________ = int((((_metile_register_packed______________________________ >> 5) & 1u) << 0) | (((_metile_register_packed______________________________ >> 6) & 1u) << 1) | (((_metile_register_packed______________________________ >> 0) & 1u) << 2) | (((_metile_register_packed______________________________ >> 1) & 1u) << 3) | (((_metile_register_packed______________________________ >> 2) & 1u) << 4) | (((_metile_register_packed______________________________ >> 3) & 1u) << 5) | (((_metile_register_packed______________________________ >> 4) & 1u) << 6) | (((_metile_register_packed______________________________ >> 7) & 1u) << 7) | (((_metile_register_packed______________________________ >> 8) & 1u) << 8) | (((_metile_register_packed______________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________________________ = _metile_bounded_thread + 992;\n int _metile_register_index_______________________________ = int((((_metile_register_packed_______________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________________________ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v16_r16 = _metile_register_index________________ >= 0;\n bool _metile_v16_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v16_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v16_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v16_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v16_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v16_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v16_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v16_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v16_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v16_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v16_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v16_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v16_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v16_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v16_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v17_r8 = _metile_register_index________ < 1009;\n bool _metile_v17_r9 = _metile_register_index_________ < 1009;\n bool _metile_v17_r10 = _metile_register_index__________ < 1009;\n bool _metile_v17_r11 = _metile_register_index___________ < 1009;\n bool _metile_v17_r12 = _metile_register_index____________ < 1009;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v17_r14 = _metile_register_index______________ < 1009;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v17_r16 = _metile_register_index________________ < 1009;\n bool _metile_v17_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v17_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v17_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v17_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v17_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v17_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v17_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v17_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v17_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v17_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v17_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v17_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v17_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v17_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v17_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n bool _metile_v18_r16 = _metile_v16_r16 & _metile_v17_r16;\n bool _metile_v18_r17 = _metile_v16_r17 & _metile_v17_r17;\n bool _metile_v18_r18 = _metile_v16_r18 & _metile_v17_r18;\n bool _metile_v18_r19 = _metile_v16_r19 & _metile_v17_r19;\n bool _metile_v18_r20 = _metile_v16_r20 & _metile_v17_r20;\n bool _metile_v18_r21 = _metile_v16_r21 & _metile_v17_r21;\n bool _metile_v18_r22 = _metile_v16_r22 & _metile_v17_r22;\n bool _metile_v18_r23 = _metile_v16_r23 & _metile_v17_r23;\n bool _metile_v18_r24 = _metile_v16_r24 & _metile_v17_r24;\n bool _metile_v18_r25 = _metile_v16_r25 & _metile_v17_r25;\n bool _metile_v18_r26 = _metile_v16_r26 & _metile_v17_r26;\n bool _metile_v18_r27 = _metile_v16_r27 & _metile_v17_r27;\n bool _metile_v18_r28 = _metile_v16_r28 & _metile_v17_r28;\n bool _metile_v18_r29 = _metile_v16_r29 & _metile_v17_r29;\n bool _metile_v18_r30 = _metile_v16_r30 & _metile_v17_r30;\n bool _metile_v18_r31 = _metile_v16_r31 & _metile_v17_r31;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n int _off__metile_v19_r16 = v2 + _metile_register_index________________;\n int _off__metile_v19_r17 = v2 + _metile_register_index_________________;\n int _off__metile_v19_r18 = v2 + _metile_register_index__________________;\n int _off__metile_v19_r19 = v2 + _metile_register_index___________________;\n int _off__metile_v19_r20 = v2 + _metile_register_index____________________;\n int _off__metile_v19_r21 = v2 + _metile_register_index_____________________;\n int _off__metile_v19_r22 = v2 + _metile_register_index______________________;\n int _off__metile_v19_r23 = v2 + _metile_register_index_______________________;\n int _off__metile_v19_r24 = v2 + _metile_register_index________________________;\n int _off__metile_v19_r25 = v2 + _metile_register_index_________________________;\n int _off__metile_v19_r26 = v2 + _metile_register_index__________________________;\n int _off__metile_v19_r27 = v2 + _metile_register_index___________________________;\n int _off__metile_v19_r28 = v2 + _metile_register_index____________________________;\n int _off__metile_v19_r29 = v2 + _metile_register_index_____________________________;\n int _off__metile_v19_r30 = v2 + _metile_register_index______________________________;\n int _off__metile_v19_r31 = v2 + _metile_register_index_______________________________;\n half4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = half4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n half _metile_v20_r0 = _metile_vector_load[0];\n half _metile_v20_r1 = _metile_vector_load[1];\n half _metile_v20_r2 = _metile_vector_load[2];\n half _metile_v20_r3 = _metile_vector_load[3];\n half4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = half4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n half _metile_v20_r4 = _metile_vector_load_[0];\n half _metile_v20_r5 = _metile_vector_load_[1];\n half _metile_v20_r6 = _metile_vector_load_[2];\n half _metile_v20_r7 = _metile_vector_load_[3];\n half4 _metile_vector_load__;\n if ((_metile_v18_r8) && (_metile_v18_r9) && (_metile_v18_r10) && (_metile_v18_r11) && (long(_off__metile_v19_r9) == long(_off__metile_v19_r8) + 1) && (long(_off__metile_v19_r10) == long(_off__metile_v19_r8) + 2) && (long(_off__metile_v19_r11) == long(_off__metile_v19_r8) + 3)) {\n _metile_vector_load__ = half4(*reinterpret_cast(X + _off__metile_v19_r8));\n } else {\n _metile_vector_load__[0] = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n _metile_vector_load__[1] = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n _metile_vector_load__[2] = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n _metile_vector_load__[3] = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n }\n half _metile_v20_r8 = _metile_vector_load__[0];\n half _metile_v20_r9 = _metile_vector_load__[1];\n half _metile_v20_r10 = _metile_vector_load__[2];\n half _metile_v20_r11 = _metile_vector_load__[3];\n half4 _metile_vector_load___;\n if ((_metile_v18_r12) && (_metile_v18_r13) && (_metile_v18_r14) && (_metile_v18_r15) && (long(_off__metile_v19_r13) == long(_off__metile_v19_r12) + 1) && (long(_off__metile_v19_r14) == long(_off__metile_v19_r12) + 2) && (long(_off__metile_v19_r15) == long(_off__metile_v19_r12) + 3)) {\n _metile_vector_load___ = half4(*reinterpret_cast(X + _off__metile_v19_r12));\n } else {\n _metile_vector_load___[0] = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n _metile_vector_load___[1] = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n _metile_vector_load___[2] = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n _metile_vector_load___[3] = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n }\n half _metile_v20_r12 = _metile_vector_load___[0];\n half _metile_v20_r13 = _metile_vector_load___[1];\n half _metile_v20_r14 = _metile_vector_load___[2];\n half _metile_v20_r15 = _metile_vector_load___[3];\n half4 _metile_vector_load____;\n if ((_metile_v18_r16) && (_metile_v18_r17) && (_metile_v18_r18) && (_metile_v18_r19) && (long(_off__metile_v19_r17) == long(_off__metile_v19_r16) + 1) && (long(_off__metile_v19_r18) == long(_off__metile_v19_r16) + 2) && (long(_off__metile_v19_r19) == long(_off__metile_v19_r16) + 3)) {\n _metile_vector_load____ = half4(*reinterpret_cast(X + _off__metile_v19_r16));\n } else {\n _metile_vector_load____[0] = _metile_v18_r16 ? X[_off__metile_v19_r16] : static_cast(0);\n _metile_vector_load____[1] = _metile_v18_r17 ? X[_off__metile_v19_r17] : static_cast(0);\n _metile_vector_load____[2] = _metile_v18_r18 ? X[_off__metile_v19_r18] : static_cast(0);\n _metile_vector_load____[3] = _metile_v18_r19 ? X[_off__metile_v19_r19] : static_cast(0);\n }\n half _metile_v20_r16 = _metile_vector_load____[0];\n half _metile_v20_r17 = _metile_vector_load____[1];\n half _metile_v20_r18 = _metile_vector_load____[2];\n half _metile_v20_r19 = _metile_vector_load____[3];\n half4 _metile_vector_load_____;\n if ((_metile_v18_r20) && (_metile_v18_r21) && (_metile_v18_r22) && (_metile_v18_r23) && (long(_off__metile_v19_r21) == long(_off__metile_v19_r20) + 1) && (long(_off__metile_v19_r22) == long(_off__metile_v19_r20) + 2) && (long(_off__metile_v19_r23) == long(_off__metile_v19_r20) + 3)) {\n _metile_vector_load_____ = half4(*reinterpret_cast(X + _off__metile_v19_r20));\n } else {\n _metile_vector_load_____[0] = _metile_v18_r20 ? X[_off__metile_v19_r20] : static_cast(0);\n _metile_vector_load_____[1] = _metile_v18_r21 ? X[_off__metile_v19_r21] : static_cast(0);\n _metile_vector_load_____[2] = _metile_v18_r22 ? X[_off__metile_v19_r22] : static_cast(0);\n _metile_vector_load_____[3] = _metile_v18_r23 ? X[_off__metile_v19_r23] : static_cast(0);\n }\n half _metile_v20_r20 = _metile_vector_load_____[0];\n half _metile_v20_r21 = _metile_vector_load_____[1];\n half _metile_v20_r22 = _metile_vector_load_____[2];\n half _metile_v20_r23 = _metile_vector_load_____[3];\n half4 _metile_vector_load______;\n if ((_metile_v18_r24) && (_metile_v18_r25) && (_metile_v18_r26) && (_metile_v18_r27) && (long(_off__metile_v19_r25) == long(_off__metile_v19_r24) + 1) && (long(_off__metile_v19_r26) == long(_off__metile_v19_r24) + 2) && (long(_off__metile_v19_r27) == long(_off__metile_v19_r24) + 3)) {\n _metile_vector_load______ = half4(*reinterpret_cast(X + _off__metile_v19_r24));\n } else {\n _metile_vector_load______[0] = _metile_v18_r24 ? X[_off__metile_v19_r24] : static_cast(0);\n _metile_vector_load______[1] = _metile_v18_r25 ? X[_off__metile_v19_r25] : static_cast(0);\n _metile_vector_load______[2] = _metile_v18_r26 ? X[_off__metile_v19_r26] : static_cast(0);\n _metile_vector_load______[3] = _metile_v18_r27 ? X[_off__metile_v19_r27] : static_cast(0);\n }\n half _metile_v20_r24 = _metile_vector_load______[0];\n half _metile_v20_r25 = _metile_vector_load______[1];\n half _metile_v20_r26 = _metile_vector_load______[2];\n half _metile_v20_r27 = _metile_vector_load______[3];\n half4 _metile_vector_load_______;\n if ((_metile_v18_r28) && (_metile_v18_r29) && (_metile_v18_r30) && (_metile_v18_r31) && (long(_off__metile_v19_r29) == long(_off__metile_v19_r28) + 1) && (long(_off__metile_v19_r30) == long(_off__metile_v19_r28) + 2) && (long(_off__metile_v19_r31) == long(_off__metile_v19_r28) + 3)) {\n _metile_vector_load_______ = half4(*reinterpret_cast(X + _off__metile_v19_r28));\n } else {\n _metile_vector_load_______[0] = _metile_v18_r28 ? X[_off__metile_v19_r28] : static_cast(0);\n _metile_vector_load_______[1] = _metile_v18_r29 ? X[_off__metile_v19_r29] : static_cast(0);\n _metile_vector_load_______[2] = _metile_v18_r30 ? X[_off__metile_v19_r30] : static_cast(0);\n _metile_vector_load_______[3] = _metile_v18_r31 ? X[_off__metile_v19_r31] : static_cast(0);\n }\n half _metile_v20_r28 = _metile_vector_load_______[0];\n half _metile_v20_r29 = _metile_vector_load_______[1];\n half _metile_v20_r30 = _metile_vector_load_______[2];\n half _metile_v20_r31 = _metile_vector_load_______[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v21_r16 = static_cast(_metile_v20_r16);\n float _metile_v21_r17 = static_cast(_metile_v20_r17);\n float _metile_v21_r18 = static_cast(_metile_v20_r18);\n float _metile_v21_r19 = static_cast(_metile_v20_r19);\n float _metile_v21_r20 = static_cast(_metile_v20_r20);\n float _metile_v21_r21 = static_cast(_metile_v20_r21);\n float _metile_v21_r22 = static_cast(_metile_v20_r22);\n float _metile_v21_r23 = static_cast(_metile_v20_r23);\n float _metile_v21_r24 = static_cast(_metile_v20_r24);\n float _metile_v21_r25 = static_cast(_metile_v20_r25);\n float _metile_v21_r26 = static_cast(_metile_v20_r26);\n float _metile_v21_r27 = static_cast(_metile_v20_r27);\n float _metile_v21_r28 = static_cast(_metile_v20_r28);\n float _metile_v21_r29 = static_cast(_metile_v20_r29);\n float _metile_v21_r30 = static_cast(_metile_v20_r30);\n float _metile_v21_r31 = static_cast(_metile_v20_r31);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_v22_r16 = _metile_v21_r16 * _metile_v21_r16;\n float _metile_v22_r17 = _metile_v21_r17 * _metile_v21_r17;\n float _metile_v22_r18 = _metile_v21_r18 * _metile_v21_r18;\n float _metile_v22_r19 = _metile_v21_r19 * _metile_v21_r19;\n float _metile_v22_r20 = _metile_v21_r20 * _metile_v21_r20;\n float _metile_v22_r21 = _metile_v21_r21 * _metile_v21_r21;\n float _metile_v22_r22 = _metile_v21_r22 * _metile_v21_r22;\n float _metile_v22_r23 = _metile_v21_r23 * _metile_v21_r23;\n float _metile_v22_r24 = _metile_v21_r24 * _metile_v21_r24;\n float _metile_v22_r25 = _metile_v21_r25 * _metile_v21_r25;\n float _metile_v22_r26 = _metile_v21_r26 * _metile_v21_r26;\n float _metile_v22_r27 = _metile_v21_r27 * _metile_v21_r27;\n float _metile_v22_r28 = _metile_v21_r28 * _metile_v21_r28;\n float _metile_v22_r29 = _metile_v21_r29 * _metile_v21_r29;\n float _metile_v22_r30 = _metile_v21_r30 * _metile_v21_r30;\n float _metile_v22_r31 = _metile_v21_r31 * _metile_v21_r31;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_v22_r16 + _metile_v22_r17;\n float _metile_register_sum_________ = _metile_v22_r18 + _metile_v22_r19;\n float _metile_register_sum__________ = _metile_v22_r20 + _metile_v22_r21;\n float _metile_register_sum___________ = _metile_v22_r22 + _metile_v22_r23;\n float _metile_register_sum____________ = _metile_v22_r24 + _metile_v22_r25;\n float _metile_register_sum_____________ = _metile_v22_r26 + _metile_v22_r27;\n float _metile_register_sum______________ = _metile_v22_r28 + _metile_v22_r29;\n float _metile_register_sum_______________ = _metile_v22_r30 + _metile_v22_r31;\n float _metile_register_sum________________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________________ = _metile_register_sum____________ + _metile_register_sum_____________;\n float _metile_register_sum_______________________ = _metile_register_sum______________ + _metile_register_sum_______________;\n float _metile_register_sum________________________ = _metile_register_sum________________ + _metile_register_sum_________________;\n float _metile_register_sum_________________________ = _metile_register_sum__________________ + _metile_register_sum___________________;\n float _metile_register_sum__________________________ = _metile_register_sum____________________ + _metile_register_sum_____________________;\n float _metile_register_sum___________________________ = _metile_register_sum______________________ + _metile_register_sum_______________________;\n float _metile_register_sum____________________________ = _metile_register_sum________________________ + _metile_register_sum_________________________;\n float _metile_register_sum_____________________________ = _metile_register_sum__________________________ + _metile_register_sum___________________________;\n float _metile_register_sum______________________________ = _metile_register_sum____________________________ + _metile_register_sum_____________________________;\n float v23 = simd_sum(_metile_register_sum______________________________);\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v32_r16 = _metile_register_index________________ >= 0;\n bool _metile_v32_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v32_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v32_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v32_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v32_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v32_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v32_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v32_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v32_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v32_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v32_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v32_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v32_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v32_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v32_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v33_r8 = _metile_register_index________ < 1009;\n bool _metile_v33_r9 = _metile_register_index_________ < 1009;\n bool _metile_v33_r10 = _metile_register_index__________ < 1009;\n bool _metile_v33_r11 = _metile_register_index___________ < 1009;\n bool _metile_v33_r12 = _metile_register_index____________ < 1009;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v33_r14 = _metile_register_index______________ < 1009;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v33_r16 = _metile_register_index________________ < 1009;\n bool _metile_v33_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v33_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v33_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v33_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v33_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v33_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v33_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v33_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v33_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v33_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v33_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v33_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v33_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v33_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v33_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n bool _metile_v34_r16 = _metile_v32_r16 & _metile_v33_r16;\n bool _metile_v34_r17 = _metile_v32_r17 & _metile_v33_r17;\n bool _metile_v34_r18 = _metile_v32_r18 & _metile_v33_r18;\n bool _metile_v34_r19 = _metile_v32_r19 & _metile_v33_r19;\n bool _metile_v34_r20 = _metile_v32_r20 & _metile_v33_r20;\n bool _metile_v34_r21 = _metile_v32_r21 & _metile_v33_r21;\n bool _metile_v34_r22 = _metile_v32_r22 & _metile_v33_r22;\n bool _metile_v34_r23 = _metile_v32_r23 & _metile_v33_r23;\n bool _metile_v34_r24 = _metile_v32_r24 & _metile_v33_r24;\n bool _metile_v34_r25 = _metile_v32_r25 & _metile_v33_r25;\n bool _metile_v34_r26 = _metile_v32_r26 & _metile_v33_r26;\n bool _metile_v34_r27 = _metile_v32_r27 & _metile_v33_r27;\n bool _metile_v34_r28 = _metile_v32_r28 & _metile_v33_r28;\n bool _metile_v34_r29 = _metile_v32_r29 & _metile_v33_r29;\n bool _metile_v34_r30 = _metile_v32_r30 & _metile_v33_r30;\n bool _metile_v34_r31 = _metile_v32_r31 & _metile_v33_r31;\n half4 _metile_vector_load________;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load________ = half4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load________[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load________[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load________[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load________[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n half _metile_v36_r0 = _metile_vector_load________[0];\n half _metile_v36_r1 = _metile_vector_load________[1];\n half _metile_v36_r2 = _metile_vector_load________[2];\n half _metile_v36_r3 = _metile_vector_load________[3];\n half4 _metile_vector_load_________;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load_________ = half4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load_________[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load_________[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load_________[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load_________[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n half _metile_v36_r4 = _metile_vector_load_________[0];\n half _metile_v36_r5 = _metile_vector_load_________[1];\n half _metile_v36_r6 = _metile_vector_load_________[2];\n half _metile_v36_r7 = _metile_vector_load_________[3];\n half4 _metile_vector_load__________;\n if ((_metile_v34_r8) && (_metile_v34_r9) && (_metile_v34_r10) && (_metile_v34_r11) && (long(_metile_register_index_________) == long(_metile_register_index________) + 1) && (long(_metile_register_index__________) == long(_metile_register_index________) + 2) && (long(_metile_register_index___________) == long(_metile_register_index________) + 3)) {\n _metile_vector_load__________ = half4(*reinterpret_cast(W + _metile_register_index________));\n } else {\n _metile_vector_load__________[0] = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n _metile_vector_load__________[1] = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n _metile_vector_load__________[2] = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n _metile_vector_load__________[3] = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n }\n half _metile_v36_r8 = _metile_vector_load__________[0];\n half _metile_v36_r9 = _metile_vector_load__________[1];\n half _metile_v36_r10 = _metile_vector_load__________[2];\n half _metile_v36_r11 = _metile_vector_load__________[3];\n half4 _metile_vector_load___________;\n if ((_metile_v34_r12) && (_metile_v34_r13) && (_metile_v34_r14) && (_metile_v34_r15) && (long(_metile_register_index_____________) == long(_metile_register_index____________) + 1) && (long(_metile_register_index______________) == long(_metile_register_index____________) + 2) && (long(_metile_register_index_______________) == long(_metile_register_index____________) + 3)) {\n _metile_vector_load___________ = half4(*reinterpret_cast(W + _metile_register_index____________));\n } else {\n _metile_vector_load___________[0] = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n _metile_vector_load___________[1] = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n _metile_vector_load___________[2] = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n _metile_vector_load___________[3] = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n }\n half _metile_v36_r12 = _metile_vector_load___________[0];\n half _metile_v36_r13 = _metile_vector_load___________[1];\n half _metile_v36_r14 = _metile_vector_load___________[2];\n half _metile_v36_r15 = _metile_vector_load___________[3];\n half4 _metile_vector_load____________;\n if ((_metile_v34_r16) && (_metile_v34_r17) && (_metile_v34_r18) && (_metile_v34_r19) && (long(_metile_register_index_________________) == long(_metile_register_index________________) + 1) && (long(_metile_register_index__________________) == long(_metile_register_index________________) + 2) && (long(_metile_register_index___________________) == long(_metile_register_index________________) + 3)) {\n _metile_vector_load____________ = half4(*reinterpret_cast(W + _metile_register_index________________));\n } else {\n _metile_vector_load____________[0] = _metile_v34_r16 ? W[_metile_register_index________________] : static_cast(0);\n _metile_vector_load____________[1] = _metile_v34_r17 ? W[_metile_register_index_________________] : static_cast(0);\n _metile_vector_load____________[2] = _metile_v34_r18 ? W[_metile_register_index__________________] : static_cast(0);\n _metile_vector_load____________[3] = _metile_v34_r19 ? W[_metile_register_index___________________] : static_cast(0);\n }\n half _metile_v36_r16 = _metile_vector_load____________[0];\n half _metile_v36_r17 = _metile_vector_load____________[1];\n half _metile_v36_r18 = _metile_vector_load____________[2];\n half _metile_v36_r19 = _metile_vector_load____________[3];\n half4 _metile_vector_load_____________;\n if ((_metile_v34_r20) && (_metile_v34_r21) && (_metile_v34_r22) && (_metile_v34_r23) && (long(_metile_register_index_____________________) == long(_metile_register_index____________________) + 1) && (long(_metile_register_index______________________) == long(_metile_register_index____________________) + 2) && (long(_metile_register_index_______________________) == long(_metile_register_index____________________) + 3)) {\n _metile_vector_load_____________ = half4(*reinterpret_cast(W + _metile_register_index____________________));\n } else {\n _metile_vector_load_____________[0] = _metile_v34_r20 ? W[_metile_register_index____________________] : static_cast(0);\n _metile_vector_load_____________[1] = _metile_v34_r21 ? W[_metile_register_index_____________________] : static_cast(0);\n _metile_vector_load_____________[2] = _metile_v34_r22 ? W[_metile_register_index______________________] : static_cast(0);\n _metile_vector_load_____________[3] = _metile_v34_r23 ? W[_metile_register_index_______________________] : static_cast(0);\n }\n half _metile_v36_r20 = _metile_vector_load_____________[0];\n half _metile_v36_r21 = _metile_vector_load_____________[1];\n half _metile_v36_r22 = _metile_vector_load_____________[2];\n half _metile_v36_r23 = _metile_vector_load_____________[3];\n half4 _metile_vector_load______________;\n if ((_metile_v34_r24) && (_metile_v34_r25) && (_metile_v34_r26) && (_metile_v34_r27) && (long(_metile_register_index_________________________) == long(_metile_register_index________________________) + 1) && (long(_metile_register_index__________________________) == long(_metile_register_index________________________) + 2) && (long(_metile_register_index___________________________) == long(_metile_register_index________________________) + 3)) {\n _metile_vector_load______________ = half4(*reinterpret_cast(W + _metile_register_index________________________));\n } else {\n _metile_vector_load______________[0] = _metile_v34_r24 ? W[_metile_register_index________________________] : static_cast(0);\n _metile_vector_load______________[1] = _metile_v34_r25 ? W[_metile_register_index_________________________] : static_cast(0);\n _metile_vector_load______________[2] = _metile_v34_r26 ? W[_metile_register_index__________________________] : static_cast(0);\n _metile_vector_load______________[3] = _metile_v34_r27 ? W[_metile_register_index___________________________] : static_cast(0);\n }\n half _metile_v36_r24 = _metile_vector_load______________[0];\n half _metile_v36_r25 = _metile_vector_load______________[1];\n half _metile_v36_r26 = _metile_vector_load______________[2];\n half _metile_v36_r27 = _metile_vector_load______________[3];\n half4 _metile_vector_load_______________;\n if ((_metile_v34_r28) && (_metile_v34_r29) && (_metile_v34_r30) && (_metile_v34_r31) && (long(_metile_register_index_____________________________) == long(_metile_register_index____________________________) + 1) && (long(_metile_register_index______________________________) == long(_metile_register_index____________________________) + 2) && (long(_metile_register_index_______________________________) == long(_metile_register_index____________________________) + 3)) {\n _metile_vector_load_______________ = half4(*reinterpret_cast(W + _metile_register_index____________________________));\n } else {\n _metile_vector_load_______________[0] = _metile_v34_r28 ? W[_metile_register_index____________________________] : static_cast(0);\n _metile_vector_load_______________[1] = _metile_v34_r29 ? W[_metile_register_index_____________________________] : static_cast(0);\n _metile_vector_load_______________[2] = _metile_v34_r30 ? W[_metile_register_index______________________________] : static_cast(0);\n _metile_vector_load_______________[3] = _metile_v34_r31 ? W[_metile_register_index_______________________________] : static_cast(0);\n }\n half _metile_v36_r28 = _metile_vector_load_______________[0];\n half _metile_v36_r29 = _metile_vector_load_______________[1];\n half _metile_v36_r30 = _metile_vector_load_______________[2];\n half _metile_v36_r31 = _metile_vector_load_______________[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v37_r16 = static_cast(_metile_v36_r16);\n float _metile_v37_r17 = static_cast(_metile_v36_r17);\n float _metile_v37_r18 = static_cast(_metile_v36_r18);\n float _metile_v37_r19 = static_cast(_metile_v36_r19);\n float _metile_v37_r20 = static_cast(_metile_v36_r20);\n float _metile_v37_r21 = static_cast(_metile_v36_r21);\n float _metile_v37_r22 = static_cast(_metile_v36_r22);\n float _metile_v37_r23 = static_cast(_metile_v36_r23);\n float _metile_v37_r24 = static_cast(_metile_v36_r24);\n float _metile_v37_r25 = static_cast(_metile_v36_r25);\n float _metile_v37_r26 = static_cast(_metile_v36_r26);\n float _metile_v37_r27 = static_cast(_metile_v36_r27);\n float _metile_v37_r28 = static_cast(_metile_v36_r28);\n float _metile_v37_r29 = static_cast(_metile_v36_r29);\n float _metile_v37_r30 = static_cast(_metile_v36_r30);\n float _metile_v37_r31 = static_cast(_metile_v36_r31);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v38_r16 = _metile_v21_r16 * v29;\n float _metile_v38_r17 = _metile_v21_r17 * v29;\n float _metile_v38_r18 = _metile_v21_r18 * v29;\n float _metile_v38_r19 = _metile_v21_r19 * v29;\n float _metile_v38_r20 = _metile_v21_r20 * v29;\n float _metile_v38_r21 = _metile_v21_r21 * v29;\n float _metile_v38_r22 = _metile_v21_r22 * v29;\n float _metile_v38_r23 = _metile_v21_r23 * v29;\n float _metile_v38_r24 = _metile_v21_r24 * v29;\n float _metile_v38_r25 = _metile_v21_r25 * v29;\n float _metile_v38_r26 = _metile_v21_r26 * v29;\n float _metile_v38_r27 = _metile_v21_r27 * v29;\n float _metile_v38_r28 = _metile_v21_r28 * v29;\n float _metile_v38_r29 = _metile_v21_r29 * v29;\n float _metile_v38_r30 = _metile_v21_r30 * v29;\n float _metile_v38_r31 = _metile_v21_r31 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n float _metile_v39_r16 = _metile_v38_r16 * _metile_v37_r16;\n float _metile_v39_r17 = _metile_v38_r17 * _metile_v37_r17;\n float _metile_v39_r18 = _metile_v38_r18 * _metile_v37_r18;\n float _metile_v39_r19 = _metile_v38_r19 * _metile_v37_r19;\n float _metile_v39_r20 = _metile_v38_r20 * _metile_v37_r20;\n float _metile_v39_r21 = _metile_v38_r21 * _metile_v37_r21;\n float _metile_v39_r22 = _metile_v38_r22 * _metile_v37_r22;\n float _metile_v39_r23 = _metile_v38_r23 * _metile_v37_r23;\n float _metile_v39_r24 = _metile_v38_r24 * _metile_v37_r24;\n float _metile_v39_r25 = _metile_v38_r25 * _metile_v37_r25;\n float _metile_v39_r26 = _metile_v38_r26 * _metile_v37_r26;\n float _metile_v39_r27 = _metile_v38_r27 * _metile_v37_r27;\n float _metile_v39_r28 = _metile_v38_r28 * _metile_v37_r28;\n float _metile_v39_r29 = _metile_v38_r29 * _metile_v37_r29;\n float _metile_v39_r30 = _metile_v38_r30 * _metile_v37_r30;\n float _metile_v39_r31 = _metile_v38_r31 * _metile_v37_r31;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v41_r16 = _metile_register_index________________ >= 0;\n bool _metile_v41_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v41_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v41_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v41_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v41_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v41_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v41_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v41_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v41_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v41_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v41_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v41_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v41_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v41_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v41_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v42_r8 = _metile_register_index________ < 1009;\n bool _metile_v42_r9 = _metile_register_index_________ < 1009;\n bool _metile_v42_r10 = _metile_register_index__________ < 1009;\n bool _metile_v42_r11 = _metile_register_index___________ < 1009;\n bool _metile_v42_r12 = _metile_register_index____________ < 1009;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v42_r14 = _metile_register_index______________ < 1009;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v42_r16 = _metile_register_index________________ < 1009;\n bool _metile_v42_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v42_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v42_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v42_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v42_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v42_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v42_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v42_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v42_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v42_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v42_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v42_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v42_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v42_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v42_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n bool _metile_v43_r16 = _metile_v41_r16 & _metile_v42_r16;\n bool _metile_v43_r17 = _metile_v41_r17 & _metile_v42_r17;\n bool _metile_v43_r18 = _metile_v41_r18 & _metile_v42_r18;\n bool _metile_v43_r19 = _metile_v41_r19 & _metile_v42_r19;\n bool _metile_v43_r20 = _metile_v41_r20 & _metile_v42_r20;\n bool _metile_v43_r21 = _metile_v41_r21 & _metile_v42_r21;\n bool _metile_v43_r22 = _metile_v41_r22 & _metile_v42_r22;\n bool _metile_v43_r23 = _metile_v41_r23 & _metile_v42_r23;\n bool _metile_v43_r24 = _metile_v41_r24 & _metile_v42_r24;\n bool _metile_v43_r25 = _metile_v41_r25 & _metile_v42_r25;\n bool _metile_v43_r26 = _metile_v41_r26 & _metile_v42_r26;\n bool _metile_v43_r27 = _metile_v41_r27 & _metile_v42_r27;\n bool _metile_v43_r28 = _metile_v41_r28 & _metile_v42_r28;\n bool _metile_v43_r29 = _metile_v41_r29 & _metile_v42_r29;\n bool _metile_v43_r30 = _metile_v41_r30 & _metile_v42_r30;\n bool _metile_v43_r31 = _metile_v41_r31 & _metile_v42_r31;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n int _off__metile_v44_r16 = v9 + _metile_register_index________________;\n int _off__metile_v44_r17 = v9 + _metile_register_index_________________;\n int _off__metile_v44_r18 = v9 + _metile_register_index__________________;\n int _off__metile_v44_r19 = v9 + _metile_register_index___________________;\n int _off__metile_v44_r20 = v9 + _metile_register_index____________________;\n int _off__metile_v44_r21 = v9 + _metile_register_index_____________________;\n int _off__metile_v44_r22 = v9 + _metile_register_index______________________;\n int _off__metile_v44_r23 = v9 + _metile_register_index_______________________;\n int _off__metile_v44_r24 = v9 + _metile_register_index________________________;\n int _off__metile_v44_r25 = v9 + _metile_register_index_________________________;\n int _off__metile_v44_r26 = v9 + _metile_register_index__________________________;\n int _off__metile_v44_r27 = v9 + _metile_register_index___________________________;\n int _off__metile_v44_r28 = v9 + _metile_register_index____________________________;\n int _off__metile_v44_r29 = v9 + _metile_register_index_____________________________;\n int _off__metile_v44_r30 = v9 + _metile_register_index______________________________;\n int _off__metile_v44_r31 = v9 + _metile_register_index_______________________________;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_half4(half4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_half4(half4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n if ((_metile_v43_r8) && (_metile_v43_r9) && (_metile_v43_r10) && (_metile_v43_r11) && (long(_off__metile_v44_r9) == long(_off__metile_v44_r8) + 1) && (long(_off__metile_v44_r10) == long(_off__metile_v44_r8) + 2) && (long(_off__metile_v44_r11) == long(_off__metile_v44_r8) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r8) = packed_half4(half4(static_cast(_metile_v39_r8), static_cast(_metile_v39_r9), static_cast(_metile_v39_r10), static_cast(_metile_v39_r11)));\n } else {\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = static_cast(_metile_v39_r8); }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = static_cast(_metile_v39_r9); }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = static_cast(_metile_v39_r10); }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = static_cast(_metile_v39_r11); }\n }\n if ((_metile_v43_r12) && (_metile_v43_r13) && (_metile_v43_r14) && (_metile_v43_r15) && (long(_off__metile_v44_r13) == long(_off__metile_v44_r12) + 1) && (long(_off__metile_v44_r14) == long(_off__metile_v44_r12) + 2) && (long(_off__metile_v44_r15) == long(_off__metile_v44_r12) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r12) = packed_half4(half4(static_cast(_metile_v39_r12), static_cast(_metile_v39_r13), static_cast(_metile_v39_r14), static_cast(_metile_v39_r15)));\n } else {\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = static_cast(_metile_v39_r12); }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = static_cast(_metile_v39_r13); }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = static_cast(_metile_v39_r14); }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = static_cast(_metile_v39_r15); }\n }\n if ((_metile_v43_r16) && (_metile_v43_r17) && (_metile_v43_r18) && (_metile_v43_r19) && (long(_off__metile_v44_r17) == long(_off__metile_v44_r16) + 1) && (long(_off__metile_v44_r18) == long(_off__metile_v44_r16) + 2) && (long(_off__metile_v44_r19) == long(_off__metile_v44_r16) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r16) = packed_half4(half4(static_cast(_metile_v39_r16), static_cast(_metile_v39_r17), static_cast(_metile_v39_r18), static_cast(_metile_v39_r19)));\n } else {\n if (_metile_v43_r16) { Out[_off__metile_v44_r16] = static_cast(_metile_v39_r16); }\n if (_metile_v43_r17) { Out[_off__metile_v44_r17] = static_cast(_metile_v39_r17); }\n if (_metile_v43_r18) { Out[_off__metile_v44_r18] = static_cast(_metile_v39_r18); }\n if (_metile_v43_r19) { Out[_off__metile_v44_r19] = static_cast(_metile_v39_r19); }\n }\n if ((_metile_v43_r20) && (_metile_v43_r21) && (_metile_v43_r22) && (_metile_v43_r23) && (long(_off__metile_v44_r21) == long(_off__metile_v44_r20) + 1) && (long(_off__metile_v44_r22) == long(_off__metile_v44_r20) + 2) && (long(_off__metile_v44_r23) == long(_off__metile_v44_r20) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r20) = packed_half4(half4(static_cast(_metile_v39_r20), static_cast(_metile_v39_r21), static_cast(_metile_v39_r22), static_cast(_metile_v39_r23)));\n } else {\n if (_metile_v43_r20) { Out[_off__metile_v44_r20] = static_cast(_metile_v39_r20); }\n if (_metile_v43_r21) { Out[_off__metile_v44_r21] = static_cast(_metile_v39_r21); }\n if (_metile_v43_r22) { Out[_off__metile_v44_r22] = static_cast(_metile_v39_r22); }\n if (_metile_v43_r23) { Out[_off__metile_v44_r23] = static_cast(_metile_v39_r23); }\n }\n if ((_metile_v43_r24) && (_metile_v43_r25) && (_metile_v43_r26) && (_metile_v43_r27) && (long(_off__metile_v44_r25) == long(_off__metile_v44_r24) + 1) && (long(_off__metile_v44_r26) == long(_off__metile_v44_r24) + 2) && (long(_off__metile_v44_r27) == long(_off__metile_v44_r24) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r24) = packed_half4(half4(static_cast(_metile_v39_r24), static_cast(_metile_v39_r25), static_cast(_metile_v39_r26), static_cast(_metile_v39_r27)));\n } else {\n if (_metile_v43_r24) { Out[_off__metile_v44_r24] = static_cast(_metile_v39_r24); }\n if (_metile_v43_r25) { Out[_off__metile_v44_r25] = static_cast(_metile_v39_r25); }\n if (_metile_v43_r26) { Out[_off__metile_v44_r26] = static_cast(_metile_v39_r26); }\n if (_metile_v43_r27) { Out[_off__metile_v44_r27] = static_cast(_metile_v39_r27); }\n }\n if ((_metile_v43_r28) && (_metile_v43_r29) && (_metile_v43_r30) && (_metile_v43_r31) && (long(_off__metile_v44_r29) == long(_off__metile_v44_r28) + 1) && (long(_off__metile_v44_r30) == long(_off__metile_v44_r28) + 2) && (long(_off__metile_v44_r31) == long(_off__metile_v44_r28) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r28) = packed_half4(half4(static_cast(_metile_v39_r28), static_cast(_metile_v39_r29), static_cast(_metile_v39_r30), static_cast(_metile_v39_r31)));\n } else {\n if (_metile_v43_r28) { Out[_off__metile_v44_r28] = static_cast(_metile_v39_r28); }\n if (_metile_v43_r29) { Out[_off__metile_v44_r29] = static_cast(_metile_v39_r29); }\n if (_metile_v43_r30) { Out[_off__metile_v44_r30] = static_cast(_metile_v39_r30); }\n if (_metile_v43_r31) { Out[_off__metile_v44_r31] = static_cast(_metile_v39_r31); }\n }\n}", "source_sha256": "56609b88a4b5b52c4d86d853e94eea93cb604868c18edef7efe33f8c98978f8f", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 32, 1, 1 ], "is_gemm": false, "prefer_ordered": false, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 32, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 32 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [], "double_buffered": false, "vectorized_loads": 16, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 32, "threads": 32, "scratch": null, "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 16, "grouped_stores": 8 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 593, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.541, "control": 201.917, "speedup": 0.9871712761744589 }, "gpu_us": { "candidate": 4.249974153935909, "control": 2.00001522898674, "speedup": 0.4705946804722382 } } }, { "frozen_register4": { "pairs": 616, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.958, "control": 197.375, "speedup": 0.9970549308439164 }, "gpu_us": { "candidate": 4.249974153935909, "control": 2.00001522898674, "speedup": 0.4705946804722382 } } }, { "frozen_register4": { "pairs": 613, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.917, "control": 198.541, "speedup": 0.9931171436146 }, "gpu_us": { "candidate": 4.249974153935909, "control": 2.00001522898674, "speedup": 0.4705946804722382 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.992439462605115, "round_speedups": [ 0.9871712761744589, 0.9970549308439164, 0.9931171436146 ], "candidate": 200.78644299893696, "control": 199.2683895882573 }, "gpu_us": { "speedup": 0.4705946804722382, "round_speedups": [ 0.4705946804722382, 0.4705946804722382, 0.4705946804722382 ], "candidate": 4.249974153935909, "control": 2.00001522898674 } } } }, { "name": "float16_32x1009", "dtype": "float16", "batches": 32, "width": 1009, "status": "measured", "variant": { "name": "register2_striped", "elements_per_thread": 2, "layout": "striped" }, "input_sha256": "e6d696cff86bdf9ec8254c3438c13725f24b2b1f6073b44660a256dcea0488a8", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 511;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 512;\n int _metile_register_index_ = int(_metile_register_packed_);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n threadgroup float _metile_register_reduction[16];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 16u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n}", "source_sha256": "6b537a48d161d28743d3b80a917a7b5c4532cf32e542d68bd7d3a3e00bbe03ab", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 512, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 512, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 2 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 16, "bytes": 64 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 2, "threads": 512, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 618, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.47899999999998, "control": 198.9795, "speedup": 1.0075982762724138 }, "gpu_us": { "candidate": 2.0416919142007828, "control": 2.00001522898674, "speedup": 0.9795871821188277 } } }, { "frozen_register4": { "pairs": 553, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 205.667, "control": 205.5, "speedup": 0.999188007799015 }, "gpu_us": { "candidate": 2.0833685994148254, "control": 2.0833685994148254, "speedup": 1.0 } } }, { "frozen_register4": { "pairs": 622, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.438, "control": 197.85399999999998, "speedup": 1.0021069905489317 }, "gpu_us": { "candidate": 2.0416919142007828, "control": 2.00001522898674, "speedup": 0.9795871821188277 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.002958369590896, "round_speedups": [ 1.0075982762724138, 0.999188007799015, 1.0021069905489317 ], "candidate": 200.15760319213805, "control": 200.74974335880822 }, "gpu_us": { "speedup": 0.986344731515852, "round_speedups": [ 0.9795871821188277, 1.0, 0.9795871821188277 ], "candidate": 2.0554906736965313, "control": 2.0274223966805427 } } } }, { "name": "float16_32x1009", "dtype": "float16", "batches": 32, "width": 1009, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "e6d696cff86bdf9ec8254c3438c13725f24b2b1f6073b44660a256dcea0488a8", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "ca8204464d79c2fc321323a988388e3cf7608e7f4edfce8846896960ec8dd552", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 596, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.3125, "control": 197.79149999999998, "speedup": 0.9973728332808067 }, "gpu_us": { "candidate": 1.9999570213258266, "control": 2.00001522898674, "speedup": 1.0000291044558922 } } }, { "frozen_register4": { "pairs": 410, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 222.89600000000002, "control": 228.52100000000002, "speedup": 1.0252359844950112 }, "gpu_us": { "candidate": 3.1249946914613247, "control": 3.291643224656582, "speedup": 1.053327621211839 } } }, { "frozen_register4": { "pairs": 616, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.2295, "control": 200.5625, "speedup": 1.0066907762153696 }, "gpu_us": { "candidate": 1.9999570213258266, "control": 2.00001522898674, "speedup": 1.0000291044558922 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.009700307056494, "round_speedups": [ 0.9973728332808067, 1.0252359844950112, 1.0066907762153696 ], "candidate": 206.50726573804238, "control": 208.51044962509835 }, "gpu_us": { "speedup": 1.0174886749748888, "round_speedups": [ 1.0000291044558922, 1.053327621211839, 1.0000291044558922 ], "candidate": 2.3207598543468317, "control": 2.3613468691342736 } } } }, { "name": "float16_256x1009", "dtype": "float16", "batches": 256, "width": 1009, "status": "measured", "variant": { "name": "register8_striped", "elements_per_thread": 8, "layout": "striped" }, "input_sha256": "3fe4b7685e23d624bcb19d6442cc8d72636943e6c185f3b0049a2ac1e0b63d81", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 127;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 128;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 256;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 384;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 512;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 640;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 768;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 896;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n half _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n half _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n half _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n half _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_____ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum______ = _metile_register_sum____ + _metile_register_sum_____;\n threadgroup float _metile_register_reduction[4];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 4u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n half _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n half _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n half _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n half _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n}", "source_sha256": "b4460a3d9f572d27169c13ec23164de0b27d29f07cf7c168c5a7763c87c06b01", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 128, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 128, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 8 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 4, "bytes": 16 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 8, "threads": 128, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 590, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 206.45850000000002, "control": 208.70850000000002, "speedup": 1.0108980739470643 }, "gpu_us": { "candidate": 5.250039976090193, "control": 5.5416603572666645, "speedup": 1.0555463163146517 } } }, { "frozen_register4": { "pairs": 556, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 211.10399999999998, "control": 213.312, "speedup": 1.0104592996816737 }, "gpu_us": { "candidate": 5.291658453643322, "control": 5.583337042480707, "speedup": 1.0551204487955121 } } }, { "frozen_register4": { "pairs": 583, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 207.583, "control": 208.5, "speedup": 1.004417510104392 }, "gpu_us": { "candidate": 5.291658453643322, "control": 5.583337042480707, "speedup": 1.0551204487955121 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0085872873834265, "round_speedups": [ 1.0108980739470643, 1.0104592996816737, 1.004417510104392 ], "candidate": 208.37246917602982, "control": 210.16182345163864 }, "gpu_us": { "speedup": 1.0552623855407768, "round_speedups": [ 1.0555463163146517, 1.0551204487955121, 1.0551204487955121 ], "candidate": 5.277749098479618, "control": 5.569410103947287 } } } }, { "name": "float16_256x1009", "dtype": "float16", "batches": 256, "width": 1009, "status": "measured", "variant": { "name": "register8_blocked4", "elements_per_thread": 8, "layout": "blocked4" }, "input_sha256": "3fe4b7685e23d624bcb19d6442cc8d72636943e6c185f3b0049a2ac1e0b63d81", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 127;\n int _metile_register_index = int((((_metile_bounded_thread >> 7) & 1u) << 0) | (((_metile_bounded_thread >> 8) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 6) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 128;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 7) & 1u) << 0) | (((_metile_register_packed_ >> 8) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 6) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 256;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 7) & 1u) << 0) | (((_metile_register_packed__ >> 8) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 6) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 384;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 7) & 1u) << 0) | (((_metile_register_packed___ >> 8) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 6) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 512;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 7) & 1u) << 0) | (((_metile_register_packed____ >> 8) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 5) & 1u) << 7) | (((_metile_register_packed____ >> 6) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 640;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 7) & 1u) << 0) | (((_metile_register_packed_____ >> 8) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 5) & 1u) << 7) | (((_metile_register_packed_____ >> 6) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 768;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 7) & 1u) << 0) | (((_metile_register_packed______ >> 8) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 5) & 1u) << 7) | (((_metile_register_packed______ >> 6) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 896;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 7) & 1u) << 0) | (((_metile_register_packed_______ >> 8) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 5) & 1u) << 7) | (((_metile_register_packed_______ >> 6) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n half4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = half4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n half _metile_v20_r0 = _metile_vector_load[0];\n half _metile_v20_r1 = _metile_vector_load[1];\n half _metile_v20_r2 = _metile_vector_load[2];\n half _metile_v20_r3 = _metile_vector_load[3];\n half4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = half4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n half _metile_v20_r4 = _metile_vector_load_[0];\n half _metile_v20_r5 = _metile_vector_load_[1];\n half _metile_v20_r6 = _metile_vector_load_[2];\n half _metile_v20_r7 = _metile_vector_load_[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_____ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum______ = _metile_register_sum____ + _metile_register_sum_____;\n threadgroup float _metile_register_reduction[4];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 4u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n half4 _metile_vector_load__;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load__ = half4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load__[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load__[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load__[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load__[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n half _metile_v36_r0 = _metile_vector_load__[0];\n half _metile_v36_r1 = _metile_vector_load__[1];\n half _metile_v36_r2 = _metile_vector_load__[2];\n half _metile_v36_r3 = _metile_vector_load__[3];\n half4 _metile_vector_load___;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load___ = half4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load___[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load___[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load___[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load___[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n half _metile_v36_r4 = _metile_vector_load___[0];\n half _metile_v36_r5 = _metile_vector_load___[1];\n half _metile_v36_r6 = _metile_vector_load___[2];\n half _metile_v36_r7 = _metile_vector_load___[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_half4(half4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_half4(half4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n}", "source_sha256": "4aeb4ec992d7174b6182b507a2b9a716bd1f0d8ebc18857adde04ecf0d617fd7", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 128, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 128, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 8 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 4, "bytes": 16 } ], "double_buffered": false, "vectorized_loads": 4, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 8, "threads": 128, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 4, "grouped_stores": 2 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 593, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 206.459, "control": 206.5, "speedup": 1.0001985866443217 }, "gpu_us": { "candidate": 6.125017534941435, "control": 5.583337042480707, "speedup": 0.9115626217605748 } } }, { "frozen_register4": { "pairs": 549, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 211.25, "control": 207.791, "speedup": 0.9836260355029586 }, "gpu_us": { "candidate": 6.1666942201554775, "control": 5.583337042480707, "speedup": 0.9054019614320908 } } }, { "frozen_register4": { "pairs": 577, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 208.542, "control": 206.958, "speedup": 0.9924044077452024 }, "gpu_us": { "candidate": 6.125017534941435, "control": 5.583337042480707, "speedup": 0.9115626217605748 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9920532377568475, "round_speedups": [ 1.0001985866443217, 0.9836260355029586, 0.9924044077452024 ], "candidate": 208.74112694408305, "control": 207.08231083789096 }, "gpu_us": { "speedup": 0.9095044246575547, "round_speedups": [ 0.9115626217605748, 0.9054019614320908, 0.9115626217605748 ], "candidate": 6.138878372783, "control": 5.583337042480708 } } } }, { "name": "float16_256x1009", "dtype": "float16", "batches": 256, "width": 1009, "status": "measured", "variant": { "name": "register16_striped", "elements_per_thread": 16, "layout": "striped" }, "input_sha256": "3fe4b7685e23d624bcb19d6442cc8d72636943e6c185f3b0049a2ac1e0b63d81", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 63;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 64;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 128;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 192;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 256;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 320;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 384;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 448;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n int _metile_register_packed________ = _metile_bounded_thread + 512;\n int _metile_register_index________ = int(_metile_register_packed________);\n int _metile_register_packed_________ = _metile_bounded_thread + 576;\n int _metile_register_index_________ = int(_metile_register_packed_________);\n int _metile_register_packed__________ = _metile_bounded_thread + 640;\n int _metile_register_index__________ = int(_metile_register_packed__________);\n int _metile_register_packed___________ = _metile_bounded_thread + 704;\n int _metile_register_index___________ = int(_metile_register_packed___________);\n int _metile_register_packed____________ = _metile_bounded_thread + 768;\n int _metile_register_index____________ = int(_metile_register_packed____________);\n int _metile_register_packed_____________ = _metile_bounded_thread + 832;\n int _metile_register_index_____________ = int(_metile_register_packed_____________);\n int _metile_register_packed______________ = _metile_bounded_thread + 896;\n int _metile_register_index______________ = int(_metile_register_packed______________);\n int _metile_register_packed_______________ = _metile_bounded_thread + 960;\n int _metile_register_index_______________ = int(_metile_register_packed_______________);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v17_r8 = _metile_register_index________ < 1009;\n bool _metile_v17_r9 = _metile_register_index_________ < 1009;\n bool _metile_v17_r10 = _metile_register_index__________ < 1009;\n bool _metile_v17_r11 = _metile_register_index___________ < 1009;\n bool _metile_v17_r12 = _metile_register_index____________ < 1009;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v17_r14 = _metile_register_index______________ < 1009;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n half _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n half _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n half _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n half _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n half _metile_v20_r8 = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n half _metile_v20_r9 = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n half _metile_v20_r10 = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n half _metile_v20_r11 = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n half _metile_v20_r12 = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n half _metile_v20_r13 = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n half _metile_v20_r14 = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n half _metile_v20_r15 = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________ = _metile_register_sum____________ + _metile_register_sum_____________;\n threadgroup float _metile_register_reduction[2];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______________);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 2u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v33_r8 = _metile_register_index________ < 1009;\n bool _metile_v33_r9 = _metile_register_index_________ < 1009;\n bool _metile_v33_r10 = _metile_register_index__________ < 1009;\n bool _metile_v33_r11 = _metile_register_index___________ < 1009;\n bool _metile_v33_r12 = _metile_register_index____________ < 1009;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v33_r14 = _metile_register_index______________ < 1009;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n half _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n half _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n half _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n half _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n half _metile_v36_r8 = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n half _metile_v36_r9 = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n half _metile_v36_r10 = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n half _metile_v36_r11 = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n half _metile_v36_r12 = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n half _metile_v36_r13 = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n half _metile_v36_r14 = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n half _metile_v36_r15 = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v42_r8 = _metile_register_index________ < 1009;\n bool _metile_v42_r9 = _metile_register_index_________ < 1009;\n bool _metile_v42_r10 = _metile_register_index__________ < 1009;\n bool _metile_v42_r11 = _metile_register_index___________ < 1009;\n bool _metile_v42_r12 = _metile_register_index____________ < 1009;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v42_r14 = _metile_register_index______________ < 1009;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = _metile_v39_r8; }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = _metile_v39_r9; }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = _metile_v39_r10; }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = _metile_v39_r11; }\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = _metile_v39_r12; }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = _metile_v39_r13; }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = _metile_v39_r14; }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = _metile_v39_r15; }\n}", "source_sha256": "fabd6e8e22cb59371bb98555d949a21e2b779ed4e5b695612d2857b9566e1617", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 64, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 64, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 16 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 2, "bytes": 8 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 16, "threads": 64, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 583, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 206.875, "control": 208.167, "speedup": 1.0062453172205439 }, "gpu_us": { "candidate": 5.375011824071407, "control": 5.583337042480707, "speedup": 1.0387580949080593 } } }, { "frozen_register4": { "pairs": 575, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.917, "control": 210.875, "speedup": 1.0290751865389403 }, "gpu_us": { "candidate": 5.375011824071407, "control": 5.583337042480707, "speedup": 1.0387580949080593 } } }, { "frozen_register4": { "pairs": 561, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 208.375, "control": 208.083, "speedup": 0.9985986802639472 }, "gpu_us": { "candidate": 5.41668850928545, "control": 5.624955520033836, "speedup": 1.0384491392464914 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0112238922665115, "round_speedups": [ 1.0062453172205439, 1.0290751865389403, 0.9985986802639472 ], "candidate": 206.71748109934387, "control": 209.03765583680763 }, "gpu_us": { "speedup": 1.0386550994756225, "round_speedups": [ 1.0387580949080593, 1.0387580949080593, 1.0384491392464914 ], "candidate": 5.388868300567584, "control": 5.597175540787054 } } } }, { "name": "float16_256x1009", "dtype": "float16", "batches": 256, "width": 1009, "status": "measured", "variant": { "name": "register16_blocked4", "elements_per_thread": 16, "layout": "blocked4" }, "input_sha256": "3fe4b7685e23d624bcb19d6442cc8d72636943e6c185f3b0049a2ac1e0b63d81", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 63;\n int _metile_register_index = int((((_metile_bounded_thread >> 6) & 1u) << 0) | (((_metile_bounded_thread >> 7) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 8) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 64;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 6) & 1u) << 0) | (((_metile_register_packed_ >> 7) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 8) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 128;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 6) & 1u) << 0) | (((_metile_register_packed__ >> 7) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 8) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 192;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 6) & 1u) << 0) | (((_metile_register_packed___ >> 7) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 8) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 256;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 6) & 1u) << 0) | (((_metile_register_packed____ >> 7) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 5) & 1u) << 7) | (((_metile_register_packed____ >> 8) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 320;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 6) & 1u) << 0) | (((_metile_register_packed_____ >> 7) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 5) & 1u) << 7) | (((_metile_register_packed_____ >> 8) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 384;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 6) & 1u) << 0) | (((_metile_register_packed______ >> 7) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 5) & 1u) << 7) | (((_metile_register_packed______ >> 8) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 448;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 6) & 1u) << 0) | (((_metile_register_packed_______ >> 7) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 5) & 1u) << 7) | (((_metile_register_packed_______ >> 8) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n int _metile_register_packed________ = _metile_bounded_thread + 512;\n int _metile_register_index________ = int((((_metile_register_packed________ >> 6) & 1u) << 0) | (((_metile_register_packed________ >> 7) & 1u) << 1) | (((_metile_register_packed________ >> 0) & 1u) << 2) | (((_metile_register_packed________ >> 1) & 1u) << 3) | (((_metile_register_packed________ >> 2) & 1u) << 4) | (((_metile_register_packed________ >> 3) & 1u) << 5) | (((_metile_register_packed________ >> 4) & 1u) << 6) | (((_metile_register_packed________ >> 5) & 1u) << 7) | (((_metile_register_packed________ >> 8) & 1u) << 8) | (((_metile_register_packed________ >> 9) & 1u) << 9));\n int _metile_register_packed_________ = _metile_bounded_thread + 576;\n int _metile_register_index_________ = int((((_metile_register_packed_________ >> 6) & 1u) << 0) | (((_metile_register_packed_________ >> 7) & 1u) << 1) | (((_metile_register_packed_________ >> 0) & 1u) << 2) | (((_metile_register_packed_________ >> 1) & 1u) << 3) | (((_metile_register_packed_________ >> 2) & 1u) << 4) | (((_metile_register_packed_________ >> 3) & 1u) << 5) | (((_metile_register_packed_________ >> 4) & 1u) << 6) | (((_metile_register_packed_________ >> 5) & 1u) << 7) | (((_metile_register_packed_________ >> 8) & 1u) << 8) | (((_metile_register_packed_________ >> 9) & 1u) << 9));\n int _metile_register_packed__________ = _metile_bounded_thread + 640;\n int _metile_register_index__________ = int((((_metile_register_packed__________ >> 6) & 1u) << 0) | (((_metile_register_packed__________ >> 7) & 1u) << 1) | (((_metile_register_packed__________ >> 0) & 1u) << 2) | (((_metile_register_packed__________ >> 1) & 1u) << 3) | (((_metile_register_packed__________ >> 2) & 1u) << 4) | (((_metile_register_packed__________ >> 3) & 1u) << 5) | (((_metile_register_packed__________ >> 4) & 1u) << 6) | (((_metile_register_packed__________ >> 5) & 1u) << 7) | (((_metile_register_packed__________ >> 8) & 1u) << 8) | (((_metile_register_packed__________ >> 9) & 1u) << 9));\n int _metile_register_packed___________ = _metile_bounded_thread + 704;\n int _metile_register_index___________ = int((((_metile_register_packed___________ >> 6) & 1u) << 0) | (((_metile_register_packed___________ >> 7) & 1u) << 1) | (((_metile_register_packed___________ >> 0) & 1u) << 2) | (((_metile_register_packed___________ >> 1) & 1u) << 3) | (((_metile_register_packed___________ >> 2) & 1u) << 4) | (((_metile_register_packed___________ >> 3) & 1u) << 5) | (((_metile_register_packed___________ >> 4) & 1u) << 6) | (((_metile_register_packed___________ >> 5) & 1u) << 7) | (((_metile_register_packed___________ >> 8) & 1u) << 8) | (((_metile_register_packed___________ >> 9) & 1u) << 9));\n int _metile_register_packed____________ = _metile_bounded_thread + 768;\n int _metile_register_index____________ = int((((_metile_register_packed____________ >> 6) & 1u) << 0) | (((_metile_register_packed____________ >> 7) & 1u) << 1) | (((_metile_register_packed____________ >> 0) & 1u) << 2) | (((_metile_register_packed____________ >> 1) & 1u) << 3) | (((_metile_register_packed____________ >> 2) & 1u) << 4) | (((_metile_register_packed____________ >> 3) & 1u) << 5) | (((_metile_register_packed____________ >> 4) & 1u) << 6) | (((_metile_register_packed____________ >> 5) & 1u) << 7) | (((_metile_register_packed____________ >> 8) & 1u) << 8) | (((_metile_register_packed____________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________ = _metile_bounded_thread + 832;\n int _metile_register_index_____________ = int((((_metile_register_packed_____________ >> 6) & 1u) << 0) | (((_metile_register_packed_____________ >> 7) & 1u) << 1) | (((_metile_register_packed_____________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________ >> 5) & 1u) << 7) | (((_metile_register_packed_____________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________ >> 9) & 1u) << 9));\n int _metile_register_packed______________ = _metile_bounded_thread + 896;\n int _metile_register_index______________ = int((((_metile_register_packed______________ >> 6) & 1u) << 0) | (((_metile_register_packed______________ >> 7) & 1u) << 1) | (((_metile_register_packed______________ >> 0) & 1u) << 2) | (((_metile_register_packed______________ >> 1) & 1u) << 3) | (((_metile_register_packed______________ >> 2) & 1u) << 4) | (((_metile_register_packed______________ >> 3) & 1u) << 5) | (((_metile_register_packed______________ >> 4) & 1u) << 6) | (((_metile_register_packed______________ >> 5) & 1u) << 7) | (((_metile_register_packed______________ >> 8) & 1u) << 8) | (((_metile_register_packed______________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________ = _metile_bounded_thread + 960;\n int _metile_register_index_______________ = int((((_metile_register_packed_______________ >> 6) & 1u) << 0) | (((_metile_register_packed_______________ >> 7) & 1u) << 1) | (((_metile_register_packed_______________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________ >> 5) & 1u) << 7) | (((_metile_register_packed_______________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v17_r8 = _metile_register_index________ < 1009;\n bool _metile_v17_r9 = _metile_register_index_________ < 1009;\n bool _metile_v17_r10 = _metile_register_index__________ < 1009;\n bool _metile_v17_r11 = _metile_register_index___________ < 1009;\n bool _metile_v17_r12 = _metile_register_index____________ < 1009;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v17_r14 = _metile_register_index______________ < 1009;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n half4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = half4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n half _metile_v20_r0 = _metile_vector_load[0];\n half _metile_v20_r1 = _metile_vector_load[1];\n half _metile_v20_r2 = _metile_vector_load[2];\n half _metile_v20_r3 = _metile_vector_load[3];\n half4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = half4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n half _metile_v20_r4 = _metile_vector_load_[0];\n half _metile_v20_r5 = _metile_vector_load_[1];\n half _metile_v20_r6 = _metile_vector_load_[2];\n half _metile_v20_r7 = _metile_vector_load_[3];\n half4 _metile_vector_load__;\n if ((_metile_v18_r8) && (_metile_v18_r9) && (_metile_v18_r10) && (_metile_v18_r11) && (long(_off__metile_v19_r9) == long(_off__metile_v19_r8) + 1) && (long(_off__metile_v19_r10) == long(_off__metile_v19_r8) + 2) && (long(_off__metile_v19_r11) == long(_off__metile_v19_r8) + 3)) {\n _metile_vector_load__ = half4(*reinterpret_cast(X + _off__metile_v19_r8));\n } else {\n _metile_vector_load__[0] = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n _metile_vector_load__[1] = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n _metile_vector_load__[2] = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n _metile_vector_load__[3] = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n }\n half _metile_v20_r8 = _metile_vector_load__[0];\n half _metile_v20_r9 = _metile_vector_load__[1];\n half _metile_v20_r10 = _metile_vector_load__[2];\n half _metile_v20_r11 = _metile_vector_load__[3];\n half4 _metile_vector_load___;\n if ((_metile_v18_r12) && (_metile_v18_r13) && (_metile_v18_r14) && (_metile_v18_r15) && (long(_off__metile_v19_r13) == long(_off__metile_v19_r12) + 1) && (long(_off__metile_v19_r14) == long(_off__metile_v19_r12) + 2) && (long(_off__metile_v19_r15) == long(_off__metile_v19_r12) + 3)) {\n _metile_vector_load___ = half4(*reinterpret_cast(X + _off__metile_v19_r12));\n } else {\n _metile_vector_load___[0] = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n _metile_vector_load___[1] = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n _metile_vector_load___[2] = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n _metile_vector_load___[3] = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n }\n half _metile_v20_r12 = _metile_vector_load___[0];\n half _metile_v20_r13 = _metile_vector_load___[1];\n half _metile_v20_r14 = _metile_vector_load___[2];\n half _metile_v20_r15 = _metile_vector_load___[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________ = _metile_register_sum____________ + _metile_register_sum_____________;\n threadgroup float _metile_register_reduction[2];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______________);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 2u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v33_r8 = _metile_register_index________ < 1009;\n bool _metile_v33_r9 = _metile_register_index_________ < 1009;\n bool _metile_v33_r10 = _metile_register_index__________ < 1009;\n bool _metile_v33_r11 = _metile_register_index___________ < 1009;\n bool _metile_v33_r12 = _metile_register_index____________ < 1009;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v33_r14 = _metile_register_index______________ < 1009;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n half4 _metile_vector_load____;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load____ = half4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load____[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load____[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load____[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load____[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n half _metile_v36_r0 = _metile_vector_load____[0];\n half _metile_v36_r1 = _metile_vector_load____[1];\n half _metile_v36_r2 = _metile_vector_load____[2];\n half _metile_v36_r3 = _metile_vector_load____[3];\n half4 _metile_vector_load_____;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load_____ = half4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load_____[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load_____[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load_____[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load_____[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n half _metile_v36_r4 = _metile_vector_load_____[0];\n half _metile_v36_r5 = _metile_vector_load_____[1];\n half _metile_v36_r6 = _metile_vector_load_____[2];\n half _metile_v36_r7 = _metile_vector_load_____[3];\n half4 _metile_vector_load______;\n if ((_metile_v34_r8) && (_metile_v34_r9) && (_metile_v34_r10) && (_metile_v34_r11) && (long(_metile_register_index_________) == long(_metile_register_index________) + 1) && (long(_metile_register_index__________) == long(_metile_register_index________) + 2) && (long(_metile_register_index___________) == long(_metile_register_index________) + 3)) {\n _metile_vector_load______ = half4(*reinterpret_cast(W + _metile_register_index________));\n } else {\n _metile_vector_load______[0] = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n _metile_vector_load______[1] = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n _metile_vector_load______[2] = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n _metile_vector_load______[3] = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n }\n half _metile_v36_r8 = _metile_vector_load______[0];\n half _metile_v36_r9 = _metile_vector_load______[1];\n half _metile_v36_r10 = _metile_vector_load______[2];\n half _metile_v36_r11 = _metile_vector_load______[3];\n half4 _metile_vector_load_______;\n if ((_metile_v34_r12) && (_metile_v34_r13) && (_metile_v34_r14) && (_metile_v34_r15) && (long(_metile_register_index_____________) == long(_metile_register_index____________) + 1) && (long(_metile_register_index______________) == long(_metile_register_index____________) + 2) && (long(_metile_register_index_______________) == long(_metile_register_index____________) + 3)) {\n _metile_vector_load_______ = half4(*reinterpret_cast(W + _metile_register_index____________));\n } else {\n _metile_vector_load_______[0] = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n _metile_vector_load_______[1] = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n _metile_vector_load_______[2] = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n _metile_vector_load_______[3] = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n }\n half _metile_v36_r12 = _metile_vector_load_______[0];\n half _metile_v36_r13 = _metile_vector_load_______[1];\n half _metile_v36_r14 = _metile_vector_load_______[2];\n half _metile_v36_r15 = _metile_vector_load_______[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v42_r8 = _metile_register_index________ < 1009;\n bool _metile_v42_r9 = _metile_register_index_________ < 1009;\n bool _metile_v42_r10 = _metile_register_index__________ < 1009;\n bool _metile_v42_r11 = _metile_register_index___________ < 1009;\n bool _metile_v42_r12 = _metile_register_index____________ < 1009;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v42_r14 = _metile_register_index______________ < 1009;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_half4(half4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_half4(half4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n if ((_metile_v43_r8) && (_metile_v43_r9) && (_metile_v43_r10) && (_metile_v43_r11) && (long(_off__metile_v44_r9) == long(_off__metile_v44_r8) + 1) && (long(_off__metile_v44_r10) == long(_off__metile_v44_r8) + 2) && (long(_off__metile_v44_r11) == long(_off__metile_v44_r8) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r8) = packed_half4(half4(static_cast(_metile_v39_r8), static_cast(_metile_v39_r9), static_cast(_metile_v39_r10), static_cast(_metile_v39_r11)));\n } else {\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = static_cast(_metile_v39_r8); }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = static_cast(_metile_v39_r9); }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = static_cast(_metile_v39_r10); }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = static_cast(_metile_v39_r11); }\n }\n if ((_metile_v43_r12) && (_metile_v43_r13) && (_metile_v43_r14) && (_metile_v43_r15) && (long(_off__metile_v44_r13) == long(_off__metile_v44_r12) + 1) && (long(_off__metile_v44_r14) == long(_off__metile_v44_r12) + 2) && (long(_off__metile_v44_r15) == long(_off__metile_v44_r12) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r12) = packed_half4(half4(static_cast(_metile_v39_r12), static_cast(_metile_v39_r13), static_cast(_metile_v39_r14), static_cast(_metile_v39_r15)));\n } else {\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = static_cast(_metile_v39_r12); }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = static_cast(_metile_v39_r13); }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = static_cast(_metile_v39_r14); }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = static_cast(_metile_v39_r15); }\n }\n}", "source_sha256": "69ca6afa69b470e096587fff61d2aae73d540a3d5a9f5d7c7e10d9537062ec50", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 64, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 64, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 16 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 2, "bytes": 8 } ], "double_buffered": false, "vectorized_loads": 8, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 16, "threads": 64, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 8, "grouped_stores": 4 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 546, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 214.625, "control": 207.334, "speedup": 0.9660291205591147 }, "gpu_us": { "candidate": 6.749993190169334, "control": 5.583337042480707, "speedup": 0.8271618778241523 } } }, { "frozen_register4": { "pairs": 543, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 211.958, "control": 208.875, "speedup": 0.9854546655469479 }, "gpu_us": { "candidate": 6.749993190169334, "control": 5.583337042480707, "speedup": 0.8271618778241523 } } }, { "frozen_register4": { "pairs": 576, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 210.97899999999998, "control": 210.1455, "speedup": 0.9960493698424963 }, "gpu_us": { "candidate": 6.749993190169334, "control": 5.583337042480707, "speedup": 0.8271618778241523 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.98243217596635, "round_speedups": [ 0.9660291205591147, 0.9854546655469479, 0.9960493698424963 ], "candidate": 212.51509500741338, "control": 208.78166721382897 }, "gpu_us": { "speedup": 0.8271618778241523, "round_speedups": [ 0.8271618778241523, 0.8271618778241523, 0.8271618778241523 ], "candidate": 6.749993190169335, "control": 5.583337042480708 } } } }, { "name": "float16_256x1009", "dtype": "float16", "batches": 256, "width": 1009, "status": "measured", "variant": { "name": "register32_striped", "elements_per_thread": 32, "layout": "striped" }, "input_sha256": "3fe4b7685e23d624bcb19d6442cc8d72636943e6c185f3b0049a2ac1e0b63d81", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 31;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 32;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 64;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 96;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 128;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 160;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 192;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 224;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n int _metile_register_packed________ = _metile_bounded_thread + 256;\n int _metile_register_index________ = int(_metile_register_packed________);\n int _metile_register_packed_________ = _metile_bounded_thread + 288;\n int _metile_register_index_________ = int(_metile_register_packed_________);\n int _metile_register_packed__________ = _metile_bounded_thread + 320;\n int _metile_register_index__________ = int(_metile_register_packed__________);\n int _metile_register_packed___________ = _metile_bounded_thread + 352;\n int _metile_register_index___________ = int(_metile_register_packed___________);\n int _metile_register_packed____________ = _metile_bounded_thread + 384;\n int _metile_register_index____________ = int(_metile_register_packed____________);\n int _metile_register_packed_____________ = _metile_bounded_thread + 416;\n int _metile_register_index_____________ = int(_metile_register_packed_____________);\n int _metile_register_packed______________ = _metile_bounded_thread + 448;\n int _metile_register_index______________ = int(_metile_register_packed______________);\n int _metile_register_packed_______________ = _metile_bounded_thread + 480;\n int _metile_register_index_______________ = int(_metile_register_packed_______________);\n int _metile_register_packed________________ = _metile_bounded_thread + 512;\n int _metile_register_index________________ = int(_metile_register_packed________________);\n int _metile_register_packed_________________ = _metile_bounded_thread + 544;\n int _metile_register_index_________________ = int(_metile_register_packed_________________);\n int _metile_register_packed__________________ = _metile_bounded_thread + 576;\n int _metile_register_index__________________ = int(_metile_register_packed__________________);\n int _metile_register_packed___________________ = _metile_bounded_thread + 608;\n int _metile_register_index___________________ = int(_metile_register_packed___________________);\n int _metile_register_packed____________________ = _metile_bounded_thread + 640;\n int _metile_register_index____________________ = int(_metile_register_packed____________________);\n int _metile_register_packed_____________________ = _metile_bounded_thread + 672;\n int _metile_register_index_____________________ = int(_metile_register_packed_____________________);\n int _metile_register_packed______________________ = _metile_bounded_thread + 704;\n int _metile_register_index______________________ = int(_metile_register_packed______________________);\n int _metile_register_packed_______________________ = _metile_bounded_thread + 736;\n int _metile_register_index_______________________ = int(_metile_register_packed_______________________);\n int _metile_register_packed________________________ = _metile_bounded_thread + 768;\n int _metile_register_index________________________ = int(_metile_register_packed________________________);\n int _metile_register_packed_________________________ = _metile_bounded_thread + 800;\n int _metile_register_index_________________________ = int(_metile_register_packed_________________________);\n int _metile_register_packed__________________________ = _metile_bounded_thread + 832;\n int _metile_register_index__________________________ = int(_metile_register_packed__________________________);\n int _metile_register_packed___________________________ = _metile_bounded_thread + 864;\n int _metile_register_index___________________________ = int(_metile_register_packed___________________________);\n int _metile_register_packed____________________________ = _metile_bounded_thread + 896;\n int _metile_register_index____________________________ = int(_metile_register_packed____________________________);\n int _metile_register_packed_____________________________ = _metile_bounded_thread + 928;\n int _metile_register_index_____________________________ = int(_metile_register_packed_____________________________);\n int _metile_register_packed______________________________ = _metile_bounded_thread + 960;\n int _metile_register_index______________________________ = int(_metile_register_packed______________________________);\n int _metile_register_packed_______________________________ = _metile_bounded_thread + 992;\n int _metile_register_index_______________________________ = int(_metile_register_packed_______________________________);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v16_r16 = _metile_register_index________________ >= 0;\n bool _metile_v16_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v16_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v16_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v16_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v16_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v16_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v16_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v16_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v16_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v16_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v16_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v16_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v16_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v16_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v16_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v17_r8 = _metile_register_index________ < 1009;\n bool _metile_v17_r9 = _metile_register_index_________ < 1009;\n bool _metile_v17_r10 = _metile_register_index__________ < 1009;\n bool _metile_v17_r11 = _metile_register_index___________ < 1009;\n bool _metile_v17_r12 = _metile_register_index____________ < 1009;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v17_r14 = _metile_register_index______________ < 1009;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v17_r16 = _metile_register_index________________ < 1009;\n bool _metile_v17_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v17_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v17_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v17_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v17_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v17_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v17_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v17_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v17_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v17_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v17_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v17_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v17_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v17_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v17_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n bool _metile_v18_r16 = _metile_v16_r16 & _metile_v17_r16;\n bool _metile_v18_r17 = _metile_v16_r17 & _metile_v17_r17;\n bool _metile_v18_r18 = _metile_v16_r18 & _metile_v17_r18;\n bool _metile_v18_r19 = _metile_v16_r19 & _metile_v17_r19;\n bool _metile_v18_r20 = _metile_v16_r20 & _metile_v17_r20;\n bool _metile_v18_r21 = _metile_v16_r21 & _metile_v17_r21;\n bool _metile_v18_r22 = _metile_v16_r22 & _metile_v17_r22;\n bool _metile_v18_r23 = _metile_v16_r23 & _metile_v17_r23;\n bool _metile_v18_r24 = _metile_v16_r24 & _metile_v17_r24;\n bool _metile_v18_r25 = _metile_v16_r25 & _metile_v17_r25;\n bool _metile_v18_r26 = _metile_v16_r26 & _metile_v17_r26;\n bool _metile_v18_r27 = _metile_v16_r27 & _metile_v17_r27;\n bool _metile_v18_r28 = _metile_v16_r28 & _metile_v17_r28;\n bool _metile_v18_r29 = _metile_v16_r29 & _metile_v17_r29;\n bool _metile_v18_r30 = _metile_v16_r30 & _metile_v17_r30;\n bool _metile_v18_r31 = _metile_v16_r31 & _metile_v17_r31;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n int _off__metile_v19_r16 = v2 + _metile_register_index________________;\n int _off__metile_v19_r17 = v2 + _metile_register_index_________________;\n int _off__metile_v19_r18 = v2 + _metile_register_index__________________;\n int _off__metile_v19_r19 = v2 + _metile_register_index___________________;\n int _off__metile_v19_r20 = v2 + _metile_register_index____________________;\n int _off__metile_v19_r21 = v2 + _metile_register_index_____________________;\n int _off__metile_v19_r22 = v2 + _metile_register_index______________________;\n int _off__metile_v19_r23 = v2 + _metile_register_index_______________________;\n int _off__metile_v19_r24 = v2 + _metile_register_index________________________;\n int _off__metile_v19_r25 = v2 + _metile_register_index_________________________;\n int _off__metile_v19_r26 = v2 + _metile_register_index__________________________;\n int _off__metile_v19_r27 = v2 + _metile_register_index___________________________;\n int _off__metile_v19_r28 = v2 + _metile_register_index____________________________;\n int _off__metile_v19_r29 = v2 + _metile_register_index_____________________________;\n int _off__metile_v19_r30 = v2 + _metile_register_index______________________________;\n int _off__metile_v19_r31 = v2 + _metile_register_index_______________________________;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n half _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n half _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n half _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n half _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n half _metile_v20_r8 = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n half _metile_v20_r9 = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n half _metile_v20_r10 = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n half _metile_v20_r11 = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n half _metile_v20_r12 = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n half _metile_v20_r13 = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n half _metile_v20_r14 = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n half _metile_v20_r15 = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n half _metile_v20_r16 = _metile_v18_r16 ? X[_off__metile_v19_r16] : static_cast(0);\n half _metile_v20_r17 = _metile_v18_r17 ? X[_off__metile_v19_r17] : static_cast(0);\n half _metile_v20_r18 = _metile_v18_r18 ? X[_off__metile_v19_r18] : static_cast(0);\n half _metile_v20_r19 = _metile_v18_r19 ? X[_off__metile_v19_r19] : static_cast(0);\n half _metile_v20_r20 = _metile_v18_r20 ? X[_off__metile_v19_r20] : static_cast(0);\n half _metile_v20_r21 = _metile_v18_r21 ? X[_off__metile_v19_r21] : static_cast(0);\n half _metile_v20_r22 = _metile_v18_r22 ? X[_off__metile_v19_r22] : static_cast(0);\n half _metile_v20_r23 = _metile_v18_r23 ? X[_off__metile_v19_r23] : static_cast(0);\n half _metile_v20_r24 = _metile_v18_r24 ? X[_off__metile_v19_r24] : static_cast(0);\n half _metile_v20_r25 = _metile_v18_r25 ? X[_off__metile_v19_r25] : static_cast(0);\n half _metile_v20_r26 = _metile_v18_r26 ? X[_off__metile_v19_r26] : static_cast(0);\n half _metile_v20_r27 = _metile_v18_r27 ? X[_off__metile_v19_r27] : static_cast(0);\n half _metile_v20_r28 = _metile_v18_r28 ? X[_off__metile_v19_r28] : static_cast(0);\n half _metile_v20_r29 = _metile_v18_r29 ? X[_off__metile_v19_r29] : static_cast(0);\n half _metile_v20_r30 = _metile_v18_r30 ? X[_off__metile_v19_r30] : static_cast(0);\n half _metile_v20_r31 = _metile_v18_r31 ? X[_off__metile_v19_r31] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v21_r16 = static_cast(_metile_v20_r16);\n float _metile_v21_r17 = static_cast(_metile_v20_r17);\n float _metile_v21_r18 = static_cast(_metile_v20_r18);\n float _metile_v21_r19 = static_cast(_metile_v20_r19);\n float _metile_v21_r20 = static_cast(_metile_v20_r20);\n float _metile_v21_r21 = static_cast(_metile_v20_r21);\n float _metile_v21_r22 = static_cast(_metile_v20_r22);\n float _metile_v21_r23 = static_cast(_metile_v20_r23);\n float _metile_v21_r24 = static_cast(_metile_v20_r24);\n float _metile_v21_r25 = static_cast(_metile_v20_r25);\n float _metile_v21_r26 = static_cast(_metile_v20_r26);\n float _metile_v21_r27 = static_cast(_metile_v20_r27);\n float _metile_v21_r28 = static_cast(_metile_v20_r28);\n float _metile_v21_r29 = static_cast(_metile_v20_r29);\n float _metile_v21_r30 = static_cast(_metile_v20_r30);\n float _metile_v21_r31 = static_cast(_metile_v20_r31);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_v22_r16 = _metile_v21_r16 * _metile_v21_r16;\n float _metile_v22_r17 = _metile_v21_r17 * _metile_v21_r17;\n float _metile_v22_r18 = _metile_v21_r18 * _metile_v21_r18;\n float _metile_v22_r19 = _metile_v21_r19 * _metile_v21_r19;\n float _metile_v22_r20 = _metile_v21_r20 * _metile_v21_r20;\n float _metile_v22_r21 = _metile_v21_r21 * _metile_v21_r21;\n float _metile_v22_r22 = _metile_v21_r22 * _metile_v21_r22;\n float _metile_v22_r23 = _metile_v21_r23 * _metile_v21_r23;\n float _metile_v22_r24 = _metile_v21_r24 * _metile_v21_r24;\n float _metile_v22_r25 = _metile_v21_r25 * _metile_v21_r25;\n float _metile_v22_r26 = _metile_v21_r26 * _metile_v21_r26;\n float _metile_v22_r27 = _metile_v21_r27 * _metile_v21_r27;\n float _metile_v22_r28 = _metile_v21_r28 * _metile_v21_r28;\n float _metile_v22_r29 = _metile_v21_r29 * _metile_v21_r29;\n float _metile_v22_r30 = _metile_v21_r30 * _metile_v21_r30;\n float _metile_v22_r31 = _metile_v21_r31 * _metile_v21_r31;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_v22_r16 + _metile_v22_r17;\n float _metile_register_sum_________ = _metile_v22_r18 + _metile_v22_r19;\n float _metile_register_sum__________ = _metile_v22_r20 + _metile_v22_r21;\n float _metile_register_sum___________ = _metile_v22_r22 + _metile_v22_r23;\n float _metile_register_sum____________ = _metile_v22_r24 + _metile_v22_r25;\n float _metile_register_sum_____________ = _metile_v22_r26 + _metile_v22_r27;\n float _metile_register_sum______________ = _metile_v22_r28 + _metile_v22_r29;\n float _metile_register_sum_______________ = _metile_v22_r30 + _metile_v22_r31;\n float _metile_register_sum________________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________________ = _metile_register_sum____________ + _metile_register_sum_____________;\n float _metile_register_sum_______________________ = _metile_register_sum______________ + _metile_register_sum_______________;\n float _metile_register_sum________________________ = _metile_register_sum________________ + _metile_register_sum_________________;\n float _metile_register_sum_________________________ = _metile_register_sum__________________ + _metile_register_sum___________________;\n float _metile_register_sum__________________________ = _metile_register_sum____________________ + _metile_register_sum_____________________;\n float _metile_register_sum___________________________ = _metile_register_sum______________________ + _metile_register_sum_______________________;\n float _metile_register_sum____________________________ = _metile_register_sum________________________ + _metile_register_sum_________________________;\n float _metile_register_sum_____________________________ = _metile_register_sum__________________________ + _metile_register_sum___________________________;\n float _metile_register_sum______________________________ = _metile_register_sum____________________________ + _metile_register_sum_____________________________;\n float v23 = simd_sum(_metile_register_sum______________________________);\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v32_r16 = _metile_register_index________________ >= 0;\n bool _metile_v32_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v32_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v32_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v32_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v32_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v32_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v32_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v32_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v32_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v32_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v32_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v32_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v32_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v32_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v32_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v33_r8 = _metile_register_index________ < 1009;\n bool _metile_v33_r9 = _metile_register_index_________ < 1009;\n bool _metile_v33_r10 = _metile_register_index__________ < 1009;\n bool _metile_v33_r11 = _metile_register_index___________ < 1009;\n bool _metile_v33_r12 = _metile_register_index____________ < 1009;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v33_r14 = _metile_register_index______________ < 1009;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v33_r16 = _metile_register_index________________ < 1009;\n bool _metile_v33_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v33_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v33_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v33_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v33_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v33_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v33_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v33_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v33_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v33_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v33_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v33_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v33_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v33_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v33_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n bool _metile_v34_r16 = _metile_v32_r16 & _metile_v33_r16;\n bool _metile_v34_r17 = _metile_v32_r17 & _metile_v33_r17;\n bool _metile_v34_r18 = _metile_v32_r18 & _metile_v33_r18;\n bool _metile_v34_r19 = _metile_v32_r19 & _metile_v33_r19;\n bool _metile_v34_r20 = _metile_v32_r20 & _metile_v33_r20;\n bool _metile_v34_r21 = _metile_v32_r21 & _metile_v33_r21;\n bool _metile_v34_r22 = _metile_v32_r22 & _metile_v33_r22;\n bool _metile_v34_r23 = _metile_v32_r23 & _metile_v33_r23;\n bool _metile_v34_r24 = _metile_v32_r24 & _metile_v33_r24;\n bool _metile_v34_r25 = _metile_v32_r25 & _metile_v33_r25;\n bool _metile_v34_r26 = _metile_v32_r26 & _metile_v33_r26;\n bool _metile_v34_r27 = _metile_v32_r27 & _metile_v33_r27;\n bool _metile_v34_r28 = _metile_v32_r28 & _metile_v33_r28;\n bool _metile_v34_r29 = _metile_v32_r29 & _metile_v33_r29;\n bool _metile_v34_r30 = _metile_v32_r30 & _metile_v33_r30;\n bool _metile_v34_r31 = _metile_v32_r31 & _metile_v33_r31;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n half _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n half _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n half _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n half _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n half _metile_v36_r8 = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n half _metile_v36_r9 = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n half _metile_v36_r10 = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n half _metile_v36_r11 = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n half _metile_v36_r12 = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n half _metile_v36_r13 = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n half _metile_v36_r14 = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n half _metile_v36_r15 = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n half _metile_v36_r16 = _metile_v34_r16 ? W[_metile_register_index________________] : static_cast(0);\n half _metile_v36_r17 = _metile_v34_r17 ? W[_metile_register_index_________________] : static_cast(0);\n half _metile_v36_r18 = _metile_v34_r18 ? W[_metile_register_index__________________] : static_cast(0);\n half _metile_v36_r19 = _metile_v34_r19 ? W[_metile_register_index___________________] : static_cast(0);\n half _metile_v36_r20 = _metile_v34_r20 ? W[_metile_register_index____________________] : static_cast(0);\n half _metile_v36_r21 = _metile_v34_r21 ? W[_metile_register_index_____________________] : static_cast(0);\n half _metile_v36_r22 = _metile_v34_r22 ? W[_metile_register_index______________________] : static_cast(0);\n half _metile_v36_r23 = _metile_v34_r23 ? W[_metile_register_index_______________________] : static_cast(0);\n half _metile_v36_r24 = _metile_v34_r24 ? W[_metile_register_index________________________] : static_cast(0);\n half _metile_v36_r25 = _metile_v34_r25 ? W[_metile_register_index_________________________] : static_cast(0);\n half _metile_v36_r26 = _metile_v34_r26 ? W[_metile_register_index__________________________] : static_cast(0);\n half _metile_v36_r27 = _metile_v34_r27 ? W[_metile_register_index___________________________] : static_cast(0);\n half _metile_v36_r28 = _metile_v34_r28 ? W[_metile_register_index____________________________] : static_cast(0);\n half _metile_v36_r29 = _metile_v34_r29 ? W[_metile_register_index_____________________________] : static_cast(0);\n half _metile_v36_r30 = _metile_v34_r30 ? W[_metile_register_index______________________________] : static_cast(0);\n half _metile_v36_r31 = _metile_v34_r31 ? W[_metile_register_index_______________________________] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v37_r16 = static_cast(_metile_v36_r16);\n float _metile_v37_r17 = static_cast(_metile_v36_r17);\n float _metile_v37_r18 = static_cast(_metile_v36_r18);\n float _metile_v37_r19 = static_cast(_metile_v36_r19);\n float _metile_v37_r20 = static_cast(_metile_v36_r20);\n float _metile_v37_r21 = static_cast(_metile_v36_r21);\n float _metile_v37_r22 = static_cast(_metile_v36_r22);\n float _metile_v37_r23 = static_cast(_metile_v36_r23);\n float _metile_v37_r24 = static_cast(_metile_v36_r24);\n float _metile_v37_r25 = static_cast(_metile_v36_r25);\n float _metile_v37_r26 = static_cast(_metile_v36_r26);\n float _metile_v37_r27 = static_cast(_metile_v36_r27);\n float _metile_v37_r28 = static_cast(_metile_v36_r28);\n float _metile_v37_r29 = static_cast(_metile_v36_r29);\n float _metile_v37_r30 = static_cast(_metile_v36_r30);\n float _metile_v37_r31 = static_cast(_metile_v36_r31);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v38_r16 = _metile_v21_r16 * v29;\n float _metile_v38_r17 = _metile_v21_r17 * v29;\n float _metile_v38_r18 = _metile_v21_r18 * v29;\n float _metile_v38_r19 = _metile_v21_r19 * v29;\n float _metile_v38_r20 = _metile_v21_r20 * v29;\n float _metile_v38_r21 = _metile_v21_r21 * v29;\n float _metile_v38_r22 = _metile_v21_r22 * v29;\n float _metile_v38_r23 = _metile_v21_r23 * v29;\n float _metile_v38_r24 = _metile_v21_r24 * v29;\n float _metile_v38_r25 = _metile_v21_r25 * v29;\n float _metile_v38_r26 = _metile_v21_r26 * v29;\n float _metile_v38_r27 = _metile_v21_r27 * v29;\n float _metile_v38_r28 = _metile_v21_r28 * v29;\n float _metile_v38_r29 = _metile_v21_r29 * v29;\n float _metile_v38_r30 = _metile_v21_r30 * v29;\n float _metile_v38_r31 = _metile_v21_r31 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n float _metile_v39_r16 = _metile_v38_r16 * _metile_v37_r16;\n float _metile_v39_r17 = _metile_v38_r17 * _metile_v37_r17;\n float _metile_v39_r18 = _metile_v38_r18 * _metile_v37_r18;\n float _metile_v39_r19 = _metile_v38_r19 * _metile_v37_r19;\n float _metile_v39_r20 = _metile_v38_r20 * _metile_v37_r20;\n float _metile_v39_r21 = _metile_v38_r21 * _metile_v37_r21;\n float _metile_v39_r22 = _metile_v38_r22 * _metile_v37_r22;\n float _metile_v39_r23 = _metile_v38_r23 * _metile_v37_r23;\n float _metile_v39_r24 = _metile_v38_r24 * _metile_v37_r24;\n float _metile_v39_r25 = _metile_v38_r25 * _metile_v37_r25;\n float _metile_v39_r26 = _metile_v38_r26 * _metile_v37_r26;\n float _metile_v39_r27 = _metile_v38_r27 * _metile_v37_r27;\n float _metile_v39_r28 = _metile_v38_r28 * _metile_v37_r28;\n float _metile_v39_r29 = _metile_v38_r29 * _metile_v37_r29;\n float _metile_v39_r30 = _metile_v38_r30 * _metile_v37_r30;\n float _metile_v39_r31 = _metile_v38_r31 * _metile_v37_r31;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v41_r16 = _metile_register_index________________ >= 0;\n bool _metile_v41_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v41_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v41_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v41_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v41_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v41_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v41_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v41_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v41_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v41_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v41_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v41_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v41_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v41_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v41_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v42_r8 = _metile_register_index________ < 1009;\n bool _metile_v42_r9 = _metile_register_index_________ < 1009;\n bool _metile_v42_r10 = _metile_register_index__________ < 1009;\n bool _metile_v42_r11 = _metile_register_index___________ < 1009;\n bool _metile_v42_r12 = _metile_register_index____________ < 1009;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v42_r14 = _metile_register_index______________ < 1009;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v42_r16 = _metile_register_index________________ < 1009;\n bool _metile_v42_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v42_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v42_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v42_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v42_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v42_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v42_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v42_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v42_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v42_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v42_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v42_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v42_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v42_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v42_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n bool _metile_v43_r16 = _metile_v41_r16 & _metile_v42_r16;\n bool _metile_v43_r17 = _metile_v41_r17 & _metile_v42_r17;\n bool _metile_v43_r18 = _metile_v41_r18 & _metile_v42_r18;\n bool _metile_v43_r19 = _metile_v41_r19 & _metile_v42_r19;\n bool _metile_v43_r20 = _metile_v41_r20 & _metile_v42_r20;\n bool _metile_v43_r21 = _metile_v41_r21 & _metile_v42_r21;\n bool _metile_v43_r22 = _metile_v41_r22 & _metile_v42_r22;\n bool _metile_v43_r23 = _metile_v41_r23 & _metile_v42_r23;\n bool _metile_v43_r24 = _metile_v41_r24 & _metile_v42_r24;\n bool _metile_v43_r25 = _metile_v41_r25 & _metile_v42_r25;\n bool _metile_v43_r26 = _metile_v41_r26 & _metile_v42_r26;\n bool _metile_v43_r27 = _metile_v41_r27 & _metile_v42_r27;\n bool _metile_v43_r28 = _metile_v41_r28 & _metile_v42_r28;\n bool _metile_v43_r29 = _metile_v41_r29 & _metile_v42_r29;\n bool _metile_v43_r30 = _metile_v41_r30 & _metile_v42_r30;\n bool _metile_v43_r31 = _metile_v41_r31 & _metile_v42_r31;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n int _off__metile_v44_r16 = v9 + _metile_register_index________________;\n int _off__metile_v44_r17 = v9 + _metile_register_index_________________;\n int _off__metile_v44_r18 = v9 + _metile_register_index__________________;\n int _off__metile_v44_r19 = v9 + _metile_register_index___________________;\n int _off__metile_v44_r20 = v9 + _metile_register_index____________________;\n int _off__metile_v44_r21 = v9 + _metile_register_index_____________________;\n int _off__metile_v44_r22 = v9 + _metile_register_index______________________;\n int _off__metile_v44_r23 = v9 + _metile_register_index_______________________;\n int _off__metile_v44_r24 = v9 + _metile_register_index________________________;\n int _off__metile_v44_r25 = v9 + _metile_register_index_________________________;\n int _off__metile_v44_r26 = v9 + _metile_register_index__________________________;\n int _off__metile_v44_r27 = v9 + _metile_register_index___________________________;\n int _off__metile_v44_r28 = v9 + _metile_register_index____________________________;\n int _off__metile_v44_r29 = v9 + _metile_register_index_____________________________;\n int _off__metile_v44_r30 = v9 + _metile_register_index______________________________;\n int _off__metile_v44_r31 = v9 + _metile_register_index_______________________________;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = _metile_v39_r8; }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = _metile_v39_r9; }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = _metile_v39_r10; }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = _metile_v39_r11; }\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = _metile_v39_r12; }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = _metile_v39_r13; }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = _metile_v39_r14; }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = _metile_v39_r15; }\n if (_metile_v43_r16) { Out[_off__metile_v44_r16] = _metile_v39_r16; }\n if (_metile_v43_r17) { Out[_off__metile_v44_r17] = _metile_v39_r17; }\n if (_metile_v43_r18) { Out[_off__metile_v44_r18] = _metile_v39_r18; }\n if (_metile_v43_r19) { Out[_off__metile_v44_r19] = _metile_v39_r19; }\n if (_metile_v43_r20) { Out[_off__metile_v44_r20] = _metile_v39_r20; }\n if (_metile_v43_r21) { Out[_off__metile_v44_r21] = _metile_v39_r21; }\n if (_metile_v43_r22) { Out[_off__metile_v44_r22] = _metile_v39_r22; }\n if (_metile_v43_r23) { Out[_off__metile_v44_r23] = _metile_v39_r23; }\n if (_metile_v43_r24) { Out[_off__metile_v44_r24] = _metile_v39_r24; }\n if (_metile_v43_r25) { Out[_off__metile_v44_r25] = _metile_v39_r25; }\n if (_metile_v43_r26) { Out[_off__metile_v44_r26] = _metile_v39_r26; }\n if (_metile_v43_r27) { Out[_off__metile_v44_r27] = _metile_v39_r27; }\n if (_metile_v43_r28) { Out[_off__metile_v44_r28] = _metile_v39_r28; }\n if (_metile_v43_r29) { Out[_off__metile_v44_r29] = _metile_v39_r29; }\n if (_metile_v43_r30) { Out[_off__metile_v44_r30] = _metile_v39_r30; }\n if (_metile_v43_r31) { Out[_off__metile_v44_r31] = _metile_v39_r31; }\n}", "source_sha256": "d5c41916120b99fb67bf8cd3981daa7226ce2516e5cb14fd030515e31ba811e0", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 32, 1, 1 ], "is_gemm": false, "prefer_ordered": false, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 32, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 32 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 32, "threads": 32, "scratch": null, "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 568, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 207.89600000000002, "control": 210.458, "speedup": 1.0123234694270211 }, "gpu_us": { "candidate": 5.624955520033836, "control": 5.624955520033836, "speedup": 1.0 } } }, { "frozen_register4": { "pairs": 579, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 209.75, "control": 208.042, "speedup": 0.9918569725864124 }, "gpu_us": { "candidate": 5.583337042480707, "control": 5.583337042480707, "speedup": 1.0 } } }, { "frozen_register4": { "pairs": 580, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 208.5, "control": 208.25, "speedup": 0.9988009592326139 }, "gpu_us": { "candidate": 5.583337042480707, "control": 5.624955520033836, "speedup": 1.007454050729246 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0009578018894607, "round_speedups": [ 1.0123234694270211, 0.9918569725864124, 0.9988009592326139 ], "candidate": 208.7139067701654, "control": 208.91381334442664 }, "gpu_us": { "speedup": 1.002478535363539, "round_speedups": [ 1.0, 1.0, 1.007454050729246 ], "candidate": 5.597175540787054, "control": 5.61104833830083 } } } }, { "name": "float16_256x1009", "dtype": "float16", "batches": 256, "width": 1009, "status": "measured", "variant": { "name": "register32_blocked4", "elements_per_thread": 32, "layout": "blocked4" }, "input_sha256": "3fe4b7685e23d624bcb19d6442cc8d72636943e6c185f3b0049a2ac1e0b63d81", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 31;\n int _metile_register_index = int((((_metile_bounded_thread >> 5) & 1u) << 0) | (((_metile_bounded_thread >> 6) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 7) & 1u) << 7) | (((_metile_bounded_thread >> 8) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 32;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 5) & 1u) << 0) | (((_metile_register_packed_ >> 6) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 7) & 1u) << 7) | (((_metile_register_packed_ >> 8) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 64;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 5) & 1u) << 0) | (((_metile_register_packed__ >> 6) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 7) & 1u) << 7) | (((_metile_register_packed__ >> 8) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 96;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 5) & 1u) << 0) | (((_metile_register_packed___ >> 6) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 7) & 1u) << 7) | (((_metile_register_packed___ >> 8) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 128;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 5) & 1u) << 0) | (((_metile_register_packed____ >> 6) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 7) & 1u) << 7) | (((_metile_register_packed____ >> 8) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 160;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 5) & 1u) << 0) | (((_metile_register_packed_____ >> 6) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 7) & 1u) << 7) | (((_metile_register_packed_____ >> 8) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 192;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 5) & 1u) << 0) | (((_metile_register_packed______ >> 6) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 7) & 1u) << 7) | (((_metile_register_packed______ >> 8) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 224;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 5) & 1u) << 0) | (((_metile_register_packed_______ >> 6) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 7) & 1u) << 7) | (((_metile_register_packed_______ >> 8) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n int _metile_register_packed________ = _metile_bounded_thread + 256;\n int _metile_register_index________ = int((((_metile_register_packed________ >> 5) & 1u) << 0) | (((_metile_register_packed________ >> 6) & 1u) << 1) | (((_metile_register_packed________ >> 0) & 1u) << 2) | (((_metile_register_packed________ >> 1) & 1u) << 3) | (((_metile_register_packed________ >> 2) & 1u) << 4) | (((_metile_register_packed________ >> 3) & 1u) << 5) | (((_metile_register_packed________ >> 4) & 1u) << 6) | (((_metile_register_packed________ >> 7) & 1u) << 7) | (((_metile_register_packed________ >> 8) & 1u) << 8) | (((_metile_register_packed________ >> 9) & 1u) << 9));\n int _metile_register_packed_________ = _metile_bounded_thread + 288;\n int _metile_register_index_________ = int((((_metile_register_packed_________ >> 5) & 1u) << 0) | (((_metile_register_packed_________ >> 6) & 1u) << 1) | (((_metile_register_packed_________ >> 0) & 1u) << 2) | (((_metile_register_packed_________ >> 1) & 1u) << 3) | (((_metile_register_packed_________ >> 2) & 1u) << 4) | (((_metile_register_packed_________ >> 3) & 1u) << 5) | (((_metile_register_packed_________ >> 4) & 1u) << 6) | (((_metile_register_packed_________ >> 7) & 1u) << 7) | (((_metile_register_packed_________ >> 8) & 1u) << 8) | (((_metile_register_packed_________ >> 9) & 1u) << 9));\n int _metile_register_packed__________ = _metile_bounded_thread + 320;\n int _metile_register_index__________ = int((((_metile_register_packed__________ >> 5) & 1u) << 0) | (((_metile_register_packed__________ >> 6) & 1u) << 1) | (((_metile_register_packed__________ >> 0) & 1u) << 2) | (((_metile_register_packed__________ >> 1) & 1u) << 3) | (((_metile_register_packed__________ >> 2) & 1u) << 4) | (((_metile_register_packed__________ >> 3) & 1u) << 5) | (((_metile_register_packed__________ >> 4) & 1u) << 6) | (((_metile_register_packed__________ >> 7) & 1u) << 7) | (((_metile_register_packed__________ >> 8) & 1u) << 8) | (((_metile_register_packed__________ >> 9) & 1u) << 9));\n int _metile_register_packed___________ = _metile_bounded_thread + 352;\n int _metile_register_index___________ = int((((_metile_register_packed___________ >> 5) & 1u) << 0) | (((_metile_register_packed___________ >> 6) & 1u) << 1) | (((_metile_register_packed___________ >> 0) & 1u) << 2) | (((_metile_register_packed___________ >> 1) & 1u) << 3) | (((_metile_register_packed___________ >> 2) & 1u) << 4) | (((_metile_register_packed___________ >> 3) & 1u) << 5) | (((_metile_register_packed___________ >> 4) & 1u) << 6) | (((_metile_register_packed___________ >> 7) & 1u) << 7) | (((_metile_register_packed___________ >> 8) & 1u) << 8) | (((_metile_register_packed___________ >> 9) & 1u) << 9));\n int _metile_register_packed____________ = _metile_bounded_thread + 384;\n int _metile_register_index____________ = int((((_metile_register_packed____________ >> 5) & 1u) << 0) | (((_metile_register_packed____________ >> 6) & 1u) << 1) | (((_metile_register_packed____________ >> 0) & 1u) << 2) | (((_metile_register_packed____________ >> 1) & 1u) << 3) | (((_metile_register_packed____________ >> 2) & 1u) << 4) | (((_metile_register_packed____________ >> 3) & 1u) << 5) | (((_metile_register_packed____________ >> 4) & 1u) << 6) | (((_metile_register_packed____________ >> 7) & 1u) << 7) | (((_metile_register_packed____________ >> 8) & 1u) << 8) | (((_metile_register_packed____________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________ = _metile_bounded_thread + 416;\n int _metile_register_index_____________ = int((((_metile_register_packed_____________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________ >> 9) & 1u) << 9));\n int _metile_register_packed______________ = _metile_bounded_thread + 448;\n int _metile_register_index______________ = int((((_metile_register_packed______________ >> 5) & 1u) << 0) | (((_metile_register_packed______________ >> 6) & 1u) << 1) | (((_metile_register_packed______________ >> 0) & 1u) << 2) | (((_metile_register_packed______________ >> 1) & 1u) << 3) | (((_metile_register_packed______________ >> 2) & 1u) << 4) | (((_metile_register_packed______________ >> 3) & 1u) << 5) | (((_metile_register_packed______________ >> 4) & 1u) << 6) | (((_metile_register_packed______________ >> 7) & 1u) << 7) | (((_metile_register_packed______________ >> 8) & 1u) << 8) | (((_metile_register_packed______________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________ = _metile_bounded_thread + 480;\n int _metile_register_index_______________ = int((((_metile_register_packed_______________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________ >> 9) & 1u) << 9));\n int _metile_register_packed________________ = _metile_bounded_thread + 512;\n int _metile_register_index________________ = int((((_metile_register_packed________________ >> 5) & 1u) << 0) | (((_metile_register_packed________________ >> 6) & 1u) << 1) | (((_metile_register_packed________________ >> 0) & 1u) << 2) | (((_metile_register_packed________________ >> 1) & 1u) << 3) | (((_metile_register_packed________________ >> 2) & 1u) << 4) | (((_metile_register_packed________________ >> 3) & 1u) << 5) | (((_metile_register_packed________________ >> 4) & 1u) << 6) | (((_metile_register_packed________________ >> 7) & 1u) << 7) | (((_metile_register_packed________________ >> 8) & 1u) << 8) | (((_metile_register_packed________________ >> 9) & 1u) << 9));\n int _metile_register_packed_________________ = _metile_bounded_thread + 544;\n int _metile_register_index_________________ = int((((_metile_register_packed_________________ >> 5) & 1u) << 0) | (((_metile_register_packed_________________ >> 6) & 1u) << 1) | (((_metile_register_packed_________________ >> 0) & 1u) << 2) | (((_metile_register_packed_________________ >> 1) & 1u) << 3) | (((_metile_register_packed_________________ >> 2) & 1u) << 4) | (((_metile_register_packed_________________ >> 3) & 1u) << 5) | (((_metile_register_packed_________________ >> 4) & 1u) << 6) | (((_metile_register_packed_________________ >> 7) & 1u) << 7) | (((_metile_register_packed_________________ >> 8) & 1u) << 8) | (((_metile_register_packed_________________ >> 9) & 1u) << 9));\n int _metile_register_packed__________________ = _metile_bounded_thread + 576;\n int _metile_register_index__________________ = int((((_metile_register_packed__________________ >> 5) & 1u) << 0) | (((_metile_register_packed__________________ >> 6) & 1u) << 1) | (((_metile_register_packed__________________ >> 0) & 1u) << 2) | (((_metile_register_packed__________________ >> 1) & 1u) << 3) | (((_metile_register_packed__________________ >> 2) & 1u) << 4) | (((_metile_register_packed__________________ >> 3) & 1u) << 5) | (((_metile_register_packed__________________ >> 4) & 1u) << 6) | (((_metile_register_packed__________________ >> 7) & 1u) << 7) | (((_metile_register_packed__________________ >> 8) & 1u) << 8) | (((_metile_register_packed__________________ >> 9) & 1u) << 9));\n int _metile_register_packed___________________ = _metile_bounded_thread + 608;\n int _metile_register_index___________________ = int((((_metile_register_packed___________________ >> 5) & 1u) << 0) | (((_metile_register_packed___________________ >> 6) & 1u) << 1) | (((_metile_register_packed___________________ >> 0) & 1u) << 2) | (((_metile_register_packed___________________ >> 1) & 1u) << 3) | (((_metile_register_packed___________________ >> 2) & 1u) << 4) | (((_metile_register_packed___________________ >> 3) & 1u) << 5) | (((_metile_register_packed___________________ >> 4) & 1u) << 6) | (((_metile_register_packed___________________ >> 7) & 1u) << 7) | (((_metile_register_packed___________________ >> 8) & 1u) << 8) | (((_metile_register_packed___________________ >> 9) & 1u) << 9));\n int _metile_register_packed____________________ = _metile_bounded_thread + 640;\n int _metile_register_index____________________ = int((((_metile_register_packed____________________ >> 5) & 1u) << 0) | (((_metile_register_packed____________________ >> 6) & 1u) << 1) | (((_metile_register_packed____________________ >> 0) & 1u) << 2) | (((_metile_register_packed____________________ >> 1) & 1u) << 3) | (((_metile_register_packed____________________ >> 2) & 1u) << 4) | (((_metile_register_packed____________________ >> 3) & 1u) << 5) | (((_metile_register_packed____________________ >> 4) & 1u) << 6) | (((_metile_register_packed____________________ >> 7) & 1u) << 7) | (((_metile_register_packed____________________ >> 8) & 1u) << 8) | (((_metile_register_packed____________________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________________ = _metile_bounded_thread + 672;\n int _metile_register_index_____________________ = int((((_metile_register_packed_____________________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________________ >> 9) & 1u) << 9));\n int _metile_register_packed______________________ = _metile_bounded_thread + 704;\n int _metile_register_index______________________ = int((((_metile_register_packed______________________ >> 5) & 1u) << 0) | (((_metile_register_packed______________________ >> 6) & 1u) << 1) | (((_metile_register_packed______________________ >> 0) & 1u) << 2) | (((_metile_register_packed______________________ >> 1) & 1u) << 3) | (((_metile_register_packed______________________ >> 2) & 1u) << 4) | (((_metile_register_packed______________________ >> 3) & 1u) << 5) | (((_metile_register_packed______________________ >> 4) & 1u) << 6) | (((_metile_register_packed______________________ >> 7) & 1u) << 7) | (((_metile_register_packed______________________ >> 8) & 1u) << 8) | (((_metile_register_packed______________________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________________ = _metile_bounded_thread + 736;\n int _metile_register_index_______________________ = int((((_metile_register_packed_______________________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________________ >> 9) & 1u) << 9));\n int _metile_register_packed________________________ = _metile_bounded_thread + 768;\n int _metile_register_index________________________ = int((((_metile_register_packed________________________ >> 5) & 1u) << 0) | (((_metile_register_packed________________________ >> 6) & 1u) << 1) | (((_metile_register_packed________________________ >> 0) & 1u) << 2) | (((_metile_register_packed________________________ >> 1) & 1u) << 3) | (((_metile_register_packed________________________ >> 2) & 1u) << 4) | (((_metile_register_packed________________________ >> 3) & 1u) << 5) | (((_metile_register_packed________________________ >> 4) & 1u) << 6) | (((_metile_register_packed________________________ >> 7) & 1u) << 7) | (((_metile_register_packed________________________ >> 8) & 1u) << 8) | (((_metile_register_packed________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_________________________ = _metile_bounded_thread + 800;\n int _metile_register_index_________________________ = int((((_metile_register_packed_________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_________________________ >> 9) & 1u) << 9));\n int _metile_register_packed__________________________ = _metile_bounded_thread + 832;\n int _metile_register_index__________________________ = int((((_metile_register_packed__________________________ >> 5) & 1u) << 0) | (((_metile_register_packed__________________________ >> 6) & 1u) << 1) | (((_metile_register_packed__________________________ >> 0) & 1u) << 2) | (((_metile_register_packed__________________________ >> 1) & 1u) << 3) | (((_metile_register_packed__________________________ >> 2) & 1u) << 4) | (((_metile_register_packed__________________________ >> 3) & 1u) << 5) | (((_metile_register_packed__________________________ >> 4) & 1u) << 6) | (((_metile_register_packed__________________________ >> 7) & 1u) << 7) | (((_metile_register_packed__________________________ >> 8) & 1u) << 8) | (((_metile_register_packed__________________________ >> 9) & 1u) << 9));\n int _metile_register_packed___________________________ = _metile_bounded_thread + 864;\n int _metile_register_index___________________________ = int((((_metile_register_packed___________________________ >> 5) & 1u) << 0) | (((_metile_register_packed___________________________ >> 6) & 1u) << 1) | (((_metile_register_packed___________________________ >> 0) & 1u) << 2) | (((_metile_register_packed___________________________ >> 1) & 1u) << 3) | (((_metile_register_packed___________________________ >> 2) & 1u) << 4) | (((_metile_register_packed___________________________ >> 3) & 1u) << 5) | (((_metile_register_packed___________________________ >> 4) & 1u) << 6) | (((_metile_register_packed___________________________ >> 7) & 1u) << 7) | (((_metile_register_packed___________________________ >> 8) & 1u) << 8) | (((_metile_register_packed___________________________ >> 9) & 1u) << 9));\n int _metile_register_packed____________________________ = _metile_bounded_thread + 896;\n int _metile_register_index____________________________ = int((((_metile_register_packed____________________________ >> 5) & 1u) << 0) | (((_metile_register_packed____________________________ >> 6) & 1u) << 1) | (((_metile_register_packed____________________________ >> 0) & 1u) << 2) | (((_metile_register_packed____________________________ >> 1) & 1u) << 3) | (((_metile_register_packed____________________________ >> 2) & 1u) << 4) | (((_metile_register_packed____________________________ >> 3) & 1u) << 5) | (((_metile_register_packed____________________________ >> 4) & 1u) << 6) | (((_metile_register_packed____________________________ >> 7) & 1u) << 7) | (((_metile_register_packed____________________________ >> 8) & 1u) << 8) | (((_metile_register_packed____________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________________________ = _metile_bounded_thread + 928;\n int _metile_register_index_____________________________ = int((((_metile_register_packed_____________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________________________ >> 9) & 1u) << 9));\n int _metile_register_packed______________________________ = _metile_bounded_thread + 960;\n int _metile_register_index______________________________ = int((((_metile_register_packed______________________________ >> 5) & 1u) << 0) | (((_metile_register_packed______________________________ >> 6) & 1u) << 1) | (((_metile_register_packed______________________________ >> 0) & 1u) << 2) | (((_metile_register_packed______________________________ >> 1) & 1u) << 3) | (((_metile_register_packed______________________________ >> 2) & 1u) << 4) | (((_metile_register_packed______________________________ >> 3) & 1u) << 5) | (((_metile_register_packed______________________________ >> 4) & 1u) << 6) | (((_metile_register_packed______________________________ >> 7) & 1u) << 7) | (((_metile_register_packed______________________________ >> 8) & 1u) << 8) | (((_metile_register_packed______________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________________________ = _metile_bounded_thread + 992;\n int _metile_register_index_______________________________ = int((((_metile_register_packed_______________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________________________ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v16_r16 = _metile_register_index________________ >= 0;\n bool _metile_v16_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v16_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v16_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v16_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v16_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v16_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v16_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v16_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v16_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v16_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v16_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v16_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v16_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v16_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v16_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v17_r8 = _metile_register_index________ < 1009;\n bool _metile_v17_r9 = _metile_register_index_________ < 1009;\n bool _metile_v17_r10 = _metile_register_index__________ < 1009;\n bool _metile_v17_r11 = _metile_register_index___________ < 1009;\n bool _metile_v17_r12 = _metile_register_index____________ < 1009;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v17_r14 = _metile_register_index______________ < 1009;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v17_r16 = _metile_register_index________________ < 1009;\n bool _metile_v17_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v17_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v17_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v17_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v17_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v17_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v17_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v17_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v17_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v17_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v17_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v17_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v17_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v17_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v17_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n bool _metile_v18_r16 = _metile_v16_r16 & _metile_v17_r16;\n bool _metile_v18_r17 = _metile_v16_r17 & _metile_v17_r17;\n bool _metile_v18_r18 = _metile_v16_r18 & _metile_v17_r18;\n bool _metile_v18_r19 = _metile_v16_r19 & _metile_v17_r19;\n bool _metile_v18_r20 = _metile_v16_r20 & _metile_v17_r20;\n bool _metile_v18_r21 = _metile_v16_r21 & _metile_v17_r21;\n bool _metile_v18_r22 = _metile_v16_r22 & _metile_v17_r22;\n bool _metile_v18_r23 = _metile_v16_r23 & _metile_v17_r23;\n bool _metile_v18_r24 = _metile_v16_r24 & _metile_v17_r24;\n bool _metile_v18_r25 = _metile_v16_r25 & _metile_v17_r25;\n bool _metile_v18_r26 = _metile_v16_r26 & _metile_v17_r26;\n bool _metile_v18_r27 = _metile_v16_r27 & _metile_v17_r27;\n bool _metile_v18_r28 = _metile_v16_r28 & _metile_v17_r28;\n bool _metile_v18_r29 = _metile_v16_r29 & _metile_v17_r29;\n bool _metile_v18_r30 = _metile_v16_r30 & _metile_v17_r30;\n bool _metile_v18_r31 = _metile_v16_r31 & _metile_v17_r31;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n int _off__metile_v19_r16 = v2 + _metile_register_index________________;\n int _off__metile_v19_r17 = v2 + _metile_register_index_________________;\n int _off__metile_v19_r18 = v2 + _metile_register_index__________________;\n int _off__metile_v19_r19 = v2 + _metile_register_index___________________;\n int _off__metile_v19_r20 = v2 + _metile_register_index____________________;\n int _off__metile_v19_r21 = v2 + _metile_register_index_____________________;\n int _off__metile_v19_r22 = v2 + _metile_register_index______________________;\n int _off__metile_v19_r23 = v2 + _metile_register_index_______________________;\n int _off__metile_v19_r24 = v2 + _metile_register_index________________________;\n int _off__metile_v19_r25 = v2 + _metile_register_index_________________________;\n int _off__metile_v19_r26 = v2 + _metile_register_index__________________________;\n int _off__metile_v19_r27 = v2 + _metile_register_index___________________________;\n int _off__metile_v19_r28 = v2 + _metile_register_index____________________________;\n int _off__metile_v19_r29 = v2 + _metile_register_index_____________________________;\n int _off__metile_v19_r30 = v2 + _metile_register_index______________________________;\n int _off__metile_v19_r31 = v2 + _metile_register_index_______________________________;\n half4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = half4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n half _metile_v20_r0 = _metile_vector_load[0];\n half _metile_v20_r1 = _metile_vector_load[1];\n half _metile_v20_r2 = _metile_vector_load[2];\n half _metile_v20_r3 = _metile_vector_load[3];\n half4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = half4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n half _metile_v20_r4 = _metile_vector_load_[0];\n half _metile_v20_r5 = _metile_vector_load_[1];\n half _metile_v20_r6 = _metile_vector_load_[2];\n half _metile_v20_r7 = _metile_vector_load_[3];\n half4 _metile_vector_load__;\n if ((_metile_v18_r8) && (_metile_v18_r9) && (_metile_v18_r10) && (_metile_v18_r11) && (long(_off__metile_v19_r9) == long(_off__metile_v19_r8) + 1) && (long(_off__metile_v19_r10) == long(_off__metile_v19_r8) + 2) && (long(_off__metile_v19_r11) == long(_off__metile_v19_r8) + 3)) {\n _metile_vector_load__ = half4(*reinterpret_cast(X + _off__metile_v19_r8));\n } else {\n _metile_vector_load__[0] = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n _metile_vector_load__[1] = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n _metile_vector_load__[2] = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n _metile_vector_load__[3] = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n }\n half _metile_v20_r8 = _metile_vector_load__[0];\n half _metile_v20_r9 = _metile_vector_load__[1];\n half _metile_v20_r10 = _metile_vector_load__[2];\n half _metile_v20_r11 = _metile_vector_load__[3];\n half4 _metile_vector_load___;\n if ((_metile_v18_r12) && (_metile_v18_r13) && (_metile_v18_r14) && (_metile_v18_r15) && (long(_off__metile_v19_r13) == long(_off__metile_v19_r12) + 1) && (long(_off__metile_v19_r14) == long(_off__metile_v19_r12) + 2) && (long(_off__metile_v19_r15) == long(_off__metile_v19_r12) + 3)) {\n _metile_vector_load___ = half4(*reinterpret_cast(X + _off__metile_v19_r12));\n } else {\n _metile_vector_load___[0] = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n _metile_vector_load___[1] = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n _metile_vector_load___[2] = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n _metile_vector_load___[3] = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n }\n half _metile_v20_r12 = _metile_vector_load___[0];\n half _metile_v20_r13 = _metile_vector_load___[1];\n half _metile_v20_r14 = _metile_vector_load___[2];\n half _metile_v20_r15 = _metile_vector_load___[3];\n half4 _metile_vector_load____;\n if ((_metile_v18_r16) && (_metile_v18_r17) && (_metile_v18_r18) && (_metile_v18_r19) && (long(_off__metile_v19_r17) == long(_off__metile_v19_r16) + 1) && (long(_off__metile_v19_r18) == long(_off__metile_v19_r16) + 2) && (long(_off__metile_v19_r19) == long(_off__metile_v19_r16) + 3)) {\n _metile_vector_load____ = half4(*reinterpret_cast(X + _off__metile_v19_r16));\n } else {\n _metile_vector_load____[0] = _metile_v18_r16 ? X[_off__metile_v19_r16] : static_cast(0);\n _metile_vector_load____[1] = _metile_v18_r17 ? X[_off__metile_v19_r17] : static_cast(0);\n _metile_vector_load____[2] = _metile_v18_r18 ? X[_off__metile_v19_r18] : static_cast(0);\n _metile_vector_load____[3] = _metile_v18_r19 ? X[_off__metile_v19_r19] : static_cast(0);\n }\n half _metile_v20_r16 = _metile_vector_load____[0];\n half _metile_v20_r17 = _metile_vector_load____[1];\n half _metile_v20_r18 = _metile_vector_load____[2];\n half _metile_v20_r19 = _metile_vector_load____[3];\n half4 _metile_vector_load_____;\n if ((_metile_v18_r20) && (_metile_v18_r21) && (_metile_v18_r22) && (_metile_v18_r23) && (long(_off__metile_v19_r21) == long(_off__metile_v19_r20) + 1) && (long(_off__metile_v19_r22) == long(_off__metile_v19_r20) + 2) && (long(_off__metile_v19_r23) == long(_off__metile_v19_r20) + 3)) {\n _metile_vector_load_____ = half4(*reinterpret_cast(X + _off__metile_v19_r20));\n } else {\n _metile_vector_load_____[0] = _metile_v18_r20 ? X[_off__metile_v19_r20] : static_cast(0);\n _metile_vector_load_____[1] = _metile_v18_r21 ? X[_off__metile_v19_r21] : static_cast(0);\n _metile_vector_load_____[2] = _metile_v18_r22 ? X[_off__metile_v19_r22] : static_cast(0);\n _metile_vector_load_____[3] = _metile_v18_r23 ? X[_off__metile_v19_r23] : static_cast(0);\n }\n half _metile_v20_r20 = _metile_vector_load_____[0];\n half _metile_v20_r21 = _metile_vector_load_____[1];\n half _metile_v20_r22 = _metile_vector_load_____[2];\n half _metile_v20_r23 = _metile_vector_load_____[3];\n half4 _metile_vector_load______;\n if ((_metile_v18_r24) && (_metile_v18_r25) && (_metile_v18_r26) && (_metile_v18_r27) && (long(_off__metile_v19_r25) == long(_off__metile_v19_r24) + 1) && (long(_off__metile_v19_r26) == long(_off__metile_v19_r24) + 2) && (long(_off__metile_v19_r27) == long(_off__metile_v19_r24) + 3)) {\n _metile_vector_load______ = half4(*reinterpret_cast(X + _off__metile_v19_r24));\n } else {\n _metile_vector_load______[0] = _metile_v18_r24 ? X[_off__metile_v19_r24] : static_cast(0);\n _metile_vector_load______[1] = _metile_v18_r25 ? X[_off__metile_v19_r25] : static_cast(0);\n _metile_vector_load______[2] = _metile_v18_r26 ? X[_off__metile_v19_r26] : static_cast(0);\n _metile_vector_load______[3] = _metile_v18_r27 ? X[_off__metile_v19_r27] : static_cast(0);\n }\n half _metile_v20_r24 = _metile_vector_load______[0];\n half _metile_v20_r25 = _metile_vector_load______[1];\n half _metile_v20_r26 = _metile_vector_load______[2];\n half _metile_v20_r27 = _metile_vector_load______[3];\n half4 _metile_vector_load_______;\n if ((_metile_v18_r28) && (_metile_v18_r29) && (_metile_v18_r30) && (_metile_v18_r31) && (long(_off__metile_v19_r29) == long(_off__metile_v19_r28) + 1) && (long(_off__metile_v19_r30) == long(_off__metile_v19_r28) + 2) && (long(_off__metile_v19_r31) == long(_off__metile_v19_r28) + 3)) {\n _metile_vector_load_______ = half4(*reinterpret_cast(X + _off__metile_v19_r28));\n } else {\n _metile_vector_load_______[0] = _metile_v18_r28 ? X[_off__metile_v19_r28] : static_cast(0);\n _metile_vector_load_______[1] = _metile_v18_r29 ? X[_off__metile_v19_r29] : static_cast(0);\n _metile_vector_load_______[2] = _metile_v18_r30 ? X[_off__metile_v19_r30] : static_cast(0);\n _metile_vector_load_______[3] = _metile_v18_r31 ? X[_off__metile_v19_r31] : static_cast(0);\n }\n half _metile_v20_r28 = _metile_vector_load_______[0];\n half _metile_v20_r29 = _metile_vector_load_______[1];\n half _metile_v20_r30 = _metile_vector_load_______[2];\n half _metile_v20_r31 = _metile_vector_load_______[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v21_r16 = static_cast(_metile_v20_r16);\n float _metile_v21_r17 = static_cast(_metile_v20_r17);\n float _metile_v21_r18 = static_cast(_metile_v20_r18);\n float _metile_v21_r19 = static_cast(_metile_v20_r19);\n float _metile_v21_r20 = static_cast(_metile_v20_r20);\n float _metile_v21_r21 = static_cast(_metile_v20_r21);\n float _metile_v21_r22 = static_cast(_metile_v20_r22);\n float _metile_v21_r23 = static_cast(_metile_v20_r23);\n float _metile_v21_r24 = static_cast(_metile_v20_r24);\n float _metile_v21_r25 = static_cast(_metile_v20_r25);\n float _metile_v21_r26 = static_cast(_metile_v20_r26);\n float _metile_v21_r27 = static_cast(_metile_v20_r27);\n float _metile_v21_r28 = static_cast(_metile_v20_r28);\n float _metile_v21_r29 = static_cast(_metile_v20_r29);\n float _metile_v21_r30 = static_cast(_metile_v20_r30);\n float _metile_v21_r31 = static_cast(_metile_v20_r31);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_v22_r16 = _metile_v21_r16 * _metile_v21_r16;\n float _metile_v22_r17 = _metile_v21_r17 * _metile_v21_r17;\n float _metile_v22_r18 = _metile_v21_r18 * _metile_v21_r18;\n float _metile_v22_r19 = _metile_v21_r19 * _metile_v21_r19;\n float _metile_v22_r20 = _metile_v21_r20 * _metile_v21_r20;\n float _metile_v22_r21 = _metile_v21_r21 * _metile_v21_r21;\n float _metile_v22_r22 = _metile_v21_r22 * _metile_v21_r22;\n float _metile_v22_r23 = _metile_v21_r23 * _metile_v21_r23;\n float _metile_v22_r24 = _metile_v21_r24 * _metile_v21_r24;\n float _metile_v22_r25 = _metile_v21_r25 * _metile_v21_r25;\n float _metile_v22_r26 = _metile_v21_r26 * _metile_v21_r26;\n float _metile_v22_r27 = _metile_v21_r27 * _metile_v21_r27;\n float _metile_v22_r28 = _metile_v21_r28 * _metile_v21_r28;\n float _metile_v22_r29 = _metile_v21_r29 * _metile_v21_r29;\n float _metile_v22_r30 = _metile_v21_r30 * _metile_v21_r30;\n float _metile_v22_r31 = _metile_v21_r31 * _metile_v21_r31;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_v22_r16 + _metile_v22_r17;\n float _metile_register_sum_________ = _metile_v22_r18 + _metile_v22_r19;\n float _metile_register_sum__________ = _metile_v22_r20 + _metile_v22_r21;\n float _metile_register_sum___________ = _metile_v22_r22 + _metile_v22_r23;\n float _metile_register_sum____________ = _metile_v22_r24 + _metile_v22_r25;\n float _metile_register_sum_____________ = _metile_v22_r26 + _metile_v22_r27;\n float _metile_register_sum______________ = _metile_v22_r28 + _metile_v22_r29;\n float _metile_register_sum_______________ = _metile_v22_r30 + _metile_v22_r31;\n float _metile_register_sum________________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________________ = _metile_register_sum____________ + _metile_register_sum_____________;\n float _metile_register_sum_______________________ = _metile_register_sum______________ + _metile_register_sum_______________;\n float _metile_register_sum________________________ = _metile_register_sum________________ + _metile_register_sum_________________;\n float _metile_register_sum_________________________ = _metile_register_sum__________________ + _metile_register_sum___________________;\n float _metile_register_sum__________________________ = _metile_register_sum____________________ + _metile_register_sum_____________________;\n float _metile_register_sum___________________________ = _metile_register_sum______________________ + _metile_register_sum_______________________;\n float _metile_register_sum____________________________ = _metile_register_sum________________________ + _metile_register_sum_________________________;\n float _metile_register_sum_____________________________ = _metile_register_sum__________________________ + _metile_register_sum___________________________;\n float _metile_register_sum______________________________ = _metile_register_sum____________________________ + _metile_register_sum_____________________________;\n float v23 = simd_sum(_metile_register_sum______________________________);\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v32_r16 = _metile_register_index________________ >= 0;\n bool _metile_v32_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v32_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v32_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v32_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v32_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v32_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v32_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v32_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v32_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v32_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v32_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v32_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v32_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v32_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v32_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v33_r8 = _metile_register_index________ < 1009;\n bool _metile_v33_r9 = _metile_register_index_________ < 1009;\n bool _metile_v33_r10 = _metile_register_index__________ < 1009;\n bool _metile_v33_r11 = _metile_register_index___________ < 1009;\n bool _metile_v33_r12 = _metile_register_index____________ < 1009;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v33_r14 = _metile_register_index______________ < 1009;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v33_r16 = _metile_register_index________________ < 1009;\n bool _metile_v33_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v33_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v33_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v33_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v33_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v33_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v33_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v33_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v33_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v33_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v33_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v33_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v33_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v33_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v33_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n bool _metile_v34_r16 = _metile_v32_r16 & _metile_v33_r16;\n bool _metile_v34_r17 = _metile_v32_r17 & _metile_v33_r17;\n bool _metile_v34_r18 = _metile_v32_r18 & _metile_v33_r18;\n bool _metile_v34_r19 = _metile_v32_r19 & _metile_v33_r19;\n bool _metile_v34_r20 = _metile_v32_r20 & _metile_v33_r20;\n bool _metile_v34_r21 = _metile_v32_r21 & _metile_v33_r21;\n bool _metile_v34_r22 = _metile_v32_r22 & _metile_v33_r22;\n bool _metile_v34_r23 = _metile_v32_r23 & _metile_v33_r23;\n bool _metile_v34_r24 = _metile_v32_r24 & _metile_v33_r24;\n bool _metile_v34_r25 = _metile_v32_r25 & _metile_v33_r25;\n bool _metile_v34_r26 = _metile_v32_r26 & _metile_v33_r26;\n bool _metile_v34_r27 = _metile_v32_r27 & _metile_v33_r27;\n bool _metile_v34_r28 = _metile_v32_r28 & _metile_v33_r28;\n bool _metile_v34_r29 = _metile_v32_r29 & _metile_v33_r29;\n bool _metile_v34_r30 = _metile_v32_r30 & _metile_v33_r30;\n bool _metile_v34_r31 = _metile_v32_r31 & _metile_v33_r31;\n half4 _metile_vector_load________;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load________ = half4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load________[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load________[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load________[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load________[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n half _metile_v36_r0 = _metile_vector_load________[0];\n half _metile_v36_r1 = _metile_vector_load________[1];\n half _metile_v36_r2 = _metile_vector_load________[2];\n half _metile_v36_r3 = _metile_vector_load________[3];\n half4 _metile_vector_load_________;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load_________ = half4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load_________[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load_________[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load_________[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load_________[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n half _metile_v36_r4 = _metile_vector_load_________[0];\n half _metile_v36_r5 = _metile_vector_load_________[1];\n half _metile_v36_r6 = _metile_vector_load_________[2];\n half _metile_v36_r7 = _metile_vector_load_________[3];\n half4 _metile_vector_load__________;\n if ((_metile_v34_r8) && (_metile_v34_r9) && (_metile_v34_r10) && (_metile_v34_r11) && (long(_metile_register_index_________) == long(_metile_register_index________) + 1) && (long(_metile_register_index__________) == long(_metile_register_index________) + 2) && (long(_metile_register_index___________) == long(_metile_register_index________) + 3)) {\n _metile_vector_load__________ = half4(*reinterpret_cast(W + _metile_register_index________));\n } else {\n _metile_vector_load__________[0] = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n _metile_vector_load__________[1] = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n _metile_vector_load__________[2] = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n _metile_vector_load__________[3] = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n }\n half _metile_v36_r8 = _metile_vector_load__________[0];\n half _metile_v36_r9 = _metile_vector_load__________[1];\n half _metile_v36_r10 = _metile_vector_load__________[2];\n half _metile_v36_r11 = _metile_vector_load__________[3];\n half4 _metile_vector_load___________;\n if ((_metile_v34_r12) && (_metile_v34_r13) && (_metile_v34_r14) && (_metile_v34_r15) && (long(_metile_register_index_____________) == long(_metile_register_index____________) + 1) && (long(_metile_register_index______________) == long(_metile_register_index____________) + 2) && (long(_metile_register_index_______________) == long(_metile_register_index____________) + 3)) {\n _metile_vector_load___________ = half4(*reinterpret_cast(W + _metile_register_index____________));\n } else {\n _metile_vector_load___________[0] = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n _metile_vector_load___________[1] = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n _metile_vector_load___________[2] = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n _metile_vector_load___________[3] = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n }\n half _metile_v36_r12 = _metile_vector_load___________[0];\n half _metile_v36_r13 = _metile_vector_load___________[1];\n half _metile_v36_r14 = _metile_vector_load___________[2];\n half _metile_v36_r15 = _metile_vector_load___________[3];\n half4 _metile_vector_load____________;\n if ((_metile_v34_r16) && (_metile_v34_r17) && (_metile_v34_r18) && (_metile_v34_r19) && (long(_metile_register_index_________________) == long(_metile_register_index________________) + 1) && (long(_metile_register_index__________________) == long(_metile_register_index________________) + 2) && (long(_metile_register_index___________________) == long(_metile_register_index________________) + 3)) {\n _metile_vector_load____________ = half4(*reinterpret_cast(W + _metile_register_index________________));\n } else {\n _metile_vector_load____________[0] = _metile_v34_r16 ? W[_metile_register_index________________] : static_cast(0);\n _metile_vector_load____________[1] = _metile_v34_r17 ? W[_metile_register_index_________________] : static_cast(0);\n _metile_vector_load____________[2] = _metile_v34_r18 ? W[_metile_register_index__________________] : static_cast(0);\n _metile_vector_load____________[3] = _metile_v34_r19 ? W[_metile_register_index___________________] : static_cast(0);\n }\n half _metile_v36_r16 = _metile_vector_load____________[0];\n half _metile_v36_r17 = _metile_vector_load____________[1];\n half _metile_v36_r18 = _metile_vector_load____________[2];\n half _metile_v36_r19 = _metile_vector_load____________[3];\n half4 _metile_vector_load_____________;\n if ((_metile_v34_r20) && (_metile_v34_r21) && (_metile_v34_r22) && (_metile_v34_r23) && (long(_metile_register_index_____________________) == long(_metile_register_index____________________) + 1) && (long(_metile_register_index______________________) == long(_metile_register_index____________________) + 2) && (long(_metile_register_index_______________________) == long(_metile_register_index____________________) + 3)) {\n _metile_vector_load_____________ = half4(*reinterpret_cast(W + _metile_register_index____________________));\n } else {\n _metile_vector_load_____________[0] = _metile_v34_r20 ? W[_metile_register_index____________________] : static_cast(0);\n _metile_vector_load_____________[1] = _metile_v34_r21 ? W[_metile_register_index_____________________] : static_cast(0);\n _metile_vector_load_____________[2] = _metile_v34_r22 ? W[_metile_register_index______________________] : static_cast(0);\n _metile_vector_load_____________[3] = _metile_v34_r23 ? W[_metile_register_index_______________________] : static_cast(0);\n }\n half _metile_v36_r20 = _metile_vector_load_____________[0];\n half _metile_v36_r21 = _metile_vector_load_____________[1];\n half _metile_v36_r22 = _metile_vector_load_____________[2];\n half _metile_v36_r23 = _metile_vector_load_____________[3];\n half4 _metile_vector_load______________;\n if ((_metile_v34_r24) && (_metile_v34_r25) && (_metile_v34_r26) && (_metile_v34_r27) && (long(_metile_register_index_________________________) == long(_metile_register_index________________________) + 1) && (long(_metile_register_index__________________________) == long(_metile_register_index________________________) + 2) && (long(_metile_register_index___________________________) == long(_metile_register_index________________________) + 3)) {\n _metile_vector_load______________ = half4(*reinterpret_cast(W + _metile_register_index________________________));\n } else {\n _metile_vector_load______________[0] = _metile_v34_r24 ? W[_metile_register_index________________________] : static_cast(0);\n _metile_vector_load______________[1] = _metile_v34_r25 ? W[_metile_register_index_________________________] : static_cast(0);\n _metile_vector_load______________[2] = _metile_v34_r26 ? W[_metile_register_index__________________________] : static_cast(0);\n _metile_vector_load______________[3] = _metile_v34_r27 ? W[_metile_register_index___________________________] : static_cast(0);\n }\n half _metile_v36_r24 = _metile_vector_load______________[0];\n half _metile_v36_r25 = _metile_vector_load______________[1];\n half _metile_v36_r26 = _metile_vector_load______________[2];\n half _metile_v36_r27 = _metile_vector_load______________[3];\n half4 _metile_vector_load_______________;\n if ((_metile_v34_r28) && (_metile_v34_r29) && (_metile_v34_r30) && (_metile_v34_r31) && (long(_metile_register_index_____________________________) == long(_metile_register_index____________________________) + 1) && (long(_metile_register_index______________________________) == long(_metile_register_index____________________________) + 2) && (long(_metile_register_index_______________________________) == long(_metile_register_index____________________________) + 3)) {\n _metile_vector_load_______________ = half4(*reinterpret_cast(W + _metile_register_index____________________________));\n } else {\n _metile_vector_load_______________[0] = _metile_v34_r28 ? W[_metile_register_index____________________________] : static_cast(0);\n _metile_vector_load_______________[1] = _metile_v34_r29 ? W[_metile_register_index_____________________________] : static_cast(0);\n _metile_vector_load_______________[2] = _metile_v34_r30 ? W[_metile_register_index______________________________] : static_cast(0);\n _metile_vector_load_______________[3] = _metile_v34_r31 ? W[_metile_register_index_______________________________] : static_cast(0);\n }\n half _metile_v36_r28 = _metile_vector_load_______________[0];\n half _metile_v36_r29 = _metile_vector_load_______________[1];\n half _metile_v36_r30 = _metile_vector_load_______________[2];\n half _metile_v36_r31 = _metile_vector_load_______________[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v37_r16 = static_cast(_metile_v36_r16);\n float _metile_v37_r17 = static_cast(_metile_v36_r17);\n float _metile_v37_r18 = static_cast(_metile_v36_r18);\n float _metile_v37_r19 = static_cast(_metile_v36_r19);\n float _metile_v37_r20 = static_cast(_metile_v36_r20);\n float _metile_v37_r21 = static_cast(_metile_v36_r21);\n float _metile_v37_r22 = static_cast(_metile_v36_r22);\n float _metile_v37_r23 = static_cast(_metile_v36_r23);\n float _metile_v37_r24 = static_cast(_metile_v36_r24);\n float _metile_v37_r25 = static_cast(_metile_v36_r25);\n float _metile_v37_r26 = static_cast(_metile_v36_r26);\n float _metile_v37_r27 = static_cast(_metile_v36_r27);\n float _metile_v37_r28 = static_cast(_metile_v36_r28);\n float _metile_v37_r29 = static_cast(_metile_v36_r29);\n float _metile_v37_r30 = static_cast(_metile_v36_r30);\n float _metile_v37_r31 = static_cast(_metile_v36_r31);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v38_r16 = _metile_v21_r16 * v29;\n float _metile_v38_r17 = _metile_v21_r17 * v29;\n float _metile_v38_r18 = _metile_v21_r18 * v29;\n float _metile_v38_r19 = _metile_v21_r19 * v29;\n float _metile_v38_r20 = _metile_v21_r20 * v29;\n float _metile_v38_r21 = _metile_v21_r21 * v29;\n float _metile_v38_r22 = _metile_v21_r22 * v29;\n float _metile_v38_r23 = _metile_v21_r23 * v29;\n float _metile_v38_r24 = _metile_v21_r24 * v29;\n float _metile_v38_r25 = _metile_v21_r25 * v29;\n float _metile_v38_r26 = _metile_v21_r26 * v29;\n float _metile_v38_r27 = _metile_v21_r27 * v29;\n float _metile_v38_r28 = _metile_v21_r28 * v29;\n float _metile_v38_r29 = _metile_v21_r29 * v29;\n float _metile_v38_r30 = _metile_v21_r30 * v29;\n float _metile_v38_r31 = _metile_v21_r31 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n float _metile_v39_r16 = _metile_v38_r16 * _metile_v37_r16;\n float _metile_v39_r17 = _metile_v38_r17 * _metile_v37_r17;\n float _metile_v39_r18 = _metile_v38_r18 * _metile_v37_r18;\n float _metile_v39_r19 = _metile_v38_r19 * _metile_v37_r19;\n float _metile_v39_r20 = _metile_v38_r20 * _metile_v37_r20;\n float _metile_v39_r21 = _metile_v38_r21 * _metile_v37_r21;\n float _metile_v39_r22 = _metile_v38_r22 * _metile_v37_r22;\n float _metile_v39_r23 = _metile_v38_r23 * _metile_v37_r23;\n float _metile_v39_r24 = _metile_v38_r24 * _metile_v37_r24;\n float _metile_v39_r25 = _metile_v38_r25 * _metile_v37_r25;\n float _metile_v39_r26 = _metile_v38_r26 * _metile_v37_r26;\n float _metile_v39_r27 = _metile_v38_r27 * _metile_v37_r27;\n float _metile_v39_r28 = _metile_v38_r28 * _metile_v37_r28;\n float _metile_v39_r29 = _metile_v38_r29 * _metile_v37_r29;\n float _metile_v39_r30 = _metile_v38_r30 * _metile_v37_r30;\n float _metile_v39_r31 = _metile_v38_r31 * _metile_v37_r31;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v41_r16 = _metile_register_index________________ >= 0;\n bool _metile_v41_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v41_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v41_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v41_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v41_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v41_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v41_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v41_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v41_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v41_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v41_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v41_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v41_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v41_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v41_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v42_r8 = _metile_register_index________ < 1009;\n bool _metile_v42_r9 = _metile_register_index_________ < 1009;\n bool _metile_v42_r10 = _metile_register_index__________ < 1009;\n bool _metile_v42_r11 = _metile_register_index___________ < 1009;\n bool _metile_v42_r12 = _metile_register_index____________ < 1009;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v42_r14 = _metile_register_index______________ < 1009;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v42_r16 = _metile_register_index________________ < 1009;\n bool _metile_v42_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v42_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v42_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v42_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v42_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v42_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v42_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v42_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v42_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v42_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v42_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v42_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v42_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v42_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v42_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n bool _metile_v43_r16 = _metile_v41_r16 & _metile_v42_r16;\n bool _metile_v43_r17 = _metile_v41_r17 & _metile_v42_r17;\n bool _metile_v43_r18 = _metile_v41_r18 & _metile_v42_r18;\n bool _metile_v43_r19 = _metile_v41_r19 & _metile_v42_r19;\n bool _metile_v43_r20 = _metile_v41_r20 & _metile_v42_r20;\n bool _metile_v43_r21 = _metile_v41_r21 & _metile_v42_r21;\n bool _metile_v43_r22 = _metile_v41_r22 & _metile_v42_r22;\n bool _metile_v43_r23 = _metile_v41_r23 & _metile_v42_r23;\n bool _metile_v43_r24 = _metile_v41_r24 & _metile_v42_r24;\n bool _metile_v43_r25 = _metile_v41_r25 & _metile_v42_r25;\n bool _metile_v43_r26 = _metile_v41_r26 & _metile_v42_r26;\n bool _metile_v43_r27 = _metile_v41_r27 & _metile_v42_r27;\n bool _metile_v43_r28 = _metile_v41_r28 & _metile_v42_r28;\n bool _metile_v43_r29 = _metile_v41_r29 & _metile_v42_r29;\n bool _metile_v43_r30 = _metile_v41_r30 & _metile_v42_r30;\n bool _metile_v43_r31 = _metile_v41_r31 & _metile_v42_r31;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n int _off__metile_v44_r16 = v9 + _metile_register_index________________;\n int _off__metile_v44_r17 = v9 + _metile_register_index_________________;\n int _off__metile_v44_r18 = v9 + _metile_register_index__________________;\n int _off__metile_v44_r19 = v9 + _metile_register_index___________________;\n int _off__metile_v44_r20 = v9 + _metile_register_index____________________;\n int _off__metile_v44_r21 = v9 + _metile_register_index_____________________;\n int _off__metile_v44_r22 = v9 + _metile_register_index______________________;\n int _off__metile_v44_r23 = v9 + _metile_register_index_______________________;\n int _off__metile_v44_r24 = v9 + _metile_register_index________________________;\n int _off__metile_v44_r25 = v9 + _metile_register_index_________________________;\n int _off__metile_v44_r26 = v9 + _metile_register_index__________________________;\n int _off__metile_v44_r27 = v9 + _metile_register_index___________________________;\n int _off__metile_v44_r28 = v9 + _metile_register_index____________________________;\n int _off__metile_v44_r29 = v9 + _metile_register_index_____________________________;\n int _off__metile_v44_r30 = v9 + _metile_register_index______________________________;\n int _off__metile_v44_r31 = v9 + _metile_register_index_______________________________;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_half4(half4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_half4(half4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n if ((_metile_v43_r8) && (_metile_v43_r9) && (_metile_v43_r10) && (_metile_v43_r11) && (long(_off__metile_v44_r9) == long(_off__metile_v44_r8) + 1) && (long(_off__metile_v44_r10) == long(_off__metile_v44_r8) + 2) && (long(_off__metile_v44_r11) == long(_off__metile_v44_r8) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r8) = packed_half4(half4(static_cast(_metile_v39_r8), static_cast(_metile_v39_r9), static_cast(_metile_v39_r10), static_cast(_metile_v39_r11)));\n } else {\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = static_cast(_metile_v39_r8); }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = static_cast(_metile_v39_r9); }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = static_cast(_metile_v39_r10); }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = static_cast(_metile_v39_r11); }\n }\n if ((_metile_v43_r12) && (_metile_v43_r13) && (_metile_v43_r14) && (_metile_v43_r15) && (long(_off__metile_v44_r13) == long(_off__metile_v44_r12) + 1) && (long(_off__metile_v44_r14) == long(_off__metile_v44_r12) + 2) && (long(_off__metile_v44_r15) == long(_off__metile_v44_r12) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r12) = packed_half4(half4(static_cast(_metile_v39_r12), static_cast(_metile_v39_r13), static_cast(_metile_v39_r14), static_cast(_metile_v39_r15)));\n } else {\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = static_cast(_metile_v39_r12); }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = static_cast(_metile_v39_r13); }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = static_cast(_metile_v39_r14); }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = static_cast(_metile_v39_r15); }\n }\n if ((_metile_v43_r16) && (_metile_v43_r17) && (_metile_v43_r18) && (_metile_v43_r19) && (long(_off__metile_v44_r17) == long(_off__metile_v44_r16) + 1) && (long(_off__metile_v44_r18) == long(_off__metile_v44_r16) + 2) && (long(_off__metile_v44_r19) == long(_off__metile_v44_r16) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r16) = packed_half4(half4(static_cast(_metile_v39_r16), static_cast(_metile_v39_r17), static_cast(_metile_v39_r18), static_cast(_metile_v39_r19)));\n } else {\n if (_metile_v43_r16) { Out[_off__metile_v44_r16] = static_cast(_metile_v39_r16); }\n if (_metile_v43_r17) { Out[_off__metile_v44_r17] = static_cast(_metile_v39_r17); }\n if (_metile_v43_r18) { Out[_off__metile_v44_r18] = static_cast(_metile_v39_r18); }\n if (_metile_v43_r19) { Out[_off__metile_v44_r19] = static_cast(_metile_v39_r19); }\n }\n if ((_metile_v43_r20) && (_metile_v43_r21) && (_metile_v43_r22) && (_metile_v43_r23) && (long(_off__metile_v44_r21) == long(_off__metile_v44_r20) + 1) && (long(_off__metile_v44_r22) == long(_off__metile_v44_r20) + 2) && (long(_off__metile_v44_r23) == long(_off__metile_v44_r20) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r20) = packed_half4(half4(static_cast(_metile_v39_r20), static_cast(_metile_v39_r21), static_cast(_metile_v39_r22), static_cast(_metile_v39_r23)));\n } else {\n if (_metile_v43_r20) { Out[_off__metile_v44_r20] = static_cast(_metile_v39_r20); }\n if (_metile_v43_r21) { Out[_off__metile_v44_r21] = static_cast(_metile_v39_r21); }\n if (_metile_v43_r22) { Out[_off__metile_v44_r22] = static_cast(_metile_v39_r22); }\n if (_metile_v43_r23) { Out[_off__metile_v44_r23] = static_cast(_metile_v39_r23); }\n }\n if ((_metile_v43_r24) && (_metile_v43_r25) && (_metile_v43_r26) && (_metile_v43_r27) && (long(_off__metile_v44_r25) == long(_off__metile_v44_r24) + 1) && (long(_off__metile_v44_r26) == long(_off__metile_v44_r24) + 2) && (long(_off__metile_v44_r27) == long(_off__metile_v44_r24) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r24) = packed_half4(half4(static_cast(_metile_v39_r24), static_cast(_metile_v39_r25), static_cast(_metile_v39_r26), static_cast(_metile_v39_r27)));\n } else {\n if (_metile_v43_r24) { Out[_off__metile_v44_r24] = static_cast(_metile_v39_r24); }\n if (_metile_v43_r25) { Out[_off__metile_v44_r25] = static_cast(_metile_v39_r25); }\n if (_metile_v43_r26) { Out[_off__metile_v44_r26] = static_cast(_metile_v39_r26); }\n if (_metile_v43_r27) { Out[_off__metile_v44_r27] = static_cast(_metile_v39_r27); }\n }\n if ((_metile_v43_r28) && (_metile_v43_r29) && (_metile_v43_r30) && (_metile_v43_r31) && (long(_off__metile_v44_r29) == long(_off__metile_v44_r28) + 1) && (long(_off__metile_v44_r30) == long(_off__metile_v44_r28) + 2) && (long(_off__metile_v44_r31) == long(_off__metile_v44_r28) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r28) = packed_half4(half4(static_cast(_metile_v39_r28), static_cast(_metile_v39_r29), static_cast(_metile_v39_r30), static_cast(_metile_v39_r31)));\n } else {\n if (_metile_v43_r28) { Out[_off__metile_v44_r28] = static_cast(_metile_v39_r28); }\n if (_metile_v43_r29) { Out[_off__metile_v44_r29] = static_cast(_metile_v39_r29); }\n if (_metile_v43_r30) { Out[_off__metile_v44_r30] = static_cast(_metile_v39_r30); }\n if (_metile_v43_r31) { Out[_off__metile_v44_r31] = static_cast(_metile_v39_r31); }\n }\n}", "source_sha256": "56609b88a4b5b52c4d86d853e94eea93cb604868c18edef7efe33f8c98978f8f", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 32, 1, 1 ], "is_gemm": false, "prefer_ordered": false, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 32, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 32 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [], "double_buffered": false, "vectorized_loads": 16, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 32, "threads": 32, "scratch": null, "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 16, "grouped_stores": 8 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 576, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 210.833, "control": 207.333, "speedup": 0.9833991832398153 }, "gpu_us": { "candidate": 7.333292160183191, "control": 5.624955520033836, "speedup": 0.7670436956780569 } } }, { "frozen_register4": { "pairs": 538, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 210.75, "control": 207.708, "speedup": 0.9855658362989324 }, "gpu_us": { "candidate": 7.333350367844105, "control": 5.62501372769475, "speedup": 0.7670455447430667 } } }, { "frozen_register4": { "pairs": 573, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 209.459, "control": 208.833, "speedup": 0.9970113482829575 }, "gpu_us": { "candidate": 7.374968845397234, "control": 5.624955520033836, "speedup": 0.7627090551771494 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9886407982124261, "round_speedups": [ 0.9833991832398153, 0.9855658362989324, 0.9970113482829575 ], "candidate": 210.34639139462482, "control": 207.95702428948553 }, "gpu_us": { "speedup": 0.7655967004045169, "round_speedups": [ 0.7670436956780569, 0.7670455447430667, 0.7627090551771494 ], "candidate": 7.347177593044079, "control": 5.624974922520549 } } } }, { "name": "float16_256x1009", "dtype": "float16", "batches": 256, "width": 1009, "status": "measured", "variant": { "name": "register2_striped", "elements_per_thread": 2, "layout": "striped" }, "input_sha256": "3fe4b7685e23d624bcb19d6442cc8d72636943e6c185f3b0049a2ac1e0b63d81", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 511;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 512;\n int _metile_register_index_ = int(_metile_register_packed_);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n threadgroup float _metile_register_reduction[16];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 16u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n}", "source_sha256": "6b537a48d161d28743d3b80a917a7b5c4532cf32e542d68bd7d3a3e00bbe03ab", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 512, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 512, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 2 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 16, "bytes": 64 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 2, "threads": 512, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 582, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 206.4995, "control": 208.188, "speedup": 1.008176775246429 }, "gpu_us": { "candidate": 5.875015631318092, "control": 5.583337042480707, "speedup": 0.9503527127174731 } } }, { "frozen_register4": { "pairs": 574, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 209.35399999999998, "control": 204.958, "speedup": 0.9790020730437442 }, "gpu_us": { "candidate": 5.9166341088712215, "control": 5.583337042480707, "speedup": 0.9436677914744164 } } }, { "frozen_register4": { "pairs": 521, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 210.958, "control": 212.583, "speedup": 1.0077029550905867 }, "gpu_us": { "candidate": 5.958310794085264, "control": 5.62501372769475, "speedup": 0.9440618192120199 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9982001038957292, "round_speedups": [ 1.008176775246429, 0.9790020730437442, 1.0077029550905867 ], "candidate": 208.9290144627768, "control": 208.55296394357623 }, "gpu_us": { "speedup": 0.9460224910799342, "round_speedups": [ 0.9503527127174731, 0.9436677914744164, 0.9440618192120199 ], "candidate": 5.916555790403222, "control": 5.597194847450666 } } } }, { "name": "float16_256x1009", "dtype": "float16", "batches": 256, "width": 1009, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "3fe4b7685e23d624bcb19d6442cc8d72636943e6c185f3b0049a2ac1e0b63d81", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "ca8204464d79c2fc321323a988388e3cf7608e7f4edfce8846896960ec8dd552", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 543, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 211.083, "control": 212.208, "speedup": 1.005329657054334 }, "gpu_us": { "candidate": 5.499983672052622, "control": 5.62501372769475, "speedup": 1.022732804876758 } } }, { "frozen_register4": { "pairs": 560, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.08350000000002, "control": 210.41649999999998, "speedup": 1.031031416062543 }, "gpu_us": { "candidate": 5.41668850928545, "control": 5.583337042480707, "speedup": 1.0307657589890176 } } }, { "frozen_register4": { "pairs": 579, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 206.416, "control": 207.417, "speedup": 1.0048494302767228 }, "gpu_us": { "candidate": 5.458306986838579, "control": 5.583337042480707, "speedup": 1.022906380301366 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0136634669647118, "round_speedups": [ 1.005329657054334, 1.031031416062543, 1.0048494302767228 ], "candidate": 207.17380216308314, "control": 210.0045145648923 }, "gpu_us": { "speedup": 1.0254614825088542, "round_speedups": [ 1.022732804876758, 1.0307657589890176, 1.022906380301366 ], "candidate": 5.458220462612389, "control": 5.597194847450666 } } } }, { "name": "float16_256x1009", "dtype": "float16", "batches": 256, "width": 1009, "status": "measured", "variant": { "name": "register4_blocked4", "elements_per_thread": 4, "layout": "blocked4" }, "input_sha256": "3fe4b7685e23d624bcb19d6442cc8d72636943e6c185f3b0049a2ac1e0b63d81", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int((((_metile_bounded_thread >> 8) & 1u) << 0) | (((_metile_bounded_thread >> 9) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 6) & 1u) << 8) | (((_metile_bounded_thread >> 7) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 8) & 1u) << 0) | (((_metile_register_packed_ >> 9) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 6) & 1u) << 8) | (((_metile_register_packed_ >> 7) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 8) & 1u) << 0) | (((_metile_register_packed__ >> 9) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 6) & 1u) << 8) | (((_metile_register_packed__ >> 7) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 8) & 1u) << 0) | (((_metile_register_packed___ >> 9) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 6) & 1u) << 8) | (((_metile_register_packed___ >> 7) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = half4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n half _metile_v20_r0 = _metile_vector_load[0];\n half _metile_v20_r1 = _metile_vector_load[1];\n half _metile_v20_r2 = _metile_vector_load[2];\n half _metile_v20_r3 = _metile_vector_load[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half4 _metile_vector_load_;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load_ = half4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load_[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load_[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load_[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load_[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n half _metile_v36_r0 = _metile_vector_load_[0];\n half _metile_v36_r1 = _metile_vector_load_[1];\n half _metile_v36_r2 = _metile_vector_load_[2];\n half _metile_v36_r3 = _metile_vector_load_[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_half4(half4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n}", "source_sha256": "32e68c0449ebffcd9bddb41f7a561299b60a076baf9a7d4067b0b3e1392256c7", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 2, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 2, "grouped_stores": 1 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 580, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 209.14600000000002, "control": 208.6045, "speedup": 0.9974108995629847 }, "gpu_us": { "candidate": 6.375019438564777, "control": 5.5416603572666645, "speedup": 0.8692774054527858 } } }, { "frozen_register4": { "pairs": 579, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 210.667, "control": 207.458, "speedup": 0.9847674291654601 }, "gpu_us": { "candidate": 6.375019438564777, "control": 5.5416603572666645, "speedup": 0.8692774054527858 } } }, { "frozen_register4": { "pairs": 509, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 216.667, "control": 215.417, "speedup": 0.9942307781064952 }, "gpu_us": { "candidate": 6.458372808992863, "control": 5.62501372769475, "speedup": 0.8709645438650252 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9921218088046448, "round_speedups": [ 0.9974108995629847, 0.9847674291654601, 0.9942307781064952 ], "candidate": 212.13530262759855, "control": 210.464060154214 }, "gpu_us": { "speedup": 0.8698394214836354, "round_speedups": [ 0.8692774054527858, 0.8692774054527858, 0.8709645438650252 ], "candidate": 6.402683673480677, "control": 5.569306662483149 } } } }, { "name": "float16_1x1024", "dtype": "float16", "batches": 1, "width": 1024, "status": "measured", "variant": { "name": "register8_blocked4", "elements_per_thread": 8, "layout": "blocked4" }, "input_sha256": "3cc059cb43f2d2ee6f0120b1b81a1fb6efa6af199ab539eb734dc561564c6ebe", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 127;\n int _metile_register_index = int((((_metile_bounded_thread >> 7) & 1u) << 0) | (((_metile_bounded_thread >> 8) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 6) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 128;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 7) & 1u) << 0) | (((_metile_register_packed_ >> 8) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 6) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 256;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 7) & 1u) << 0) | (((_metile_register_packed__ >> 8) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 6) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 384;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 7) & 1u) << 0) | (((_metile_register_packed___ >> 8) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 6) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 512;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 7) & 1u) << 0) | (((_metile_register_packed____ >> 8) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 5) & 1u) << 7) | (((_metile_register_packed____ >> 6) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 640;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 7) & 1u) << 0) | (((_metile_register_packed_____ >> 8) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 5) & 1u) << 7) | (((_metile_register_packed_____ >> 6) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 768;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 7) & 1u) << 0) | (((_metile_register_packed______ >> 8) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 5) & 1u) << 7) | (((_metile_register_packed______ >> 6) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 896;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 7) & 1u) << 0) | (((_metile_register_packed_______ >> 8) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 5) & 1u) << 7) | (((_metile_register_packed_______ >> 6) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n half4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = half4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n half _metile_v20_r0 = _metile_vector_load[0];\n half _metile_v20_r1 = _metile_vector_load[1];\n half _metile_v20_r2 = _metile_vector_load[2];\n half _metile_v20_r3 = _metile_vector_load[3];\n half4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = half4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n half _metile_v20_r4 = _metile_vector_load_[0];\n half _metile_v20_r5 = _metile_vector_load_[1];\n half _metile_v20_r6 = _metile_vector_load_[2];\n half _metile_v20_r7 = _metile_vector_load_[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_____ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum______ = _metile_register_sum____ + _metile_register_sum_____;\n threadgroup float _metile_register_reduction[4];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 4u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n half4 _metile_vector_load__;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load__ = half4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load__[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load__[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load__[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load__[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n half _metile_v36_r0 = _metile_vector_load__[0];\n half _metile_v36_r1 = _metile_vector_load__[1];\n half _metile_v36_r2 = _metile_vector_load__[2];\n half _metile_v36_r3 = _metile_vector_load__[3];\n half4 _metile_vector_load___;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load___ = half4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load___[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load___[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load___[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load___[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n half _metile_v36_r4 = _metile_vector_load___[0];\n half _metile_v36_r5 = _metile_vector_load___[1];\n half _metile_v36_r6 = _metile_vector_load___[2];\n half _metile_v36_r7 = _metile_vector_load___[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_half4(half4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_half4(half4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n}", "source_sha256": "0795515dc02028985d5e8efef00cea1dcab53425817a6bcfdff5ade2f974789f", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 128, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 128, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 8 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 4, "bytes": 16 } ], "double_buffered": false, "vectorized_loads": 4, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 8, "threads": 128, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 4, "grouped_stores": 2 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 691, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.291, "control": 204.833, "speedup": 1.0026530782070673 }, "gpu_us": { "candidate": 1.8749851733446121, "control": 1.6249832697212696, "speedup": 0.8666645970445797 } } }, { "frozen_register4": { "pairs": 547, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.958, "control": 205.958, "speedup": 1.004879048390402 }, "gpu_us": { "candidate": 1.8749851733446121, "control": 1.5833647921681404, "speedup": 0.8444679001614305 } } }, { "frozen_register4": { "pairs": 623, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.417, "control": 199.542, "speedup": 1.005669877077065 }, "gpu_us": { "candidate": 1.833366695791483, "control": 1.5416881069540977, "speedup": 0.840905483061879 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.00439985547894, "round_speedups": [ 1.0026530782070673, 1.004879048390402, 1.005669877077065 ], "candidate": 202.53387062745955, "control": 203.42499038781074 }, "gpu_us": { "speedup": 0.850603428265127, "round_speedups": [ 0.8666645970445797, 0.8444679001614305, 0.840905483061879 ], "candidate": 1.8610084190664096, "control": 1.5829801412881521 } } } }, { "name": "float16_1x1024", "dtype": "float16", "batches": 1, "width": 1024, "status": "measured", "variant": { "name": "register16_striped", "elements_per_thread": 16, "layout": "striped" }, "input_sha256": "3cc059cb43f2d2ee6f0120b1b81a1fb6efa6af199ab539eb734dc561564c6ebe", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 63;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 64;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 128;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 192;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 256;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 320;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 384;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 448;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n int _metile_register_packed________ = _metile_bounded_thread + 512;\n int _metile_register_index________ = int(_metile_register_packed________);\n int _metile_register_packed_________ = _metile_bounded_thread + 576;\n int _metile_register_index_________ = int(_metile_register_packed_________);\n int _metile_register_packed__________ = _metile_bounded_thread + 640;\n int _metile_register_index__________ = int(_metile_register_packed__________);\n int _metile_register_packed___________ = _metile_bounded_thread + 704;\n int _metile_register_index___________ = int(_metile_register_packed___________);\n int _metile_register_packed____________ = _metile_bounded_thread + 768;\n int _metile_register_index____________ = int(_metile_register_packed____________);\n int _metile_register_packed_____________ = _metile_bounded_thread + 832;\n int _metile_register_index_____________ = int(_metile_register_packed_____________);\n int _metile_register_packed______________ = _metile_bounded_thread + 896;\n int _metile_register_index______________ = int(_metile_register_packed______________);\n int _metile_register_packed_______________ = _metile_bounded_thread + 960;\n int _metile_register_index_______________ = int(_metile_register_packed_______________);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v17_r8 = _metile_register_index________ < 1024;\n bool _metile_v17_r9 = _metile_register_index_________ < 1024;\n bool _metile_v17_r10 = _metile_register_index__________ < 1024;\n bool _metile_v17_r11 = _metile_register_index___________ < 1024;\n bool _metile_v17_r12 = _metile_register_index____________ < 1024;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v17_r14 = _metile_register_index______________ < 1024;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n half _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n half _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n half _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n half _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n half _metile_v20_r8 = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n half _metile_v20_r9 = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n half _metile_v20_r10 = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n half _metile_v20_r11 = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n half _metile_v20_r12 = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n half _metile_v20_r13 = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n half _metile_v20_r14 = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n half _metile_v20_r15 = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________ = _metile_register_sum____________ + _metile_register_sum_____________;\n threadgroup float _metile_register_reduction[2];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______________);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 2u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v33_r8 = _metile_register_index________ < 1024;\n bool _metile_v33_r9 = _metile_register_index_________ < 1024;\n bool _metile_v33_r10 = _metile_register_index__________ < 1024;\n bool _metile_v33_r11 = _metile_register_index___________ < 1024;\n bool _metile_v33_r12 = _metile_register_index____________ < 1024;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v33_r14 = _metile_register_index______________ < 1024;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n half _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n half _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n half _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n half _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n half _metile_v36_r8 = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n half _metile_v36_r9 = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n half _metile_v36_r10 = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n half _metile_v36_r11 = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n half _metile_v36_r12 = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n half _metile_v36_r13 = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n half _metile_v36_r14 = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n half _metile_v36_r15 = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v42_r8 = _metile_register_index________ < 1024;\n bool _metile_v42_r9 = _metile_register_index_________ < 1024;\n bool _metile_v42_r10 = _metile_register_index__________ < 1024;\n bool _metile_v42_r11 = _metile_register_index___________ < 1024;\n bool _metile_v42_r12 = _metile_register_index____________ < 1024;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v42_r14 = _metile_register_index______________ < 1024;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = _metile_v39_r8; }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = _metile_v39_r9; }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = _metile_v39_r10; }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = _metile_v39_r11; }\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = _metile_v39_r12; }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = _metile_v39_r13; }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = _metile_v39_r14; }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = _metile_v39_r15; }\n}", "source_sha256": "80e4ab993c9dda4e9764e5d0ae2ad910cd88a101c3d4ec77af99d486d6933bdb", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 64, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 64, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 16 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 2, "bytes": 8 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 16, "threads": 64, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 614, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.8955, "control": 198.66649999999998, "speedup": 0.998848641623365 }, "gpu_us": { "candidate": 1.7500133253633976, "control": 1.5416881069540977, "speedup": 0.8809579244969233 } } }, { "frozen_register4": { "pairs": 612, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.60399999999998, "control": 199.77100000000002, "speedup": 1.0109663771988422 }, "gpu_us": { "candidate": 1.7500133253633976, "control": 1.5416881069540977, "speedup": 0.8809579244969233 } } }, { "frozen_register4": { "pairs": 610, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.5, "control": 199.83350000000002, "speedup": 0.9966758104738155 }, "gpu_us": { "candidate": 1.7500133253633976, "control": 1.5416881069540977, "speedup": 0.8809579244969233 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0021439395898413, "round_speedups": [ 0.998848641623365, 1.0109663771988422, 0.9966758104738155 ], "candidate": 198.99630936474205, "control": 199.42294543062144 }, "gpu_us": { "speedup": 0.8809579244969233, "round_speedups": [ 0.8809579244969233, 0.8809579244969233, 0.8809579244969233 ], "candidate": 1.7500133253633976, "control": 1.5416881069540977 } } } }, { "name": "float16_1x1024", "dtype": "float16", "batches": 1, "width": 1024, "status": "measured", "variant": { "name": "register16_blocked4", "elements_per_thread": 16, "layout": "blocked4" }, "input_sha256": "3cc059cb43f2d2ee6f0120b1b81a1fb6efa6af199ab539eb734dc561564c6ebe", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 63;\n int _metile_register_index = int((((_metile_bounded_thread >> 6) & 1u) << 0) | (((_metile_bounded_thread >> 7) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 8) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 64;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 6) & 1u) << 0) | (((_metile_register_packed_ >> 7) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 8) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 128;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 6) & 1u) << 0) | (((_metile_register_packed__ >> 7) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 8) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 192;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 6) & 1u) << 0) | (((_metile_register_packed___ >> 7) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 8) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 256;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 6) & 1u) << 0) | (((_metile_register_packed____ >> 7) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 5) & 1u) << 7) | (((_metile_register_packed____ >> 8) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 320;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 6) & 1u) << 0) | (((_metile_register_packed_____ >> 7) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 5) & 1u) << 7) | (((_metile_register_packed_____ >> 8) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 384;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 6) & 1u) << 0) | (((_metile_register_packed______ >> 7) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 5) & 1u) << 7) | (((_metile_register_packed______ >> 8) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 448;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 6) & 1u) << 0) | (((_metile_register_packed_______ >> 7) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 5) & 1u) << 7) | (((_metile_register_packed_______ >> 8) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n int _metile_register_packed________ = _metile_bounded_thread + 512;\n int _metile_register_index________ = int((((_metile_register_packed________ >> 6) & 1u) << 0) | (((_metile_register_packed________ >> 7) & 1u) << 1) | (((_metile_register_packed________ >> 0) & 1u) << 2) | (((_metile_register_packed________ >> 1) & 1u) << 3) | (((_metile_register_packed________ >> 2) & 1u) << 4) | (((_metile_register_packed________ >> 3) & 1u) << 5) | (((_metile_register_packed________ >> 4) & 1u) << 6) | (((_metile_register_packed________ >> 5) & 1u) << 7) | (((_metile_register_packed________ >> 8) & 1u) << 8) | (((_metile_register_packed________ >> 9) & 1u) << 9));\n int _metile_register_packed_________ = _metile_bounded_thread + 576;\n int _metile_register_index_________ = int((((_metile_register_packed_________ >> 6) & 1u) << 0) | (((_metile_register_packed_________ >> 7) & 1u) << 1) | (((_metile_register_packed_________ >> 0) & 1u) << 2) | (((_metile_register_packed_________ >> 1) & 1u) << 3) | (((_metile_register_packed_________ >> 2) & 1u) << 4) | (((_metile_register_packed_________ >> 3) & 1u) << 5) | (((_metile_register_packed_________ >> 4) & 1u) << 6) | (((_metile_register_packed_________ >> 5) & 1u) << 7) | (((_metile_register_packed_________ >> 8) & 1u) << 8) | (((_metile_register_packed_________ >> 9) & 1u) << 9));\n int _metile_register_packed__________ = _metile_bounded_thread + 640;\n int _metile_register_index__________ = int((((_metile_register_packed__________ >> 6) & 1u) << 0) | (((_metile_register_packed__________ >> 7) & 1u) << 1) | (((_metile_register_packed__________ >> 0) & 1u) << 2) | (((_metile_register_packed__________ >> 1) & 1u) << 3) | (((_metile_register_packed__________ >> 2) & 1u) << 4) | (((_metile_register_packed__________ >> 3) & 1u) << 5) | (((_metile_register_packed__________ >> 4) & 1u) << 6) | (((_metile_register_packed__________ >> 5) & 1u) << 7) | (((_metile_register_packed__________ >> 8) & 1u) << 8) | (((_metile_register_packed__________ >> 9) & 1u) << 9));\n int _metile_register_packed___________ = _metile_bounded_thread + 704;\n int _metile_register_index___________ = int((((_metile_register_packed___________ >> 6) & 1u) << 0) | (((_metile_register_packed___________ >> 7) & 1u) << 1) | (((_metile_register_packed___________ >> 0) & 1u) << 2) | (((_metile_register_packed___________ >> 1) & 1u) << 3) | (((_metile_register_packed___________ >> 2) & 1u) << 4) | (((_metile_register_packed___________ >> 3) & 1u) << 5) | (((_metile_register_packed___________ >> 4) & 1u) << 6) | (((_metile_register_packed___________ >> 5) & 1u) << 7) | (((_metile_register_packed___________ >> 8) & 1u) << 8) | (((_metile_register_packed___________ >> 9) & 1u) << 9));\n int _metile_register_packed____________ = _metile_bounded_thread + 768;\n int _metile_register_index____________ = int((((_metile_register_packed____________ >> 6) & 1u) << 0) | (((_metile_register_packed____________ >> 7) & 1u) << 1) | (((_metile_register_packed____________ >> 0) & 1u) << 2) | (((_metile_register_packed____________ >> 1) & 1u) << 3) | (((_metile_register_packed____________ >> 2) & 1u) << 4) | (((_metile_register_packed____________ >> 3) & 1u) << 5) | (((_metile_register_packed____________ >> 4) & 1u) << 6) | (((_metile_register_packed____________ >> 5) & 1u) << 7) | (((_metile_register_packed____________ >> 8) & 1u) << 8) | (((_metile_register_packed____________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________ = _metile_bounded_thread + 832;\n int _metile_register_index_____________ = int((((_metile_register_packed_____________ >> 6) & 1u) << 0) | (((_metile_register_packed_____________ >> 7) & 1u) << 1) | (((_metile_register_packed_____________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________ >> 5) & 1u) << 7) | (((_metile_register_packed_____________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________ >> 9) & 1u) << 9));\n int _metile_register_packed______________ = _metile_bounded_thread + 896;\n int _metile_register_index______________ = int((((_metile_register_packed______________ >> 6) & 1u) << 0) | (((_metile_register_packed______________ >> 7) & 1u) << 1) | (((_metile_register_packed______________ >> 0) & 1u) << 2) | (((_metile_register_packed______________ >> 1) & 1u) << 3) | (((_metile_register_packed______________ >> 2) & 1u) << 4) | (((_metile_register_packed______________ >> 3) & 1u) << 5) | (((_metile_register_packed______________ >> 4) & 1u) << 6) | (((_metile_register_packed______________ >> 5) & 1u) << 7) | (((_metile_register_packed______________ >> 8) & 1u) << 8) | (((_metile_register_packed______________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________ = _metile_bounded_thread + 960;\n int _metile_register_index_______________ = int((((_metile_register_packed_______________ >> 6) & 1u) << 0) | (((_metile_register_packed_______________ >> 7) & 1u) << 1) | (((_metile_register_packed_______________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________ >> 5) & 1u) << 7) | (((_metile_register_packed_______________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v17_r8 = _metile_register_index________ < 1024;\n bool _metile_v17_r9 = _metile_register_index_________ < 1024;\n bool _metile_v17_r10 = _metile_register_index__________ < 1024;\n bool _metile_v17_r11 = _metile_register_index___________ < 1024;\n bool _metile_v17_r12 = _metile_register_index____________ < 1024;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v17_r14 = _metile_register_index______________ < 1024;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n half4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = half4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n half _metile_v20_r0 = _metile_vector_load[0];\n half _metile_v20_r1 = _metile_vector_load[1];\n half _metile_v20_r2 = _metile_vector_load[2];\n half _metile_v20_r3 = _metile_vector_load[3];\n half4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = half4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n half _metile_v20_r4 = _metile_vector_load_[0];\n half _metile_v20_r5 = _metile_vector_load_[1];\n half _metile_v20_r6 = _metile_vector_load_[2];\n half _metile_v20_r7 = _metile_vector_load_[3];\n half4 _metile_vector_load__;\n if ((_metile_v18_r8) && (_metile_v18_r9) && (_metile_v18_r10) && (_metile_v18_r11) && (long(_off__metile_v19_r9) == long(_off__metile_v19_r8) + 1) && (long(_off__metile_v19_r10) == long(_off__metile_v19_r8) + 2) && (long(_off__metile_v19_r11) == long(_off__metile_v19_r8) + 3)) {\n _metile_vector_load__ = half4(*reinterpret_cast(X + _off__metile_v19_r8));\n } else {\n _metile_vector_load__[0] = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n _metile_vector_load__[1] = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n _metile_vector_load__[2] = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n _metile_vector_load__[3] = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n }\n half _metile_v20_r8 = _metile_vector_load__[0];\n half _metile_v20_r9 = _metile_vector_load__[1];\n half _metile_v20_r10 = _metile_vector_load__[2];\n half _metile_v20_r11 = _metile_vector_load__[3];\n half4 _metile_vector_load___;\n if ((_metile_v18_r12) && (_metile_v18_r13) && (_metile_v18_r14) && (_metile_v18_r15) && (long(_off__metile_v19_r13) == long(_off__metile_v19_r12) + 1) && (long(_off__metile_v19_r14) == long(_off__metile_v19_r12) + 2) && (long(_off__metile_v19_r15) == long(_off__metile_v19_r12) + 3)) {\n _metile_vector_load___ = half4(*reinterpret_cast(X + _off__metile_v19_r12));\n } else {\n _metile_vector_load___[0] = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n _metile_vector_load___[1] = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n _metile_vector_load___[2] = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n _metile_vector_load___[3] = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n }\n half _metile_v20_r12 = _metile_vector_load___[0];\n half _metile_v20_r13 = _metile_vector_load___[1];\n half _metile_v20_r14 = _metile_vector_load___[2];\n half _metile_v20_r15 = _metile_vector_load___[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________ = _metile_register_sum____________ + _metile_register_sum_____________;\n threadgroup float _metile_register_reduction[2];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______________);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 2u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v33_r8 = _metile_register_index________ < 1024;\n bool _metile_v33_r9 = _metile_register_index_________ < 1024;\n bool _metile_v33_r10 = _metile_register_index__________ < 1024;\n bool _metile_v33_r11 = _metile_register_index___________ < 1024;\n bool _metile_v33_r12 = _metile_register_index____________ < 1024;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v33_r14 = _metile_register_index______________ < 1024;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n half4 _metile_vector_load____;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load____ = half4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load____[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load____[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load____[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load____[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n half _metile_v36_r0 = _metile_vector_load____[0];\n half _metile_v36_r1 = _metile_vector_load____[1];\n half _metile_v36_r2 = _metile_vector_load____[2];\n half _metile_v36_r3 = _metile_vector_load____[3];\n half4 _metile_vector_load_____;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load_____ = half4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load_____[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load_____[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load_____[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load_____[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n half _metile_v36_r4 = _metile_vector_load_____[0];\n half _metile_v36_r5 = _metile_vector_load_____[1];\n half _metile_v36_r6 = _metile_vector_load_____[2];\n half _metile_v36_r7 = _metile_vector_load_____[3];\n half4 _metile_vector_load______;\n if ((_metile_v34_r8) && (_metile_v34_r9) && (_metile_v34_r10) && (_metile_v34_r11) && (long(_metile_register_index_________) == long(_metile_register_index________) + 1) && (long(_metile_register_index__________) == long(_metile_register_index________) + 2) && (long(_metile_register_index___________) == long(_metile_register_index________) + 3)) {\n _metile_vector_load______ = half4(*reinterpret_cast(W + _metile_register_index________));\n } else {\n _metile_vector_load______[0] = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n _metile_vector_load______[1] = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n _metile_vector_load______[2] = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n _metile_vector_load______[3] = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n }\n half _metile_v36_r8 = _metile_vector_load______[0];\n half _metile_v36_r9 = _metile_vector_load______[1];\n half _metile_v36_r10 = _metile_vector_load______[2];\n half _metile_v36_r11 = _metile_vector_load______[3];\n half4 _metile_vector_load_______;\n if ((_metile_v34_r12) && (_metile_v34_r13) && (_metile_v34_r14) && (_metile_v34_r15) && (long(_metile_register_index_____________) == long(_metile_register_index____________) + 1) && (long(_metile_register_index______________) == long(_metile_register_index____________) + 2) && (long(_metile_register_index_______________) == long(_metile_register_index____________) + 3)) {\n _metile_vector_load_______ = half4(*reinterpret_cast(W + _metile_register_index____________));\n } else {\n _metile_vector_load_______[0] = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n _metile_vector_load_______[1] = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n _metile_vector_load_______[2] = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n _metile_vector_load_______[3] = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n }\n half _metile_v36_r12 = _metile_vector_load_______[0];\n half _metile_v36_r13 = _metile_vector_load_______[1];\n half _metile_v36_r14 = _metile_vector_load_______[2];\n half _metile_v36_r15 = _metile_vector_load_______[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v42_r8 = _metile_register_index________ < 1024;\n bool _metile_v42_r9 = _metile_register_index_________ < 1024;\n bool _metile_v42_r10 = _metile_register_index__________ < 1024;\n bool _metile_v42_r11 = _metile_register_index___________ < 1024;\n bool _metile_v42_r12 = _metile_register_index____________ < 1024;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v42_r14 = _metile_register_index______________ < 1024;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_half4(half4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_half4(half4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n if ((_metile_v43_r8) && (_metile_v43_r9) && (_metile_v43_r10) && (_metile_v43_r11) && (long(_off__metile_v44_r9) == long(_off__metile_v44_r8) + 1) && (long(_off__metile_v44_r10) == long(_off__metile_v44_r8) + 2) && (long(_off__metile_v44_r11) == long(_off__metile_v44_r8) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r8) = packed_half4(half4(static_cast(_metile_v39_r8), static_cast(_metile_v39_r9), static_cast(_metile_v39_r10), static_cast(_metile_v39_r11)));\n } else {\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = static_cast(_metile_v39_r8); }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = static_cast(_metile_v39_r9); }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = static_cast(_metile_v39_r10); }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = static_cast(_metile_v39_r11); }\n }\n if ((_metile_v43_r12) && (_metile_v43_r13) && (_metile_v43_r14) && (_metile_v43_r15) && (long(_off__metile_v44_r13) == long(_off__metile_v44_r12) + 1) && (long(_off__metile_v44_r14) == long(_off__metile_v44_r12) + 2) && (long(_off__metile_v44_r15) == long(_off__metile_v44_r12) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r12) = packed_half4(half4(static_cast(_metile_v39_r12), static_cast(_metile_v39_r13), static_cast(_metile_v39_r14), static_cast(_metile_v39_r15)));\n } else {\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = static_cast(_metile_v39_r12); }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = static_cast(_metile_v39_r13); }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = static_cast(_metile_v39_r14); }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = static_cast(_metile_v39_r15); }\n }\n}", "source_sha256": "fd2a997847283829837787e56478df38b489706b6dd7fc7e98f217fcdab4f642", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 64, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 64, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 16 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 2, "bytes": 8 } ], "double_buffered": false, "vectorized_loads": 8, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 16, "threads": 64, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 8, "grouped_stores": 4 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 611, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.0, "control": 200.125, "speedup": 1.0056532663316582 }, "gpu_us": { "candidate": 2.374988980591297, "control": 1.5416881069540977, "speedup": 0.6491348463310622 } } }, { "frozen_register4": { "pairs": 611, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.291, "control": 200.041, "speedup": 1.008825413155413 }, "gpu_us": { "candidate": 2.374988980591297, "control": 1.5416881069540977, "speedup": 0.6491348463310622 } } }, { "frozen_register4": { "pairs": 615, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.916, "control": 198.875, "speedup": 0.99979388284502 }, "gpu_us": { "candidate": 2.374988980591297, "control": 1.5416881069540977, "speedup": 0.6491348463310622 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.004750549924131, "round_speedups": [ 1.0056532663316582, 1.008825413155413, 0.99979388284502 ], "candidate": 198.73541479578952, "control": 199.67951730546983 }, "gpu_us": { "speedup": 0.6491348463310622, "round_speedups": [ 0.6491348463310622, 0.6491348463310622, 0.6491348463310622 ], "candidate": 2.374988980591297, "control": 1.5416881069540977 } } } }, { "name": "float16_1x1024", "dtype": "float16", "batches": 1, "width": 1024, "status": "measured", "variant": { "name": "register32_striped", "elements_per_thread": 32, "layout": "striped" }, "input_sha256": "3cc059cb43f2d2ee6f0120b1b81a1fb6efa6af199ab539eb734dc561564c6ebe", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 31;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 32;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 64;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 96;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 128;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 160;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 192;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 224;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n int _metile_register_packed________ = _metile_bounded_thread + 256;\n int _metile_register_index________ = int(_metile_register_packed________);\n int _metile_register_packed_________ = _metile_bounded_thread + 288;\n int _metile_register_index_________ = int(_metile_register_packed_________);\n int _metile_register_packed__________ = _metile_bounded_thread + 320;\n int _metile_register_index__________ = int(_metile_register_packed__________);\n int _metile_register_packed___________ = _metile_bounded_thread + 352;\n int _metile_register_index___________ = int(_metile_register_packed___________);\n int _metile_register_packed____________ = _metile_bounded_thread + 384;\n int _metile_register_index____________ = int(_metile_register_packed____________);\n int _metile_register_packed_____________ = _metile_bounded_thread + 416;\n int _metile_register_index_____________ = int(_metile_register_packed_____________);\n int _metile_register_packed______________ = _metile_bounded_thread + 448;\n int _metile_register_index______________ = int(_metile_register_packed______________);\n int _metile_register_packed_______________ = _metile_bounded_thread + 480;\n int _metile_register_index_______________ = int(_metile_register_packed_______________);\n int _metile_register_packed________________ = _metile_bounded_thread + 512;\n int _metile_register_index________________ = int(_metile_register_packed________________);\n int _metile_register_packed_________________ = _metile_bounded_thread + 544;\n int _metile_register_index_________________ = int(_metile_register_packed_________________);\n int _metile_register_packed__________________ = _metile_bounded_thread + 576;\n int _metile_register_index__________________ = int(_metile_register_packed__________________);\n int _metile_register_packed___________________ = _metile_bounded_thread + 608;\n int _metile_register_index___________________ = int(_metile_register_packed___________________);\n int _metile_register_packed____________________ = _metile_bounded_thread + 640;\n int _metile_register_index____________________ = int(_metile_register_packed____________________);\n int _metile_register_packed_____________________ = _metile_bounded_thread + 672;\n int _metile_register_index_____________________ = int(_metile_register_packed_____________________);\n int _metile_register_packed______________________ = _metile_bounded_thread + 704;\n int _metile_register_index______________________ = int(_metile_register_packed______________________);\n int _metile_register_packed_______________________ = _metile_bounded_thread + 736;\n int _metile_register_index_______________________ = int(_metile_register_packed_______________________);\n int _metile_register_packed________________________ = _metile_bounded_thread + 768;\n int _metile_register_index________________________ = int(_metile_register_packed________________________);\n int _metile_register_packed_________________________ = _metile_bounded_thread + 800;\n int _metile_register_index_________________________ = int(_metile_register_packed_________________________);\n int _metile_register_packed__________________________ = _metile_bounded_thread + 832;\n int _metile_register_index__________________________ = int(_metile_register_packed__________________________);\n int _metile_register_packed___________________________ = _metile_bounded_thread + 864;\n int _metile_register_index___________________________ = int(_metile_register_packed___________________________);\n int _metile_register_packed____________________________ = _metile_bounded_thread + 896;\n int _metile_register_index____________________________ = int(_metile_register_packed____________________________);\n int _metile_register_packed_____________________________ = _metile_bounded_thread + 928;\n int _metile_register_index_____________________________ = int(_metile_register_packed_____________________________);\n int _metile_register_packed______________________________ = _metile_bounded_thread + 960;\n int _metile_register_index______________________________ = int(_metile_register_packed______________________________);\n int _metile_register_packed_______________________________ = _metile_bounded_thread + 992;\n int _metile_register_index_______________________________ = int(_metile_register_packed_______________________________);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v16_r16 = _metile_register_index________________ >= 0;\n bool _metile_v16_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v16_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v16_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v16_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v16_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v16_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v16_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v16_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v16_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v16_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v16_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v16_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v16_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v16_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v16_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v17_r8 = _metile_register_index________ < 1024;\n bool _metile_v17_r9 = _metile_register_index_________ < 1024;\n bool _metile_v17_r10 = _metile_register_index__________ < 1024;\n bool _metile_v17_r11 = _metile_register_index___________ < 1024;\n bool _metile_v17_r12 = _metile_register_index____________ < 1024;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v17_r14 = _metile_register_index______________ < 1024;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v17_r16 = _metile_register_index________________ < 1024;\n bool _metile_v17_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v17_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v17_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v17_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v17_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v17_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v17_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v17_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v17_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v17_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v17_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v17_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v17_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v17_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v17_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n bool _metile_v18_r16 = _metile_v16_r16 & _metile_v17_r16;\n bool _metile_v18_r17 = _metile_v16_r17 & _metile_v17_r17;\n bool _metile_v18_r18 = _metile_v16_r18 & _metile_v17_r18;\n bool _metile_v18_r19 = _metile_v16_r19 & _metile_v17_r19;\n bool _metile_v18_r20 = _metile_v16_r20 & _metile_v17_r20;\n bool _metile_v18_r21 = _metile_v16_r21 & _metile_v17_r21;\n bool _metile_v18_r22 = _metile_v16_r22 & _metile_v17_r22;\n bool _metile_v18_r23 = _metile_v16_r23 & _metile_v17_r23;\n bool _metile_v18_r24 = _metile_v16_r24 & _metile_v17_r24;\n bool _metile_v18_r25 = _metile_v16_r25 & _metile_v17_r25;\n bool _metile_v18_r26 = _metile_v16_r26 & _metile_v17_r26;\n bool _metile_v18_r27 = _metile_v16_r27 & _metile_v17_r27;\n bool _metile_v18_r28 = _metile_v16_r28 & _metile_v17_r28;\n bool _metile_v18_r29 = _metile_v16_r29 & _metile_v17_r29;\n bool _metile_v18_r30 = _metile_v16_r30 & _metile_v17_r30;\n bool _metile_v18_r31 = _metile_v16_r31 & _metile_v17_r31;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n int _off__metile_v19_r16 = v2 + _metile_register_index________________;\n int _off__metile_v19_r17 = v2 + _metile_register_index_________________;\n int _off__metile_v19_r18 = v2 + _metile_register_index__________________;\n int _off__metile_v19_r19 = v2 + _metile_register_index___________________;\n int _off__metile_v19_r20 = v2 + _metile_register_index____________________;\n int _off__metile_v19_r21 = v2 + _metile_register_index_____________________;\n int _off__metile_v19_r22 = v2 + _metile_register_index______________________;\n int _off__metile_v19_r23 = v2 + _metile_register_index_______________________;\n int _off__metile_v19_r24 = v2 + _metile_register_index________________________;\n int _off__metile_v19_r25 = v2 + _metile_register_index_________________________;\n int _off__metile_v19_r26 = v2 + _metile_register_index__________________________;\n int _off__metile_v19_r27 = v2 + _metile_register_index___________________________;\n int _off__metile_v19_r28 = v2 + _metile_register_index____________________________;\n int _off__metile_v19_r29 = v2 + _metile_register_index_____________________________;\n int _off__metile_v19_r30 = v2 + _metile_register_index______________________________;\n int _off__metile_v19_r31 = v2 + _metile_register_index_______________________________;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n half _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n half _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n half _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n half _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n half _metile_v20_r8 = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n half _metile_v20_r9 = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n half _metile_v20_r10 = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n half _metile_v20_r11 = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n half _metile_v20_r12 = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n half _metile_v20_r13 = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n half _metile_v20_r14 = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n half _metile_v20_r15 = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n half _metile_v20_r16 = _metile_v18_r16 ? X[_off__metile_v19_r16] : static_cast(0);\n half _metile_v20_r17 = _metile_v18_r17 ? X[_off__metile_v19_r17] : static_cast(0);\n half _metile_v20_r18 = _metile_v18_r18 ? X[_off__metile_v19_r18] : static_cast(0);\n half _metile_v20_r19 = _metile_v18_r19 ? X[_off__metile_v19_r19] : static_cast(0);\n half _metile_v20_r20 = _metile_v18_r20 ? X[_off__metile_v19_r20] : static_cast(0);\n half _metile_v20_r21 = _metile_v18_r21 ? X[_off__metile_v19_r21] : static_cast(0);\n half _metile_v20_r22 = _metile_v18_r22 ? X[_off__metile_v19_r22] : static_cast(0);\n half _metile_v20_r23 = _metile_v18_r23 ? X[_off__metile_v19_r23] : static_cast(0);\n half _metile_v20_r24 = _metile_v18_r24 ? X[_off__metile_v19_r24] : static_cast(0);\n half _metile_v20_r25 = _metile_v18_r25 ? X[_off__metile_v19_r25] : static_cast(0);\n half _metile_v20_r26 = _metile_v18_r26 ? X[_off__metile_v19_r26] : static_cast(0);\n half _metile_v20_r27 = _metile_v18_r27 ? X[_off__metile_v19_r27] : static_cast(0);\n half _metile_v20_r28 = _metile_v18_r28 ? X[_off__metile_v19_r28] : static_cast(0);\n half _metile_v20_r29 = _metile_v18_r29 ? X[_off__metile_v19_r29] : static_cast(0);\n half _metile_v20_r30 = _metile_v18_r30 ? X[_off__metile_v19_r30] : static_cast(0);\n half _metile_v20_r31 = _metile_v18_r31 ? X[_off__metile_v19_r31] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v21_r16 = static_cast(_metile_v20_r16);\n float _metile_v21_r17 = static_cast(_metile_v20_r17);\n float _metile_v21_r18 = static_cast(_metile_v20_r18);\n float _metile_v21_r19 = static_cast(_metile_v20_r19);\n float _metile_v21_r20 = static_cast(_metile_v20_r20);\n float _metile_v21_r21 = static_cast(_metile_v20_r21);\n float _metile_v21_r22 = static_cast(_metile_v20_r22);\n float _metile_v21_r23 = static_cast(_metile_v20_r23);\n float _metile_v21_r24 = static_cast(_metile_v20_r24);\n float _metile_v21_r25 = static_cast(_metile_v20_r25);\n float _metile_v21_r26 = static_cast(_metile_v20_r26);\n float _metile_v21_r27 = static_cast(_metile_v20_r27);\n float _metile_v21_r28 = static_cast(_metile_v20_r28);\n float _metile_v21_r29 = static_cast(_metile_v20_r29);\n float _metile_v21_r30 = static_cast(_metile_v20_r30);\n float _metile_v21_r31 = static_cast(_metile_v20_r31);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_v22_r16 = _metile_v21_r16 * _metile_v21_r16;\n float _metile_v22_r17 = _metile_v21_r17 * _metile_v21_r17;\n float _metile_v22_r18 = _metile_v21_r18 * _metile_v21_r18;\n float _metile_v22_r19 = _metile_v21_r19 * _metile_v21_r19;\n float _metile_v22_r20 = _metile_v21_r20 * _metile_v21_r20;\n float _metile_v22_r21 = _metile_v21_r21 * _metile_v21_r21;\n float _metile_v22_r22 = _metile_v21_r22 * _metile_v21_r22;\n float _metile_v22_r23 = _metile_v21_r23 * _metile_v21_r23;\n float _metile_v22_r24 = _metile_v21_r24 * _metile_v21_r24;\n float _metile_v22_r25 = _metile_v21_r25 * _metile_v21_r25;\n float _metile_v22_r26 = _metile_v21_r26 * _metile_v21_r26;\n float _metile_v22_r27 = _metile_v21_r27 * _metile_v21_r27;\n float _metile_v22_r28 = _metile_v21_r28 * _metile_v21_r28;\n float _metile_v22_r29 = _metile_v21_r29 * _metile_v21_r29;\n float _metile_v22_r30 = _metile_v21_r30 * _metile_v21_r30;\n float _metile_v22_r31 = _metile_v21_r31 * _metile_v21_r31;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_v22_r16 + _metile_v22_r17;\n float _metile_register_sum_________ = _metile_v22_r18 + _metile_v22_r19;\n float _metile_register_sum__________ = _metile_v22_r20 + _metile_v22_r21;\n float _metile_register_sum___________ = _metile_v22_r22 + _metile_v22_r23;\n float _metile_register_sum____________ = _metile_v22_r24 + _metile_v22_r25;\n float _metile_register_sum_____________ = _metile_v22_r26 + _metile_v22_r27;\n float _metile_register_sum______________ = _metile_v22_r28 + _metile_v22_r29;\n float _metile_register_sum_______________ = _metile_v22_r30 + _metile_v22_r31;\n float _metile_register_sum________________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________________ = _metile_register_sum____________ + _metile_register_sum_____________;\n float _metile_register_sum_______________________ = _metile_register_sum______________ + _metile_register_sum_______________;\n float _metile_register_sum________________________ = _metile_register_sum________________ + _metile_register_sum_________________;\n float _metile_register_sum_________________________ = _metile_register_sum__________________ + _metile_register_sum___________________;\n float _metile_register_sum__________________________ = _metile_register_sum____________________ + _metile_register_sum_____________________;\n float _metile_register_sum___________________________ = _metile_register_sum______________________ + _metile_register_sum_______________________;\n float _metile_register_sum____________________________ = _metile_register_sum________________________ + _metile_register_sum_________________________;\n float _metile_register_sum_____________________________ = _metile_register_sum__________________________ + _metile_register_sum___________________________;\n float _metile_register_sum______________________________ = _metile_register_sum____________________________ + _metile_register_sum_____________________________;\n float v23 = simd_sum(_metile_register_sum______________________________);\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v32_r16 = _metile_register_index________________ >= 0;\n bool _metile_v32_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v32_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v32_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v32_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v32_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v32_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v32_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v32_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v32_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v32_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v32_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v32_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v32_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v32_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v32_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v33_r8 = _metile_register_index________ < 1024;\n bool _metile_v33_r9 = _metile_register_index_________ < 1024;\n bool _metile_v33_r10 = _metile_register_index__________ < 1024;\n bool _metile_v33_r11 = _metile_register_index___________ < 1024;\n bool _metile_v33_r12 = _metile_register_index____________ < 1024;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v33_r14 = _metile_register_index______________ < 1024;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v33_r16 = _metile_register_index________________ < 1024;\n bool _metile_v33_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v33_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v33_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v33_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v33_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v33_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v33_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v33_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v33_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v33_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v33_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v33_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v33_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v33_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v33_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n bool _metile_v34_r16 = _metile_v32_r16 & _metile_v33_r16;\n bool _metile_v34_r17 = _metile_v32_r17 & _metile_v33_r17;\n bool _metile_v34_r18 = _metile_v32_r18 & _metile_v33_r18;\n bool _metile_v34_r19 = _metile_v32_r19 & _metile_v33_r19;\n bool _metile_v34_r20 = _metile_v32_r20 & _metile_v33_r20;\n bool _metile_v34_r21 = _metile_v32_r21 & _metile_v33_r21;\n bool _metile_v34_r22 = _metile_v32_r22 & _metile_v33_r22;\n bool _metile_v34_r23 = _metile_v32_r23 & _metile_v33_r23;\n bool _metile_v34_r24 = _metile_v32_r24 & _metile_v33_r24;\n bool _metile_v34_r25 = _metile_v32_r25 & _metile_v33_r25;\n bool _metile_v34_r26 = _metile_v32_r26 & _metile_v33_r26;\n bool _metile_v34_r27 = _metile_v32_r27 & _metile_v33_r27;\n bool _metile_v34_r28 = _metile_v32_r28 & _metile_v33_r28;\n bool _metile_v34_r29 = _metile_v32_r29 & _metile_v33_r29;\n bool _metile_v34_r30 = _metile_v32_r30 & _metile_v33_r30;\n bool _metile_v34_r31 = _metile_v32_r31 & _metile_v33_r31;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n half _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n half _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n half _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n half _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n half _metile_v36_r8 = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n half _metile_v36_r9 = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n half _metile_v36_r10 = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n half _metile_v36_r11 = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n half _metile_v36_r12 = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n half _metile_v36_r13 = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n half _metile_v36_r14 = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n half _metile_v36_r15 = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n half _metile_v36_r16 = _metile_v34_r16 ? W[_metile_register_index________________] : static_cast(0);\n half _metile_v36_r17 = _metile_v34_r17 ? W[_metile_register_index_________________] : static_cast(0);\n half _metile_v36_r18 = _metile_v34_r18 ? W[_metile_register_index__________________] : static_cast(0);\n half _metile_v36_r19 = _metile_v34_r19 ? W[_metile_register_index___________________] : static_cast(0);\n half _metile_v36_r20 = _metile_v34_r20 ? W[_metile_register_index____________________] : static_cast(0);\n half _metile_v36_r21 = _metile_v34_r21 ? W[_metile_register_index_____________________] : static_cast(0);\n half _metile_v36_r22 = _metile_v34_r22 ? W[_metile_register_index______________________] : static_cast(0);\n half _metile_v36_r23 = _metile_v34_r23 ? W[_metile_register_index_______________________] : static_cast(0);\n half _metile_v36_r24 = _metile_v34_r24 ? W[_metile_register_index________________________] : static_cast(0);\n half _metile_v36_r25 = _metile_v34_r25 ? W[_metile_register_index_________________________] : static_cast(0);\n half _metile_v36_r26 = _metile_v34_r26 ? W[_metile_register_index__________________________] : static_cast(0);\n half _metile_v36_r27 = _metile_v34_r27 ? W[_metile_register_index___________________________] : static_cast(0);\n half _metile_v36_r28 = _metile_v34_r28 ? W[_metile_register_index____________________________] : static_cast(0);\n half _metile_v36_r29 = _metile_v34_r29 ? W[_metile_register_index_____________________________] : static_cast(0);\n half _metile_v36_r30 = _metile_v34_r30 ? W[_metile_register_index______________________________] : static_cast(0);\n half _metile_v36_r31 = _metile_v34_r31 ? W[_metile_register_index_______________________________] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v37_r16 = static_cast(_metile_v36_r16);\n float _metile_v37_r17 = static_cast(_metile_v36_r17);\n float _metile_v37_r18 = static_cast(_metile_v36_r18);\n float _metile_v37_r19 = static_cast(_metile_v36_r19);\n float _metile_v37_r20 = static_cast(_metile_v36_r20);\n float _metile_v37_r21 = static_cast(_metile_v36_r21);\n float _metile_v37_r22 = static_cast(_metile_v36_r22);\n float _metile_v37_r23 = static_cast(_metile_v36_r23);\n float _metile_v37_r24 = static_cast(_metile_v36_r24);\n float _metile_v37_r25 = static_cast(_metile_v36_r25);\n float _metile_v37_r26 = static_cast(_metile_v36_r26);\n float _metile_v37_r27 = static_cast(_metile_v36_r27);\n float _metile_v37_r28 = static_cast(_metile_v36_r28);\n float _metile_v37_r29 = static_cast(_metile_v36_r29);\n float _metile_v37_r30 = static_cast(_metile_v36_r30);\n float _metile_v37_r31 = static_cast(_metile_v36_r31);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v38_r16 = _metile_v21_r16 * v29;\n float _metile_v38_r17 = _metile_v21_r17 * v29;\n float _metile_v38_r18 = _metile_v21_r18 * v29;\n float _metile_v38_r19 = _metile_v21_r19 * v29;\n float _metile_v38_r20 = _metile_v21_r20 * v29;\n float _metile_v38_r21 = _metile_v21_r21 * v29;\n float _metile_v38_r22 = _metile_v21_r22 * v29;\n float _metile_v38_r23 = _metile_v21_r23 * v29;\n float _metile_v38_r24 = _metile_v21_r24 * v29;\n float _metile_v38_r25 = _metile_v21_r25 * v29;\n float _metile_v38_r26 = _metile_v21_r26 * v29;\n float _metile_v38_r27 = _metile_v21_r27 * v29;\n float _metile_v38_r28 = _metile_v21_r28 * v29;\n float _metile_v38_r29 = _metile_v21_r29 * v29;\n float _metile_v38_r30 = _metile_v21_r30 * v29;\n float _metile_v38_r31 = _metile_v21_r31 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n float _metile_v39_r16 = _metile_v38_r16 * _metile_v37_r16;\n float _metile_v39_r17 = _metile_v38_r17 * _metile_v37_r17;\n float _metile_v39_r18 = _metile_v38_r18 * _metile_v37_r18;\n float _metile_v39_r19 = _metile_v38_r19 * _metile_v37_r19;\n float _metile_v39_r20 = _metile_v38_r20 * _metile_v37_r20;\n float _metile_v39_r21 = _metile_v38_r21 * _metile_v37_r21;\n float _metile_v39_r22 = _metile_v38_r22 * _metile_v37_r22;\n float _metile_v39_r23 = _metile_v38_r23 * _metile_v37_r23;\n float _metile_v39_r24 = _metile_v38_r24 * _metile_v37_r24;\n float _metile_v39_r25 = _metile_v38_r25 * _metile_v37_r25;\n float _metile_v39_r26 = _metile_v38_r26 * _metile_v37_r26;\n float _metile_v39_r27 = _metile_v38_r27 * _metile_v37_r27;\n float _metile_v39_r28 = _metile_v38_r28 * _metile_v37_r28;\n float _metile_v39_r29 = _metile_v38_r29 * _metile_v37_r29;\n float _metile_v39_r30 = _metile_v38_r30 * _metile_v37_r30;\n float _metile_v39_r31 = _metile_v38_r31 * _metile_v37_r31;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v41_r16 = _metile_register_index________________ >= 0;\n bool _metile_v41_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v41_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v41_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v41_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v41_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v41_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v41_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v41_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v41_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v41_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v41_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v41_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v41_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v41_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v41_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v42_r8 = _metile_register_index________ < 1024;\n bool _metile_v42_r9 = _metile_register_index_________ < 1024;\n bool _metile_v42_r10 = _metile_register_index__________ < 1024;\n bool _metile_v42_r11 = _metile_register_index___________ < 1024;\n bool _metile_v42_r12 = _metile_register_index____________ < 1024;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v42_r14 = _metile_register_index______________ < 1024;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v42_r16 = _metile_register_index________________ < 1024;\n bool _metile_v42_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v42_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v42_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v42_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v42_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v42_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v42_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v42_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v42_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v42_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v42_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v42_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v42_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v42_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v42_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n bool _metile_v43_r16 = _metile_v41_r16 & _metile_v42_r16;\n bool _metile_v43_r17 = _metile_v41_r17 & _metile_v42_r17;\n bool _metile_v43_r18 = _metile_v41_r18 & _metile_v42_r18;\n bool _metile_v43_r19 = _metile_v41_r19 & _metile_v42_r19;\n bool _metile_v43_r20 = _metile_v41_r20 & _metile_v42_r20;\n bool _metile_v43_r21 = _metile_v41_r21 & _metile_v42_r21;\n bool _metile_v43_r22 = _metile_v41_r22 & _metile_v42_r22;\n bool _metile_v43_r23 = _metile_v41_r23 & _metile_v42_r23;\n bool _metile_v43_r24 = _metile_v41_r24 & _metile_v42_r24;\n bool _metile_v43_r25 = _metile_v41_r25 & _metile_v42_r25;\n bool _metile_v43_r26 = _metile_v41_r26 & _metile_v42_r26;\n bool _metile_v43_r27 = _metile_v41_r27 & _metile_v42_r27;\n bool _metile_v43_r28 = _metile_v41_r28 & _metile_v42_r28;\n bool _metile_v43_r29 = _metile_v41_r29 & _metile_v42_r29;\n bool _metile_v43_r30 = _metile_v41_r30 & _metile_v42_r30;\n bool _metile_v43_r31 = _metile_v41_r31 & _metile_v42_r31;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n int _off__metile_v44_r16 = v9 + _metile_register_index________________;\n int _off__metile_v44_r17 = v9 + _metile_register_index_________________;\n int _off__metile_v44_r18 = v9 + _metile_register_index__________________;\n int _off__metile_v44_r19 = v9 + _metile_register_index___________________;\n int _off__metile_v44_r20 = v9 + _metile_register_index____________________;\n int _off__metile_v44_r21 = v9 + _metile_register_index_____________________;\n int _off__metile_v44_r22 = v9 + _metile_register_index______________________;\n int _off__metile_v44_r23 = v9 + _metile_register_index_______________________;\n int _off__metile_v44_r24 = v9 + _metile_register_index________________________;\n int _off__metile_v44_r25 = v9 + _metile_register_index_________________________;\n int _off__metile_v44_r26 = v9 + _metile_register_index__________________________;\n int _off__metile_v44_r27 = v9 + _metile_register_index___________________________;\n int _off__metile_v44_r28 = v9 + _metile_register_index____________________________;\n int _off__metile_v44_r29 = v9 + _metile_register_index_____________________________;\n int _off__metile_v44_r30 = v9 + _metile_register_index______________________________;\n int _off__metile_v44_r31 = v9 + _metile_register_index_______________________________;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = _metile_v39_r8; }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = _metile_v39_r9; }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = _metile_v39_r10; }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = _metile_v39_r11; }\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = _metile_v39_r12; }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = _metile_v39_r13; }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = _metile_v39_r14; }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = _metile_v39_r15; }\n if (_metile_v43_r16) { Out[_off__metile_v44_r16] = _metile_v39_r16; }\n if (_metile_v43_r17) { Out[_off__metile_v44_r17] = _metile_v39_r17; }\n if (_metile_v43_r18) { Out[_off__metile_v44_r18] = _metile_v39_r18; }\n if (_metile_v43_r19) { Out[_off__metile_v44_r19] = _metile_v39_r19; }\n if (_metile_v43_r20) { Out[_off__metile_v44_r20] = _metile_v39_r20; }\n if (_metile_v43_r21) { Out[_off__metile_v44_r21] = _metile_v39_r21; }\n if (_metile_v43_r22) { Out[_off__metile_v44_r22] = _metile_v39_r22; }\n if (_metile_v43_r23) { Out[_off__metile_v44_r23] = _metile_v39_r23; }\n if (_metile_v43_r24) { Out[_off__metile_v44_r24] = _metile_v39_r24; }\n if (_metile_v43_r25) { Out[_off__metile_v44_r25] = _metile_v39_r25; }\n if (_metile_v43_r26) { Out[_off__metile_v44_r26] = _metile_v39_r26; }\n if (_metile_v43_r27) { Out[_off__metile_v44_r27] = _metile_v39_r27; }\n if (_metile_v43_r28) { Out[_off__metile_v44_r28] = _metile_v39_r28; }\n if (_metile_v43_r29) { Out[_off__metile_v44_r29] = _metile_v39_r29; }\n if (_metile_v43_r30) { Out[_off__metile_v44_r30] = _metile_v39_r30; }\n if (_metile_v43_r31) { Out[_off__metile_v44_r31] = _metile_v39_r31; }\n}", "source_sha256": "a52a8c0239924732be4213a7549695361b8367e8f1fc6ffa94dbf8f3a8880747", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 32, 1, 1 ], "is_gemm": false, "prefer_ordered": false, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 32, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 32 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 32, "threads": 32, "scratch": null, "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 614, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.125, "control": 199.6875, "speedup": 0.9978138663335415 }, "gpu_us": { "candidate": 2.20834044739604, "control": 1.5416881069540977, "speedup": 0.6981206673871214 } } }, { "frozen_register4": { "pairs": 595, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.334, "control": 200.583, "speedup": 1.0012429243163916 }, "gpu_us": { "candidate": 2.20834044739604, "control": 1.583306584507227, "speedup": 0.716966709718232 } } }, { "frozen_register4": { "pairs": 610, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.91649999999998, "control": 199.16649999999998, "speedup": 0.9962484337210785 }, "gpu_us": { "candidate": 2.20834044739604, "control": 1.5416881069540977, "speedup": 0.6981206673871214 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9984328974318637, "round_speedups": [ 0.9978138663335415, 1.0012429243163916, 0.9962484337210785 ], "candidate": 200.12509408448625, "control": 199.81147753559796 }, "gpu_us": { "speedup": 0.704346985836842, "round_speedups": [ 0.6981206673871214, 0.716966709718232, 0.6981206673871214 ], "candidate": 2.20834044739604, "control": 1.5554379378249839 } } } }, { "name": "float16_1x1024", "dtype": "float16", "batches": 1, "width": 1024, "status": "measured", "variant": { "name": "register32_blocked4", "elements_per_thread": 32, "layout": "blocked4" }, "input_sha256": "3cc059cb43f2d2ee6f0120b1b81a1fb6efa6af199ab539eb734dc561564c6ebe", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 31;\n int _metile_register_index = int((((_metile_bounded_thread >> 5) & 1u) << 0) | (((_metile_bounded_thread >> 6) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 7) & 1u) << 7) | (((_metile_bounded_thread >> 8) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 32;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 5) & 1u) << 0) | (((_metile_register_packed_ >> 6) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 7) & 1u) << 7) | (((_metile_register_packed_ >> 8) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 64;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 5) & 1u) << 0) | (((_metile_register_packed__ >> 6) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 7) & 1u) << 7) | (((_metile_register_packed__ >> 8) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 96;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 5) & 1u) << 0) | (((_metile_register_packed___ >> 6) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 7) & 1u) << 7) | (((_metile_register_packed___ >> 8) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 128;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 5) & 1u) << 0) | (((_metile_register_packed____ >> 6) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 7) & 1u) << 7) | (((_metile_register_packed____ >> 8) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 160;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 5) & 1u) << 0) | (((_metile_register_packed_____ >> 6) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 7) & 1u) << 7) | (((_metile_register_packed_____ >> 8) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 192;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 5) & 1u) << 0) | (((_metile_register_packed______ >> 6) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 7) & 1u) << 7) | (((_metile_register_packed______ >> 8) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 224;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 5) & 1u) << 0) | (((_metile_register_packed_______ >> 6) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 7) & 1u) << 7) | (((_metile_register_packed_______ >> 8) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n int _metile_register_packed________ = _metile_bounded_thread + 256;\n int _metile_register_index________ = int((((_metile_register_packed________ >> 5) & 1u) << 0) | (((_metile_register_packed________ >> 6) & 1u) << 1) | (((_metile_register_packed________ >> 0) & 1u) << 2) | (((_metile_register_packed________ >> 1) & 1u) << 3) | (((_metile_register_packed________ >> 2) & 1u) << 4) | (((_metile_register_packed________ >> 3) & 1u) << 5) | (((_metile_register_packed________ >> 4) & 1u) << 6) | (((_metile_register_packed________ >> 7) & 1u) << 7) | (((_metile_register_packed________ >> 8) & 1u) << 8) | (((_metile_register_packed________ >> 9) & 1u) << 9));\n int _metile_register_packed_________ = _metile_bounded_thread + 288;\n int _metile_register_index_________ = int((((_metile_register_packed_________ >> 5) & 1u) << 0) | (((_metile_register_packed_________ >> 6) & 1u) << 1) | (((_metile_register_packed_________ >> 0) & 1u) << 2) | (((_metile_register_packed_________ >> 1) & 1u) << 3) | (((_metile_register_packed_________ >> 2) & 1u) << 4) | (((_metile_register_packed_________ >> 3) & 1u) << 5) | (((_metile_register_packed_________ >> 4) & 1u) << 6) | (((_metile_register_packed_________ >> 7) & 1u) << 7) | (((_metile_register_packed_________ >> 8) & 1u) << 8) | (((_metile_register_packed_________ >> 9) & 1u) << 9));\n int _metile_register_packed__________ = _metile_bounded_thread + 320;\n int _metile_register_index__________ = int((((_metile_register_packed__________ >> 5) & 1u) << 0) | (((_metile_register_packed__________ >> 6) & 1u) << 1) | (((_metile_register_packed__________ >> 0) & 1u) << 2) | (((_metile_register_packed__________ >> 1) & 1u) << 3) | (((_metile_register_packed__________ >> 2) & 1u) << 4) | (((_metile_register_packed__________ >> 3) & 1u) << 5) | (((_metile_register_packed__________ >> 4) & 1u) << 6) | (((_metile_register_packed__________ >> 7) & 1u) << 7) | (((_metile_register_packed__________ >> 8) & 1u) << 8) | (((_metile_register_packed__________ >> 9) & 1u) << 9));\n int _metile_register_packed___________ = _metile_bounded_thread + 352;\n int _metile_register_index___________ = int((((_metile_register_packed___________ >> 5) & 1u) << 0) | (((_metile_register_packed___________ >> 6) & 1u) << 1) | (((_metile_register_packed___________ >> 0) & 1u) << 2) | (((_metile_register_packed___________ >> 1) & 1u) << 3) | (((_metile_register_packed___________ >> 2) & 1u) << 4) | (((_metile_register_packed___________ >> 3) & 1u) << 5) | (((_metile_register_packed___________ >> 4) & 1u) << 6) | (((_metile_register_packed___________ >> 7) & 1u) << 7) | (((_metile_register_packed___________ >> 8) & 1u) << 8) | (((_metile_register_packed___________ >> 9) & 1u) << 9));\n int _metile_register_packed____________ = _metile_bounded_thread + 384;\n int _metile_register_index____________ = int((((_metile_register_packed____________ >> 5) & 1u) << 0) | (((_metile_register_packed____________ >> 6) & 1u) << 1) | (((_metile_register_packed____________ >> 0) & 1u) << 2) | (((_metile_register_packed____________ >> 1) & 1u) << 3) | (((_metile_register_packed____________ >> 2) & 1u) << 4) | (((_metile_register_packed____________ >> 3) & 1u) << 5) | (((_metile_register_packed____________ >> 4) & 1u) << 6) | (((_metile_register_packed____________ >> 7) & 1u) << 7) | (((_metile_register_packed____________ >> 8) & 1u) << 8) | (((_metile_register_packed____________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________ = _metile_bounded_thread + 416;\n int _metile_register_index_____________ = int((((_metile_register_packed_____________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________ >> 9) & 1u) << 9));\n int _metile_register_packed______________ = _metile_bounded_thread + 448;\n int _metile_register_index______________ = int((((_metile_register_packed______________ >> 5) & 1u) << 0) | (((_metile_register_packed______________ >> 6) & 1u) << 1) | (((_metile_register_packed______________ >> 0) & 1u) << 2) | (((_metile_register_packed______________ >> 1) & 1u) << 3) | (((_metile_register_packed______________ >> 2) & 1u) << 4) | (((_metile_register_packed______________ >> 3) & 1u) << 5) | (((_metile_register_packed______________ >> 4) & 1u) << 6) | (((_metile_register_packed______________ >> 7) & 1u) << 7) | (((_metile_register_packed______________ >> 8) & 1u) << 8) | (((_metile_register_packed______________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________ = _metile_bounded_thread + 480;\n int _metile_register_index_______________ = int((((_metile_register_packed_______________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________ >> 9) & 1u) << 9));\n int _metile_register_packed________________ = _metile_bounded_thread + 512;\n int _metile_register_index________________ = int((((_metile_register_packed________________ >> 5) & 1u) << 0) | (((_metile_register_packed________________ >> 6) & 1u) << 1) | (((_metile_register_packed________________ >> 0) & 1u) << 2) | (((_metile_register_packed________________ >> 1) & 1u) << 3) | (((_metile_register_packed________________ >> 2) & 1u) << 4) | (((_metile_register_packed________________ >> 3) & 1u) << 5) | (((_metile_register_packed________________ >> 4) & 1u) << 6) | (((_metile_register_packed________________ >> 7) & 1u) << 7) | (((_metile_register_packed________________ >> 8) & 1u) << 8) | (((_metile_register_packed________________ >> 9) & 1u) << 9));\n int _metile_register_packed_________________ = _metile_bounded_thread + 544;\n int _metile_register_index_________________ = int((((_metile_register_packed_________________ >> 5) & 1u) << 0) | (((_metile_register_packed_________________ >> 6) & 1u) << 1) | (((_metile_register_packed_________________ >> 0) & 1u) << 2) | (((_metile_register_packed_________________ >> 1) & 1u) << 3) | (((_metile_register_packed_________________ >> 2) & 1u) << 4) | (((_metile_register_packed_________________ >> 3) & 1u) << 5) | (((_metile_register_packed_________________ >> 4) & 1u) << 6) | (((_metile_register_packed_________________ >> 7) & 1u) << 7) | (((_metile_register_packed_________________ >> 8) & 1u) << 8) | (((_metile_register_packed_________________ >> 9) & 1u) << 9));\n int _metile_register_packed__________________ = _metile_bounded_thread + 576;\n int _metile_register_index__________________ = int((((_metile_register_packed__________________ >> 5) & 1u) << 0) | (((_metile_register_packed__________________ >> 6) & 1u) << 1) | (((_metile_register_packed__________________ >> 0) & 1u) << 2) | (((_metile_register_packed__________________ >> 1) & 1u) << 3) | (((_metile_register_packed__________________ >> 2) & 1u) << 4) | (((_metile_register_packed__________________ >> 3) & 1u) << 5) | (((_metile_register_packed__________________ >> 4) & 1u) << 6) | (((_metile_register_packed__________________ >> 7) & 1u) << 7) | (((_metile_register_packed__________________ >> 8) & 1u) << 8) | (((_metile_register_packed__________________ >> 9) & 1u) << 9));\n int _metile_register_packed___________________ = _metile_bounded_thread + 608;\n int _metile_register_index___________________ = int((((_metile_register_packed___________________ >> 5) & 1u) << 0) | (((_metile_register_packed___________________ >> 6) & 1u) << 1) | (((_metile_register_packed___________________ >> 0) & 1u) << 2) | (((_metile_register_packed___________________ >> 1) & 1u) << 3) | (((_metile_register_packed___________________ >> 2) & 1u) << 4) | (((_metile_register_packed___________________ >> 3) & 1u) << 5) | (((_metile_register_packed___________________ >> 4) & 1u) << 6) | (((_metile_register_packed___________________ >> 7) & 1u) << 7) | (((_metile_register_packed___________________ >> 8) & 1u) << 8) | (((_metile_register_packed___________________ >> 9) & 1u) << 9));\n int _metile_register_packed____________________ = _metile_bounded_thread + 640;\n int _metile_register_index____________________ = int((((_metile_register_packed____________________ >> 5) & 1u) << 0) | (((_metile_register_packed____________________ >> 6) & 1u) << 1) | (((_metile_register_packed____________________ >> 0) & 1u) << 2) | (((_metile_register_packed____________________ >> 1) & 1u) << 3) | (((_metile_register_packed____________________ >> 2) & 1u) << 4) | (((_metile_register_packed____________________ >> 3) & 1u) << 5) | (((_metile_register_packed____________________ >> 4) & 1u) << 6) | (((_metile_register_packed____________________ >> 7) & 1u) << 7) | (((_metile_register_packed____________________ >> 8) & 1u) << 8) | (((_metile_register_packed____________________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________________ = _metile_bounded_thread + 672;\n int _metile_register_index_____________________ = int((((_metile_register_packed_____________________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________________ >> 9) & 1u) << 9));\n int _metile_register_packed______________________ = _metile_bounded_thread + 704;\n int _metile_register_index______________________ = int((((_metile_register_packed______________________ >> 5) & 1u) << 0) | (((_metile_register_packed______________________ >> 6) & 1u) << 1) | (((_metile_register_packed______________________ >> 0) & 1u) << 2) | (((_metile_register_packed______________________ >> 1) & 1u) << 3) | (((_metile_register_packed______________________ >> 2) & 1u) << 4) | (((_metile_register_packed______________________ >> 3) & 1u) << 5) | (((_metile_register_packed______________________ >> 4) & 1u) << 6) | (((_metile_register_packed______________________ >> 7) & 1u) << 7) | (((_metile_register_packed______________________ >> 8) & 1u) << 8) | (((_metile_register_packed______________________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________________ = _metile_bounded_thread + 736;\n int _metile_register_index_______________________ = int((((_metile_register_packed_______________________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________________ >> 9) & 1u) << 9));\n int _metile_register_packed________________________ = _metile_bounded_thread + 768;\n int _metile_register_index________________________ = int((((_metile_register_packed________________________ >> 5) & 1u) << 0) | (((_metile_register_packed________________________ >> 6) & 1u) << 1) | (((_metile_register_packed________________________ >> 0) & 1u) << 2) | (((_metile_register_packed________________________ >> 1) & 1u) << 3) | (((_metile_register_packed________________________ >> 2) & 1u) << 4) | (((_metile_register_packed________________________ >> 3) & 1u) << 5) | (((_metile_register_packed________________________ >> 4) & 1u) << 6) | (((_metile_register_packed________________________ >> 7) & 1u) << 7) | (((_metile_register_packed________________________ >> 8) & 1u) << 8) | (((_metile_register_packed________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_________________________ = _metile_bounded_thread + 800;\n int _metile_register_index_________________________ = int((((_metile_register_packed_________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_________________________ >> 9) & 1u) << 9));\n int _metile_register_packed__________________________ = _metile_bounded_thread + 832;\n int _metile_register_index__________________________ = int((((_metile_register_packed__________________________ >> 5) & 1u) << 0) | (((_metile_register_packed__________________________ >> 6) & 1u) << 1) | (((_metile_register_packed__________________________ >> 0) & 1u) << 2) | (((_metile_register_packed__________________________ >> 1) & 1u) << 3) | (((_metile_register_packed__________________________ >> 2) & 1u) << 4) | (((_metile_register_packed__________________________ >> 3) & 1u) << 5) | (((_metile_register_packed__________________________ >> 4) & 1u) << 6) | (((_metile_register_packed__________________________ >> 7) & 1u) << 7) | (((_metile_register_packed__________________________ >> 8) & 1u) << 8) | (((_metile_register_packed__________________________ >> 9) & 1u) << 9));\n int _metile_register_packed___________________________ = _metile_bounded_thread + 864;\n int _metile_register_index___________________________ = int((((_metile_register_packed___________________________ >> 5) & 1u) << 0) | (((_metile_register_packed___________________________ >> 6) & 1u) << 1) | (((_metile_register_packed___________________________ >> 0) & 1u) << 2) | (((_metile_register_packed___________________________ >> 1) & 1u) << 3) | (((_metile_register_packed___________________________ >> 2) & 1u) << 4) | (((_metile_register_packed___________________________ >> 3) & 1u) << 5) | (((_metile_register_packed___________________________ >> 4) & 1u) << 6) | (((_metile_register_packed___________________________ >> 7) & 1u) << 7) | (((_metile_register_packed___________________________ >> 8) & 1u) << 8) | (((_metile_register_packed___________________________ >> 9) & 1u) << 9));\n int _metile_register_packed____________________________ = _metile_bounded_thread + 896;\n int _metile_register_index____________________________ = int((((_metile_register_packed____________________________ >> 5) & 1u) << 0) | (((_metile_register_packed____________________________ >> 6) & 1u) << 1) | (((_metile_register_packed____________________________ >> 0) & 1u) << 2) | (((_metile_register_packed____________________________ >> 1) & 1u) << 3) | (((_metile_register_packed____________________________ >> 2) & 1u) << 4) | (((_metile_register_packed____________________________ >> 3) & 1u) << 5) | (((_metile_register_packed____________________________ >> 4) & 1u) << 6) | (((_metile_register_packed____________________________ >> 7) & 1u) << 7) | (((_metile_register_packed____________________________ >> 8) & 1u) << 8) | (((_metile_register_packed____________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________________________ = _metile_bounded_thread + 928;\n int _metile_register_index_____________________________ = int((((_metile_register_packed_____________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________________________ >> 9) & 1u) << 9));\n int _metile_register_packed______________________________ = _metile_bounded_thread + 960;\n int _metile_register_index______________________________ = int((((_metile_register_packed______________________________ >> 5) & 1u) << 0) | (((_metile_register_packed______________________________ >> 6) & 1u) << 1) | (((_metile_register_packed______________________________ >> 0) & 1u) << 2) | (((_metile_register_packed______________________________ >> 1) & 1u) << 3) | (((_metile_register_packed______________________________ >> 2) & 1u) << 4) | (((_metile_register_packed______________________________ >> 3) & 1u) << 5) | (((_metile_register_packed______________________________ >> 4) & 1u) << 6) | (((_metile_register_packed______________________________ >> 7) & 1u) << 7) | (((_metile_register_packed______________________________ >> 8) & 1u) << 8) | (((_metile_register_packed______________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________________________ = _metile_bounded_thread + 992;\n int _metile_register_index_______________________________ = int((((_metile_register_packed_______________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________________________ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v16_r16 = _metile_register_index________________ >= 0;\n bool _metile_v16_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v16_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v16_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v16_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v16_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v16_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v16_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v16_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v16_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v16_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v16_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v16_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v16_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v16_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v16_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v17_r8 = _metile_register_index________ < 1024;\n bool _metile_v17_r9 = _metile_register_index_________ < 1024;\n bool _metile_v17_r10 = _metile_register_index__________ < 1024;\n bool _metile_v17_r11 = _metile_register_index___________ < 1024;\n bool _metile_v17_r12 = _metile_register_index____________ < 1024;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v17_r14 = _metile_register_index______________ < 1024;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v17_r16 = _metile_register_index________________ < 1024;\n bool _metile_v17_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v17_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v17_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v17_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v17_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v17_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v17_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v17_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v17_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v17_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v17_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v17_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v17_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v17_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v17_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n bool _metile_v18_r16 = _metile_v16_r16 & _metile_v17_r16;\n bool _metile_v18_r17 = _metile_v16_r17 & _metile_v17_r17;\n bool _metile_v18_r18 = _metile_v16_r18 & _metile_v17_r18;\n bool _metile_v18_r19 = _metile_v16_r19 & _metile_v17_r19;\n bool _metile_v18_r20 = _metile_v16_r20 & _metile_v17_r20;\n bool _metile_v18_r21 = _metile_v16_r21 & _metile_v17_r21;\n bool _metile_v18_r22 = _metile_v16_r22 & _metile_v17_r22;\n bool _metile_v18_r23 = _metile_v16_r23 & _metile_v17_r23;\n bool _metile_v18_r24 = _metile_v16_r24 & _metile_v17_r24;\n bool _metile_v18_r25 = _metile_v16_r25 & _metile_v17_r25;\n bool _metile_v18_r26 = _metile_v16_r26 & _metile_v17_r26;\n bool _metile_v18_r27 = _metile_v16_r27 & _metile_v17_r27;\n bool _metile_v18_r28 = _metile_v16_r28 & _metile_v17_r28;\n bool _metile_v18_r29 = _metile_v16_r29 & _metile_v17_r29;\n bool _metile_v18_r30 = _metile_v16_r30 & _metile_v17_r30;\n bool _metile_v18_r31 = _metile_v16_r31 & _metile_v17_r31;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n int _off__metile_v19_r16 = v2 + _metile_register_index________________;\n int _off__metile_v19_r17 = v2 + _metile_register_index_________________;\n int _off__metile_v19_r18 = v2 + _metile_register_index__________________;\n int _off__metile_v19_r19 = v2 + _metile_register_index___________________;\n int _off__metile_v19_r20 = v2 + _metile_register_index____________________;\n int _off__metile_v19_r21 = v2 + _metile_register_index_____________________;\n int _off__metile_v19_r22 = v2 + _metile_register_index______________________;\n int _off__metile_v19_r23 = v2 + _metile_register_index_______________________;\n int _off__metile_v19_r24 = v2 + _metile_register_index________________________;\n int _off__metile_v19_r25 = v2 + _metile_register_index_________________________;\n int _off__metile_v19_r26 = v2 + _metile_register_index__________________________;\n int _off__metile_v19_r27 = v2 + _metile_register_index___________________________;\n int _off__metile_v19_r28 = v2 + _metile_register_index____________________________;\n int _off__metile_v19_r29 = v2 + _metile_register_index_____________________________;\n int _off__metile_v19_r30 = v2 + _metile_register_index______________________________;\n int _off__metile_v19_r31 = v2 + _metile_register_index_______________________________;\n half4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = half4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n half _metile_v20_r0 = _metile_vector_load[0];\n half _metile_v20_r1 = _metile_vector_load[1];\n half _metile_v20_r2 = _metile_vector_load[2];\n half _metile_v20_r3 = _metile_vector_load[3];\n half4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = half4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n half _metile_v20_r4 = _metile_vector_load_[0];\n half _metile_v20_r5 = _metile_vector_load_[1];\n half _metile_v20_r6 = _metile_vector_load_[2];\n half _metile_v20_r7 = _metile_vector_load_[3];\n half4 _metile_vector_load__;\n if ((_metile_v18_r8) && (_metile_v18_r9) && (_metile_v18_r10) && (_metile_v18_r11) && (long(_off__metile_v19_r9) == long(_off__metile_v19_r8) + 1) && (long(_off__metile_v19_r10) == long(_off__metile_v19_r8) + 2) && (long(_off__metile_v19_r11) == long(_off__metile_v19_r8) + 3)) {\n _metile_vector_load__ = half4(*reinterpret_cast(X + _off__metile_v19_r8));\n } else {\n _metile_vector_load__[0] = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n _metile_vector_load__[1] = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n _metile_vector_load__[2] = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n _metile_vector_load__[3] = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n }\n half _metile_v20_r8 = _metile_vector_load__[0];\n half _metile_v20_r9 = _metile_vector_load__[1];\n half _metile_v20_r10 = _metile_vector_load__[2];\n half _metile_v20_r11 = _metile_vector_load__[3];\n half4 _metile_vector_load___;\n if ((_metile_v18_r12) && (_metile_v18_r13) && (_metile_v18_r14) && (_metile_v18_r15) && (long(_off__metile_v19_r13) == long(_off__metile_v19_r12) + 1) && (long(_off__metile_v19_r14) == long(_off__metile_v19_r12) + 2) && (long(_off__metile_v19_r15) == long(_off__metile_v19_r12) + 3)) {\n _metile_vector_load___ = half4(*reinterpret_cast(X + _off__metile_v19_r12));\n } else {\n _metile_vector_load___[0] = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n _metile_vector_load___[1] = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n _metile_vector_load___[2] = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n _metile_vector_load___[3] = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n }\n half _metile_v20_r12 = _metile_vector_load___[0];\n half _metile_v20_r13 = _metile_vector_load___[1];\n half _metile_v20_r14 = _metile_vector_load___[2];\n half _metile_v20_r15 = _metile_vector_load___[3];\n half4 _metile_vector_load____;\n if ((_metile_v18_r16) && (_metile_v18_r17) && (_metile_v18_r18) && (_metile_v18_r19) && (long(_off__metile_v19_r17) == long(_off__metile_v19_r16) + 1) && (long(_off__metile_v19_r18) == long(_off__metile_v19_r16) + 2) && (long(_off__metile_v19_r19) == long(_off__metile_v19_r16) + 3)) {\n _metile_vector_load____ = half4(*reinterpret_cast(X + _off__metile_v19_r16));\n } else {\n _metile_vector_load____[0] = _metile_v18_r16 ? X[_off__metile_v19_r16] : static_cast(0);\n _metile_vector_load____[1] = _metile_v18_r17 ? X[_off__metile_v19_r17] : static_cast(0);\n _metile_vector_load____[2] = _metile_v18_r18 ? X[_off__metile_v19_r18] : static_cast(0);\n _metile_vector_load____[3] = _metile_v18_r19 ? X[_off__metile_v19_r19] : static_cast(0);\n }\n half _metile_v20_r16 = _metile_vector_load____[0];\n half _metile_v20_r17 = _metile_vector_load____[1];\n half _metile_v20_r18 = _metile_vector_load____[2];\n half _metile_v20_r19 = _metile_vector_load____[3];\n half4 _metile_vector_load_____;\n if ((_metile_v18_r20) && (_metile_v18_r21) && (_metile_v18_r22) && (_metile_v18_r23) && (long(_off__metile_v19_r21) == long(_off__metile_v19_r20) + 1) && (long(_off__metile_v19_r22) == long(_off__metile_v19_r20) + 2) && (long(_off__metile_v19_r23) == long(_off__metile_v19_r20) + 3)) {\n _metile_vector_load_____ = half4(*reinterpret_cast(X + _off__metile_v19_r20));\n } else {\n _metile_vector_load_____[0] = _metile_v18_r20 ? X[_off__metile_v19_r20] : static_cast(0);\n _metile_vector_load_____[1] = _metile_v18_r21 ? X[_off__metile_v19_r21] : static_cast(0);\n _metile_vector_load_____[2] = _metile_v18_r22 ? X[_off__metile_v19_r22] : static_cast(0);\n _metile_vector_load_____[3] = _metile_v18_r23 ? X[_off__metile_v19_r23] : static_cast(0);\n }\n half _metile_v20_r20 = _metile_vector_load_____[0];\n half _metile_v20_r21 = _metile_vector_load_____[1];\n half _metile_v20_r22 = _metile_vector_load_____[2];\n half _metile_v20_r23 = _metile_vector_load_____[3];\n half4 _metile_vector_load______;\n if ((_metile_v18_r24) && (_metile_v18_r25) && (_metile_v18_r26) && (_metile_v18_r27) && (long(_off__metile_v19_r25) == long(_off__metile_v19_r24) + 1) && (long(_off__metile_v19_r26) == long(_off__metile_v19_r24) + 2) && (long(_off__metile_v19_r27) == long(_off__metile_v19_r24) + 3)) {\n _metile_vector_load______ = half4(*reinterpret_cast(X + _off__metile_v19_r24));\n } else {\n _metile_vector_load______[0] = _metile_v18_r24 ? X[_off__metile_v19_r24] : static_cast(0);\n _metile_vector_load______[1] = _metile_v18_r25 ? X[_off__metile_v19_r25] : static_cast(0);\n _metile_vector_load______[2] = _metile_v18_r26 ? X[_off__metile_v19_r26] : static_cast(0);\n _metile_vector_load______[3] = _metile_v18_r27 ? X[_off__metile_v19_r27] : static_cast(0);\n }\n half _metile_v20_r24 = _metile_vector_load______[0];\n half _metile_v20_r25 = _metile_vector_load______[1];\n half _metile_v20_r26 = _metile_vector_load______[2];\n half _metile_v20_r27 = _metile_vector_load______[3];\n half4 _metile_vector_load_______;\n if ((_metile_v18_r28) && (_metile_v18_r29) && (_metile_v18_r30) && (_metile_v18_r31) && (long(_off__metile_v19_r29) == long(_off__metile_v19_r28) + 1) && (long(_off__metile_v19_r30) == long(_off__metile_v19_r28) + 2) && (long(_off__metile_v19_r31) == long(_off__metile_v19_r28) + 3)) {\n _metile_vector_load_______ = half4(*reinterpret_cast(X + _off__metile_v19_r28));\n } else {\n _metile_vector_load_______[0] = _metile_v18_r28 ? X[_off__metile_v19_r28] : static_cast(0);\n _metile_vector_load_______[1] = _metile_v18_r29 ? X[_off__metile_v19_r29] : static_cast(0);\n _metile_vector_load_______[2] = _metile_v18_r30 ? X[_off__metile_v19_r30] : static_cast(0);\n _metile_vector_load_______[3] = _metile_v18_r31 ? X[_off__metile_v19_r31] : static_cast(0);\n }\n half _metile_v20_r28 = _metile_vector_load_______[0];\n half _metile_v20_r29 = _metile_vector_load_______[1];\n half _metile_v20_r30 = _metile_vector_load_______[2];\n half _metile_v20_r31 = _metile_vector_load_______[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v21_r16 = static_cast(_metile_v20_r16);\n float _metile_v21_r17 = static_cast(_metile_v20_r17);\n float _metile_v21_r18 = static_cast(_metile_v20_r18);\n float _metile_v21_r19 = static_cast(_metile_v20_r19);\n float _metile_v21_r20 = static_cast(_metile_v20_r20);\n float _metile_v21_r21 = static_cast(_metile_v20_r21);\n float _metile_v21_r22 = static_cast(_metile_v20_r22);\n float _metile_v21_r23 = static_cast(_metile_v20_r23);\n float _metile_v21_r24 = static_cast(_metile_v20_r24);\n float _metile_v21_r25 = static_cast(_metile_v20_r25);\n float _metile_v21_r26 = static_cast(_metile_v20_r26);\n float _metile_v21_r27 = static_cast(_metile_v20_r27);\n float _metile_v21_r28 = static_cast(_metile_v20_r28);\n float _metile_v21_r29 = static_cast(_metile_v20_r29);\n float _metile_v21_r30 = static_cast(_metile_v20_r30);\n float _metile_v21_r31 = static_cast(_metile_v20_r31);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_v22_r16 = _metile_v21_r16 * _metile_v21_r16;\n float _metile_v22_r17 = _metile_v21_r17 * _metile_v21_r17;\n float _metile_v22_r18 = _metile_v21_r18 * _metile_v21_r18;\n float _metile_v22_r19 = _metile_v21_r19 * _metile_v21_r19;\n float _metile_v22_r20 = _metile_v21_r20 * _metile_v21_r20;\n float _metile_v22_r21 = _metile_v21_r21 * _metile_v21_r21;\n float _metile_v22_r22 = _metile_v21_r22 * _metile_v21_r22;\n float _metile_v22_r23 = _metile_v21_r23 * _metile_v21_r23;\n float _metile_v22_r24 = _metile_v21_r24 * _metile_v21_r24;\n float _metile_v22_r25 = _metile_v21_r25 * _metile_v21_r25;\n float _metile_v22_r26 = _metile_v21_r26 * _metile_v21_r26;\n float _metile_v22_r27 = _metile_v21_r27 * _metile_v21_r27;\n float _metile_v22_r28 = _metile_v21_r28 * _metile_v21_r28;\n float _metile_v22_r29 = _metile_v21_r29 * _metile_v21_r29;\n float _metile_v22_r30 = _metile_v21_r30 * _metile_v21_r30;\n float _metile_v22_r31 = _metile_v21_r31 * _metile_v21_r31;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_v22_r16 + _metile_v22_r17;\n float _metile_register_sum_________ = _metile_v22_r18 + _metile_v22_r19;\n float _metile_register_sum__________ = _metile_v22_r20 + _metile_v22_r21;\n float _metile_register_sum___________ = _metile_v22_r22 + _metile_v22_r23;\n float _metile_register_sum____________ = _metile_v22_r24 + _metile_v22_r25;\n float _metile_register_sum_____________ = _metile_v22_r26 + _metile_v22_r27;\n float _metile_register_sum______________ = _metile_v22_r28 + _metile_v22_r29;\n float _metile_register_sum_______________ = _metile_v22_r30 + _metile_v22_r31;\n float _metile_register_sum________________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________________ = _metile_register_sum____________ + _metile_register_sum_____________;\n float _metile_register_sum_______________________ = _metile_register_sum______________ + _metile_register_sum_______________;\n float _metile_register_sum________________________ = _metile_register_sum________________ + _metile_register_sum_________________;\n float _metile_register_sum_________________________ = _metile_register_sum__________________ + _metile_register_sum___________________;\n float _metile_register_sum__________________________ = _metile_register_sum____________________ + _metile_register_sum_____________________;\n float _metile_register_sum___________________________ = _metile_register_sum______________________ + _metile_register_sum_______________________;\n float _metile_register_sum____________________________ = _metile_register_sum________________________ + _metile_register_sum_________________________;\n float _metile_register_sum_____________________________ = _metile_register_sum__________________________ + _metile_register_sum___________________________;\n float _metile_register_sum______________________________ = _metile_register_sum____________________________ + _metile_register_sum_____________________________;\n float v23 = simd_sum(_metile_register_sum______________________________);\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v32_r16 = _metile_register_index________________ >= 0;\n bool _metile_v32_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v32_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v32_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v32_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v32_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v32_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v32_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v32_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v32_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v32_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v32_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v32_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v32_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v32_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v32_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v33_r8 = _metile_register_index________ < 1024;\n bool _metile_v33_r9 = _metile_register_index_________ < 1024;\n bool _metile_v33_r10 = _metile_register_index__________ < 1024;\n bool _metile_v33_r11 = _metile_register_index___________ < 1024;\n bool _metile_v33_r12 = _metile_register_index____________ < 1024;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v33_r14 = _metile_register_index______________ < 1024;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v33_r16 = _metile_register_index________________ < 1024;\n bool _metile_v33_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v33_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v33_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v33_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v33_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v33_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v33_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v33_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v33_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v33_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v33_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v33_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v33_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v33_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v33_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n bool _metile_v34_r16 = _metile_v32_r16 & _metile_v33_r16;\n bool _metile_v34_r17 = _metile_v32_r17 & _metile_v33_r17;\n bool _metile_v34_r18 = _metile_v32_r18 & _metile_v33_r18;\n bool _metile_v34_r19 = _metile_v32_r19 & _metile_v33_r19;\n bool _metile_v34_r20 = _metile_v32_r20 & _metile_v33_r20;\n bool _metile_v34_r21 = _metile_v32_r21 & _metile_v33_r21;\n bool _metile_v34_r22 = _metile_v32_r22 & _metile_v33_r22;\n bool _metile_v34_r23 = _metile_v32_r23 & _metile_v33_r23;\n bool _metile_v34_r24 = _metile_v32_r24 & _metile_v33_r24;\n bool _metile_v34_r25 = _metile_v32_r25 & _metile_v33_r25;\n bool _metile_v34_r26 = _metile_v32_r26 & _metile_v33_r26;\n bool _metile_v34_r27 = _metile_v32_r27 & _metile_v33_r27;\n bool _metile_v34_r28 = _metile_v32_r28 & _metile_v33_r28;\n bool _metile_v34_r29 = _metile_v32_r29 & _metile_v33_r29;\n bool _metile_v34_r30 = _metile_v32_r30 & _metile_v33_r30;\n bool _metile_v34_r31 = _metile_v32_r31 & _metile_v33_r31;\n half4 _metile_vector_load________;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load________ = half4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load________[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load________[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load________[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load________[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n half _metile_v36_r0 = _metile_vector_load________[0];\n half _metile_v36_r1 = _metile_vector_load________[1];\n half _metile_v36_r2 = _metile_vector_load________[2];\n half _metile_v36_r3 = _metile_vector_load________[3];\n half4 _metile_vector_load_________;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load_________ = half4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load_________[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load_________[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load_________[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load_________[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n half _metile_v36_r4 = _metile_vector_load_________[0];\n half _metile_v36_r5 = _metile_vector_load_________[1];\n half _metile_v36_r6 = _metile_vector_load_________[2];\n half _metile_v36_r7 = _metile_vector_load_________[3];\n half4 _metile_vector_load__________;\n if ((_metile_v34_r8) && (_metile_v34_r9) && (_metile_v34_r10) && (_metile_v34_r11) && (long(_metile_register_index_________) == long(_metile_register_index________) + 1) && (long(_metile_register_index__________) == long(_metile_register_index________) + 2) && (long(_metile_register_index___________) == long(_metile_register_index________) + 3)) {\n _metile_vector_load__________ = half4(*reinterpret_cast(W + _metile_register_index________));\n } else {\n _metile_vector_load__________[0] = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n _metile_vector_load__________[1] = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n _metile_vector_load__________[2] = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n _metile_vector_load__________[3] = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n }\n half _metile_v36_r8 = _metile_vector_load__________[0];\n half _metile_v36_r9 = _metile_vector_load__________[1];\n half _metile_v36_r10 = _metile_vector_load__________[2];\n half _metile_v36_r11 = _metile_vector_load__________[3];\n half4 _metile_vector_load___________;\n if ((_metile_v34_r12) && (_metile_v34_r13) && (_metile_v34_r14) && (_metile_v34_r15) && (long(_metile_register_index_____________) == long(_metile_register_index____________) + 1) && (long(_metile_register_index______________) == long(_metile_register_index____________) + 2) && (long(_metile_register_index_______________) == long(_metile_register_index____________) + 3)) {\n _metile_vector_load___________ = half4(*reinterpret_cast(W + _metile_register_index____________));\n } else {\n _metile_vector_load___________[0] = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n _metile_vector_load___________[1] = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n _metile_vector_load___________[2] = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n _metile_vector_load___________[3] = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n }\n half _metile_v36_r12 = _metile_vector_load___________[0];\n half _metile_v36_r13 = _metile_vector_load___________[1];\n half _metile_v36_r14 = _metile_vector_load___________[2];\n half _metile_v36_r15 = _metile_vector_load___________[3];\n half4 _metile_vector_load____________;\n if ((_metile_v34_r16) && (_metile_v34_r17) && (_metile_v34_r18) && (_metile_v34_r19) && (long(_metile_register_index_________________) == long(_metile_register_index________________) + 1) && (long(_metile_register_index__________________) == long(_metile_register_index________________) + 2) && (long(_metile_register_index___________________) == long(_metile_register_index________________) + 3)) {\n _metile_vector_load____________ = half4(*reinterpret_cast(W + _metile_register_index________________));\n } else {\n _metile_vector_load____________[0] = _metile_v34_r16 ? W[_metile_register_index________________] : static_cast(0);\n _metile_vector_load____________[1] = _metile_v34_r17 ? W[_metile_register_index_________________] : static_cast(0);\n _metile_vector_load____________[2] = _metile_v34_r18 ? W[_metile_register_index__________________] : static_cast(0);\n _metile_vector_load____________[3] = _metile_v34_r19 ? W[_metile_register_index___________________] : static_cast(0);\n }\n half _metile_v36_r16 = _metile_vector_load____________[0];\n half _metile_v36_r17 = _metile_vector_load____________[1];\n half _metile_v36_r18 = _metile_vector_load____________[2];\n half _metile_v36_r19 = _metile_vector_load____________[3];\n half4 _metile_vector_load_____________;\n if ((_metile_v34_r20) && (_metile_v34_r21) && (_metile_v34_r22) && (_metile_v34_r23) && (long(_metile_register_index_____________________) == long(_metile_register_index____________________) + 1) && (long(_metile_register_index______________________) == long(_metile_register_index____________________) + 2) && (long(_metile_register_index_______________________) == long(_metile_register_index____________________) + 3)) {\n _metile_vector_load_____________ = half4(*reinterpret_cast(W + _metile_register_index____________________));\n } else {\n _metile_vector_load_____________[0] = _metile_v34_r20 ? W[_metile_register_index____________________] : static_cast(0);\n _metile_vector_load_____________[1] = _metile_v34_r21 ? W[_metile_register_index_____________________] : static_cast(0);\n _metile_vector_load_____________[2] = _metile_v34_r22 ? W[_metile_register_index______________________] : static_cast(0);\n _metile_vector_load_____________[3] = _metile_v34_r23 ? W[_metile_register_index_______________________] : static_cast(0);\n }\n half _metile_v36_r20 = _metile_vector_load_____________[0];\n half _metile_v36_r21 = _metile_vector_load_____________[1];\n half _metile_v36_r22 = _metile_vector_load_____________[2];\n half _metile_v36_r23 = _metile_vector_load_____________[3];\n half4 _metile_vector_load______________;\n if ((_metile_v34_r24) && (_metile_v34_r25) && (_metile_v34_r26) && (_metile_v34_r27) && (long(_metile_register_index_________________________) == long(_metile_register_index________________________) + 1) && (long(_metile_register_index__________________________) == long(_metile_register_index________________________) + 2) && (long(_metile_register_index___________________________) == long(_metile_register_index________________________) + 3)) {\n _metile_vector_load______________ = half4(*reinterpret_cast(W + _metile_register_index________________________));\n } else {\n _metile_vector_load______________[0] = _metile_v34_r24 ? W[_metile_register_index________________________] : static_cast(0);\n _metile_vector_load______________[1] = _metile_v34_r25 ? W[_metile_register_index_________________________] : static_cast(0);\n _metile_vector_load______________[2] = _metile_v34_r26 ? W[_metile_register_index__________________________] : static_cast(0);\n _metile_vector_load______________[3] = _metile_v34_r27 ? W[_metile_register_index___________________________] : static_cast(0);\n }\n half _metile_v36_r24 = _metile_vector_load______________[0];\n half _metile_v36_r25 = _metile_vector_load______________[1];\n half _metile_v36_r26 = _metile_vector_load______________[2];\n half _metile_v36_r27 = _metile_vector_load______________[3];\n half4 _metile_vector_load_______________;\n if ((_metile_v34_r28) && (_metile_v34_r29) && (_metile_v34_r30) && (_metile_v34_r31) && (long(_metile_register_index_____________________________) == long(_metile_register_index____________________________) + 1) && (long(_metile_register_index______________________________) == long(_metile_register_index____________________________) + 2) && (long(_metile_register_index_______________________________) == long(_metile_register_index____________________________) + 3)) {\n _metile_vector_load_______________ = half4(*reinterpret_cast(W + _metile_register_index____________________________));\n } else {\n _metile_vector_load_______________[0] = _metile_v34_r28 ? W[_metile_register_index____________________________] : static_cast(0);\n _metile_vector_load_______________[1] = _metile_v34_r29 ? W[_metile_register_index_____________________________] : static_cast(0);\n _metile_vector_load_______________[2] = _metile_v34_r30 ? W[_metile_register_index______________________________] : static_cast(0);\n _metile_vector_load_______________[3] = _metile_v34_r31 ? W[_metile_register_index_______________________________] : static_cast(0);\n }\n half _metile_v36_r28 = _metile_vector_load_______________[0];\n half _metile_v36_r29 = _metile_vector_load_______________[1];\n half _metile_v36_r30 = _metile_vector_load_______________[2];\n half _metile_v36_r31 = _metile_vector_load_______________[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v37_r16 = static_cast(_metile_v36_r16);\n float _metile_v37_r17 = static_cast(_metile_v36_r17);\n float _metile_v37_r18 = static_cast(_metile_v36_r18);\n float _metile_v37_r19 = static_cast(_metile_v36_r19);\n float _metile_v37_r20 = static_cast(_metile_v36_r20);\n float _metile_v37_r21 = static_cast(_metile_v36_r21);\n float _metile_v37_r22 = static_cast(_metile_v36_r22);\n float _metile_v37_r23 = static_cast(_metile_v36_r23);\n float _metile_v37_r24 = static_cast(_metile_v36_r24);\n float _metile_v37_r25 = static_cast(_metile_v36_r25);\n float _metile_v37_r26 = static_cast(_metile_v36_r26);\n float _metile_v37_r27 = static_cast(_metile_v36_r27);\n float _metile_v37_r28 = static_cast(_metile_v36_r28);\n float _metile_v37_r29 = static_cast(_metile_v36_r29);\n float _metile_v37_r30 = static_cast(_metile_v36_r30);\n float _metile_v37_r31 = static_cast(_metile_v36_r31);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v38_r16 = _metile_v21_r16 * v29;\n float _metile_v38_r17 = _metile_v21_r17 * v29;\n float _metile_v38_r18 = _metile_v21_r18 * v29;\n float _metile_v38_r19 = _metile_v21_r19 * v29;\n float _metile_v38_r20 = _metile_v21_r20 * v29;\n float _metile_v38_r21 = _metile_v21_r21 * v29;\n float _metile_v38_r22 = _metile_v21_r22 * v29;\n float _metile_v38_r23 = _metile_v21_r23 * v29;\n float _metile_v38_r24 = _metile_v21_r24 * v29;\n float _metile_v38_r25 = _metile_v21_r25 * v29;\n float _metile_v38_r26 = _metile_v21_r26 * v29;\n float _metile_v38_r27 = _metile_v21_r27 * v29;\n float _metile_v38_r28 = _metile_v21_r28 * v29;\n float _metile_v38_r29 = _metile_v21_r29 * v29;\n float _metile_v38_r30 = _metile_v21_r30 * v29;\n float _metile_v38_r31 = _metile_v21_r31 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n float _metile_v39_r16 = _metile_v38_r16 * _metile_v37_r16;\n float _metile_v39_r17 = _metile_v38_r17 * _metile_v37_r17;\n float _metile_v39_r18 = _metile_v38_r18 * _metile_v37_r18;\n float _metile_v39_r19 = _metile_v38_r19 * _metile_v37_r19;\n float _metile_v39_r20 = _metile_v38_r20 * _metile_v37_r20;\n float _metile_v39_r21 = _metile_v38_r21 * _metile_v37_r21;\n float _metile_v39_r22 = _metile_v38_r22 * _metile_v37_r22;\n float _metile_v39_r23 = _metile_v38_r23 * _metile_v37_r23;\n float _metile_v39_r24 = _metile_v38_r24 * _metile_v37_r24;\n float _metile_v39_r25 = _metile_v38_r25 * _metile_v37_r25;\n float _metile_v39_r26 = _metile_v38_r26 * _metile_v37_r26;\n float _metile_v39_r27 = _metile_v38_r27 * _metile_v37_r27;\n float _metile_v39_r28 = _metile_v38_r28 * _metile_v37_r28;\n float _metile_v39_r29 = _metile_v38_r29 * _metile_v37_r29;\n float _metile_v39_r30 = _metile_v38_r30 * _metile_v37_r30;\n float _metile_v39_r31 = _metile_v38_r31 * _metile_v37_r31;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v41_r16 = _metile_register_index________________ >= 0;\n bool _metile_v41_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v41_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v41_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v41_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v41_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v41_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v41_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v41_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v41_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v41_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v41_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v41_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v41_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v41_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v41_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v42_r8 = _metile_register_index________ < 1024;\n bool _metile_v42_r9 = _metile_register_index_________ < 1024;\n bool _metile_v42_r10 = _metile_register_index__________ < 1024;\n bool _metile_v42_r11 = _metile_register_index___________ < 1024;\n bool _metile_v42_r12 = _metile_register_index____________ < 1024;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v42_r14 = _metile_register_index______________ < 1024;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v42_r16 = _metile_register_index________________ < 1024;\n bool _metile_v42_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v42_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v42_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v42_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v42_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v42_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v42_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v42_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v42_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v42_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v42_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v42_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v42_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v42_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v42_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n bool _metile_v43_r16 = _metile_v41_r16 & _metile_v42_r16;\n bool _metile_v43_r17 = _metile_v41_r17 & _metile_v42_r17;\n bool _metile_v43_r18 = _metile_v41_r18 & _metile_v42_r18;\n bool _metile_v43_r19 = _metile_v41_r19 & _metile_v42_r19;\n bool _metile_v43_r20 = _metile_v41_r20 & _metile_v42_r20;\n bool _metile_v43_r21 = _metile_v41_r21 & _metile_v42_r21;\n bool _metile_v43_r22 = _metile_v41_r22 & _metile_v42_r22;\n bool _metile_v43_r23 = _metile_v41_r23 & _metile_v42_r23;\n bool _metile_v43_r24 = _metile_v41_r24 & _metile_v42_r24;\n bool _metile_v43_r25 = _metile_v41_r25 & _metile_v42_r25;\n bool _metile_v43_r26 = _metile_v41_r26 & _metile_v42_r26;\n bool _metile_v43_r27 = _metile_v41_r27 & _metile_v42_r27;\n bool _metile_v43_r28 = _metile_v41_r28 & _metile_v42_r28;\n bool _metile_v43_r29 = _metile_v41_r29 & _metile_v42_r29;\n bool _metile_v43_r30 = _metile_v41_r30 & _metile_v42_r30;\n bool _metile_v43_r31 = _metile_v41_r31 & _metile_v42_r31;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n int _off__metile_v44_r16 = v9 + _metile_register_index________________;\n int _off__metile_v44_r17 = v9 + _metile_register_index_________________;\n int _off__metile_v44_r18 = v9 + _metile_register_index__________________;\n int _off__metile_v44_r19 = v9 + _metile_register_index___________________;\n int _off__metile_v44_r20 = v9 + _metile_register_index____________________;\n int _off__metile_v44_r21 = v9 + _metile_register_index_____________________;\n int _off__metile_v44_r22 = v9 + _metile_register_index______________________;\n int _off__metile_v44_r23 = v9 + _metile_register_index_______________________;\n int _off__metile_v44_r24 = v9 + _metile_register_index________________________;\n int _off__metile_v44_r25 = v9 + _metile_register_index_________________________;\n int _off__metile_v44_r26 = v9 + _metile_register_index__________________________;\n int _off__metile_v44_r27 = v9 + _metile_register_index___________________________;\n int _off__metile_v44_r28 = v9 + _metile_register_index____________________________;\n int _off__metile_v44_r29 = v9 + _metile_register_index_____________________________;\n int _off__metile_v44_r30 = v9 + _metile_register_index______________________________;\n int _off__metile_v44_r31 = v9 + _metile_register_index_______________________________;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_half4(half4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_half4(half4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n if ((_metile_v43_r8) && (_metile_v43_r9) && (_metile_v43_r10) && (_metile_v43_r11) && (long(_off__metile_v44_r9) == long(_off__metile_v44_r8) + 1) && (long(_off__metile_v44_r10) == long(_off__metile_v44_r8) + 2) && (long(_off__metile_v44_r11) == long(_off__metile_v44_r8) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r8) = packed_half4(half4(static_cast(_metile_v39_r8), static_cast(_metile_v39_r9), static_cast(_metile_v39_r10), static_cast(_metile_v39_r11)));\n } else {\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = static_cast(_metile_v39_r8); }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = static_cast(_metile_v39_r9); }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = static_cast(_metile_v39_r10); }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = static_cast(_metile_v39_r11); }\n }\n if ((_metile_v43_r12) && (_metile_v43_r13) && (_metile_v43_r14) && (_metile_v43_r15) && (long(_off__metile_v44_r13) == long(_off__metile_v44_r12) + 1) && (long(_off__metile_v44_r14) == long(_off__metile_v44_r12) + 2) && (long(_off__metile_v44_r15) == long(_off__metile_v44_r12) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r12) = packed_half4(half4(static_cast(_metile_v39_r12), static_cast(_metile_v39_r13), static_cast(_metile_v39_r14), static_cast(_metile_v39_r15)));\n } else {\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = static_cast(_metile_v39_r12); }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = static_cast(_metile_v39_r13); }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = static_cast(_metile_v39_r14); }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = static_cast(_metile_v39_r15); }\n }\n if ((_metile_v43_r16) && (_metile_v43_r17) && (_metile_v43_r18) && (_metile_v43_r19) && (long(_off__metile_v44_r17) == long(_off__metile_v44_r16) + 1) && (long(_off__metile_v44_r18) == long(_off__metile_v44_r16) + 2) && (long(_off__metile_v44_r19) == long(_off__metile_v44_r16) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r16) = packed_half4(half4(static_cast(_metile_v39_r16), static_cast(_metile_v39_r17), static_cast(_metile_v39_r18), static_cast(_metile_v39_r19)));\n } else {\n if (_metile_v43_r16) { Out[_off__metile_v44_r16] = static_cast(_metile_v39_r16); }\n if (_metile_v43_r17) { Out[_off__metile_v44_r17] = static_cast(_metile_v39_r17); }\n if (_metile_v43_r18) { Out[_off__metile_v44_r18] = static_cast(_metile_v39_r18); }\n if (_metile_v43_r19) { Out[_off__metile_v44_r19] = static_cast(_metile_v39_r19); }\n }\n if ((_metile_v43_r20) && (_metile_v43_r21) && (_metile_v43_r22) && (_metile_v43_r23) && (long(_off__metile_v44_r21) == long(_off__metile_v44_r20) + 1) && (long(_off__metile_v44_r22) == long(_off__metile_v44_r20) + 2) && (long(_off__metile_v44_r23) == long(_off__metile_v44_r20) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r20) = packed_half4(half4(static_cast(_metile_v39_r20), static_cast(_metile_v39_r21), static_cast(_metile_v39_r22), static_cast(_metile_v39_r23)));\n } else {\n if (_metile_v43_r20) { Out[_off__metile_v44_r20] = static_cast(_metile_v39_r20); }\n if (_metile_v43_r21) { Out[_off__metile_v44_r21] = static_cast(_metile_v39_r21); }\n if (_metile_v43_r22) { Out[_off__metile_v44_r22] = static_cast(_metile_v39_r22); }\n if (_metile_v43_r23) { Out[_off__metile_v44_r23] = static_cast(_metile_v39_r23); }\n }\n if ((_metile_v43_r24) && (_metile_v43_r25) && (_metile_v43_r26) && (_metile_v43_r27) && (long(_off__metile_v44_r25) == long(_off__metile_v44_r24) + 1) && (long(_off__metile_v44_r26) == long(_off__metile_v44_r24) + 2) && (long(_off__metile_v44_r27) == long(_off__metile_v44_r24) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r24) = packed_half4(half4(static_cast(_metile_v39_r24), static_cast(_metile_v39_r25), static_cast(_metile_v39_r26), static_cast(_metile_v39_r27)));\n } else {\n if (_metile_v43_r24) { Out[_off__metile_v44_r24] = static_cast(_metile_v39_r24); }\n if (_metile_v43_r25) { Out[_off__metile_v44_r25] = static_cast(_metile_v39_r25); }\n if (_metile_v43_r26) { Out[_off__metile_v44_r26] = static_cast(_metile_v39_r26); }\n if (_metile_v43_r27) { Out[_off__metile_v44_r27] = static_cast(_metile_v39_r27); }\n }\n if ((_metile_v43_r28) && (_metile_v43_r29) && (_metile_v43_r30) && (_metile_v43_r31) && (long(_off__metile_v44_r29) == long(_off__metile_v44_r28) + 1) && (long(_off__metile_v44_r30) == long(_off__metile_v44_r28) + 2) && (long(_off__metile_v44_r31) == long(_off__metile_v44_r28) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r28) = packed_half4(half4(static_cast(_metile_v39_r28), static_cast(_metile_v39_r29), static_cast(_metile_v39_r30), static_cast(_metile_v39_r31)));\n } else {\n if (_metile_v43_r28) { Out[_off__metile_v44_r28] = static_cast(_metile_v39_r28); }\n if (_metile_v43_r29) { Out[_off__metile_v44_r29] = static_cast(_metile_v39_r29); }\n if (_metile_v43_r30) { Out[_off__metile_v44_r30] = static_cast(_metile_v39_r30); }\n if (_metile_v43_r31) { Out[_off__metile_v44_r31] = static_cast(_metile_v39_r31); }\n }\n}", "source_sha256": "e71f6e91f3f76564671db8d5ee10d9f8eb51e2c1e61e3c1f613552152e99fce6", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 32, 1, 1 ], "is_gemm": false, "prefer_ordered": false, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 32, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 32 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [], "double_buffered": false, "vectorized_loads": 16, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 32, "threads": 32, "scratch": null, "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 16, "grouped_stores": 8 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 540, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 209.7505, "control": 207.5, "speedup": 0.989270585767376 }, "gpu_us": { "candidate": 3.4999684430658817, "control": 1.625041477382183, "speedup": 0.4643017512348451 } } }, { "frozen_register4": { "pairs": 613, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.291, "control": 197.209, "speedup": 0.994543373123339 }, "gpu_us": { "candidate": 3.249966539442539, "control": 1.5416881069540977, "speedup": 0.4743704552781459 } } }, { "frozen_register4": { "pairs": 594, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.70850000000002, "control": 198.667, "speedup": 0.9898285324238884 }, "gpu_us": { "candidate": 3.2500247471034527, "control": 1.583306584507227, "speedup": 0.4871675472373959 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9912113451641024, "round_speedups": [ 0.989270585767376, 0.994543373123339, 0.9898285324238884 ], "candidate": 202.85727673652295, "control": 201.07443415033572 }, "gpu_us": { "speedup": 0.47518796709469463, "round_speedups": [ 0.4643017512348451, 0.4743704552781459, 0.4871675472373959 ], "candidate": 3.331270472737606, "control": 1.582979643782765 } } } }, { "name": "float16_1x1024", "dtype": "float16", "batches": 1, "width": 1024, "status": "measured", "variant": { "name": "register2_striped", "elements_per_thread": 2, "layout": "striped" }, "input_sha256": "3cc059cb43f2d2ee6f0120b1b81a1fb6efa6af199ab539eb734dc561564c6ebe", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 511;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 512;\n int _metile_register_index_ = int(_metile_register_packed_);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n threadgroup float _metile_register_reduction[16];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 16u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n}", "source_sha256": "7904a94ae16a9a4d931c40f756c878c87106b2c4dc49872d49e6df50e4e1317d", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 512, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 512, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 2 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 16, "bytes": 64 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 2, "threads": 512, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 617, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.75, "control": 197.417, "speedup": 0.9983160556257902 }, "gpu_us": { "candidate": 1.4583347365260124, "control": 1.5416881069540977, "speedup": 1.0571565418695617 } } }, { "frozen_register4": { "pairs": 618, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.02100000000002, "control": 197.063, "speedup": 0.9951621292691177 }, "gpu_us": { "candidate": 1.4999532140791416, "control": 1.5416881069540977, "speedup": 1.0278241297683264 } } }, { "frozen_register4": { "pairs": 620, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.312, "control": 199.3955, "speedup": 1.0054636128928154 }, "gpu_us": { "candidate": 1.4999532140791416, "control": 1.5416881069540977, "speedup": 1.0278241297683264 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9996379877396958, "round_speedups": [ 0.9983160556257902, 0.9951621292691177, 1.0054636128928154 ], "candidate": 198.0275337025379, "control": 197.95584530745984 }, "gpu_us": { "speedup": 1.0375100366592989, "round_speedups": [ 1.0571565418695617, 1.0278241297683264, 1.0278241297683264 ], "candidate": 1.485950065522463, "control": 1.5416881069540977 } } } }, { "name": "float16_1x1024", "dtype": "float16", "batches": 1, "width": 1024, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "3cc059cb43f2d2ee6f0120b1b81a1fb6efa6af199ab539eb734dc561564c6ebe", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "a30e8c10d04f7806837b7362bac4a0f599f0d6d17735fc2e88198ca5dcb4e73d", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 560, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.47899999999998, "control": 201.9375, "speedup": 1.007275076192519 }, "gpu_us": { "candidate": 1.500011421740055, "control": 1.5416881069540977, "speedup": 1.0277842452464105 } } }, { "frozen_register4": { "pairs": 584, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.083, "control": 199.5625, "speedup": 1.007469091239531 }, "gpu_us": { "candidate": 1.500011421740055, "control": 1.5416881069540977, "speedup": 1.0277842452464105 } } }, { "frozen_register4": { "pairs": 620, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.39600000000002, "control": 198.54149999999998, "speedup": 1.0007333817214055 }, "gpu_us": { "candidate": 1.500011421740055, "control": 1.5416881069540977, "speedup": 1.0277842452464105 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0051543009752808, "round_speedups": [ 1.007275076192519, 1.007469091239531, 1.0007333817214055 ], "candidate": 198.98316511762187, "control": 200.00878423965187 }, "gpu_us": { "speedup": 1.0277842452464105, "round_speedups": [ 1.0277842452464105, 1.0277842452464105, 1.0277842452464105 ], "candidate": 1.500011421740055, "control": 1.5416881069540977 } } } }, { "name": "float16_1x1024", "dtype": "float16", "batches": 1, "width": 1024, "status": "measured", "variant": { "name": "register4_blocked4", "elements_per_thread": 4, "layout": "blocked4" }, "input_sha256": "3cc059cb43f2d2ee6f0120b1b81a1fb6efa6af199ab539eb734dc561564c6ebe", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int((((_metile_bounded_thread >> 8) & 1u) << 0) | (((_metile_bounded_thread >> 9) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 6) & 1u) << 8) | (((_metile_bounded_thread >> 7) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 8) & 1u) << 0) | (((_metile_register_packed_ >> 9) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 6) & 1u) << 8) | (((_metile_register_packed_ >> 7) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 8) & 1u) << 0) | (((_metile_register_packed__ >> 9) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 6) & 1u) << 8) | (((_metile_register_packed__ >> 7) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 8) & 1u) << 0) | (((_metile_register_packed___ >> 9) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 6) & 1u) << 8) | (((_metile_register_packed___ >> 7) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = half4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n half _metile_v20_r0 = _metile_vector_load[0];\n half _metile_v20_r1 = _metile_vector_load[1];\n half _metile_v20_r2 = _metile_vector_load[2];\n half _metile_v20_r3 = _metile_vector_load[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half4 _metile_vector_load_;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load_ = half4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load_[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load_[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load_[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load_[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n half _metile_v36_r0 = _metile_vector_load_[0];\n half _metile_v36_r1 = _metile_vector_load_[1];\n half _metile_v36_r2 = _metile_vector_load_[2];\n half _metile_v36_r3 = _metile_vector_load_[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_half4(half4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n}", "source_sha256": "2f5456f3b5088f163701ddb7dda6355b247755e6037315115cb7598baca96276", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 2, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 2, "grouped_stores": 1 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 617, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.833, "control": 199.875, "speedup": 1.0052405787771648 }, "gpu_us": { "candidate": 1.6249832697212696, "control": 1.5416881069540977, "speedup": 0.9487409105562918 } } }, { "frozen_register4": { "pairs": 618, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.8545, "control": 199.58350000000002, "speedup": 1.003665996997805 }, "gpu_us": { "candidate": 1.6249832697212696, "control": 1.5416881069540977, "speedup": 0.9487409105562918 } } }, { "frozen_register4": { "pairs": 621, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.0, "control": 197.875, "speedup": 0.9993686868686869 }, "gpu_us": { "candidate": 1.6249832697212696, "control": 1.583306584507227, "speedup": 0.9743525450442383 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.002755347627548, "round_speedups": [ 1.0052405787771648, 1.003665996997805, 0.9993686868686869 ], "candidate": 198.562101058468, "control": 199.1092086725405 }, "gpu_us": { "speedup": 0.9572024320544452, "round_speedups": [ 0.9487409105562918, 0.9487409105562918, 0.9743525450442383 ], "candidate": 1.6249832697212696, "control": 1.5554379378249839 } } } }, { "name": "float16_1x1024", "dtype": "float16", "batches": 1, "width": 1024, "status": "measured", "variant": { "name": "register8_striped", "elements_per_thread": 8, "layout": "striped" }, "input_sha256": "3cc059cb43f2d2ee6f0120b1b81a1fb6efa6af199ab539eb734dc561564c6ebe", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 127;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 128;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 256;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 384;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 512;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 640;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 768;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 896;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n half _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n half _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n half _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n half _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_____ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum______ = _metile_register_sum____ + _metile_register_sum_____;\n threadgroup float _metile_register_reduction[4];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 4u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n half _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n half _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n half _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n half _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n}", "source_sha256": "c52eee1a22cd9b99c0ecec2256f602f592be4c6e60d377eb925a553835a7a584", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 128, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 128, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 8 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 4, "bytes": 16 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 8, "threads": 128, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 619, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.625, "control": 199.083, "speedup": 1.0023058527375708 }, "gpu_us": { "candidate": 1.5416881069540977, "control": 1.5416881069540977, "speedup": 1.0 } } }, { "frozen_register4": { "pairs": 597, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.208, "control": 197.0, "speedup": 0.9839766642691601 }, "gpu_us": { "candidate": 1.5416881069540977, "control": 1.583306584507227, "speedup": 1.0269953937929472 } } }, { "frozen_register4": { "pairs": 600, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.4375, "control": 201.167, "speedup": 1.018889522000633 }, "gpu_us": { "candidate": 1.5416881069540977, "control": 1.583306584507227, "speedup": 1.0269953937929472 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0016224585174849, "round_speedups": [ 1.0023058527375708, 0.9839766642691601, 1.018889522000633 ], "candidate": 198.7535953496987, "control": 199.0760648133547 }, "gpu_us": { "speedup": 1.017916913304309, "round_speedups": [ 1.0, 1.0269953937929472, 1.0269953937929472 ], "candidate": 1.5416881069540977, "control": 1.5693103991086783 } } } }, { "name": "float16_32x1024", "dtype": "float16", "batches": 32, "width": 1024, "status": "measured", "variant": { "name": "register16_striped", "elements_per_thread": 16, "layout": "striped" }, "input_sha256": "6e821d0e3f7ad3cc0206f556836dd56fc15c5cc3181cc0547765f5bce1880ac4", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 63;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 64;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 128;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 192;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 256;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 320;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 384;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 448;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n int _metile_register_packed________ = _metile_bounded_thread + 512;\n int _metile_register_index________ = int(_metile_register_packed________);\n int _metile_register_packed_________ = _metile_bounded_thread + 576;\n int _metile_register_index_________ = int(_metile_register_packed_________);\n int _metile_register_packed__________ = _metile_bounded_thread + 640;\n int _metile_register_index__________ = int(_metile_register_packed__________);\n int _metile_register_packed___________ = _metile_bounded_thread + 704;\n int _metile_register_index___________ = int(_metile_register_packed___________);\n int _metile_register_packed____________ = _metile_bounded_thread + 768;\n int _metile_register_index____________ = int(_metile_register_packed____________);\n int _metile_register_packed_____________ = _metile_bounded_thread + 832;\n int _metile_register_index_____________ = int(_metile_register_packed_____________);\n int _metile_register_packed______________ = _metile_bounded_thread + 896;\n int _metile_register_index______________ = int(_metile_register_packed______________);\n int _metile_register_packed_______________ = _metile_bounded_thread + 960;\n int _metile_register_index_______________ = int(_metile_register_packed_______________);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v17_r8 = _metile_register_index________ < 1024;\n bool _metile_v17_r9 = _metile_register_index_________ < 1024;\n bool _metile_v17_r10 = _metile_register_index__________ < 1024;\n bool _metile_v17_r11 = _metile_register_index___________ < 1024;\n bool _metile_v17_r12 = _metile_register_index____________ < 1024;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v17_r14 = _metile_register_index______________ < 1024;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n half _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n half _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n half _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n half _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n half _metile_v20_r8 = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n half _metile_v20_r9 = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n half _metile_v20_r10 = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n half _metile_v20_r11 = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n half _metile_v20_r12 = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n half _metile_v20_r13 = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n half _metile_v20_r14 = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n half _metile_v20_r15 = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________ = _metile_register_sum____________ + _metile_register_sum_____________;\n threadgroup float _metile_register_reduction[2];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______________);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 2u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v33_r8 = _metile_register_index________ < 1024;\n bool _metile_v33_r9 = _metile_register_index_________ < 1024;\n bool _metile_v33_r10 = _metile_register_index__________ < 1024;\n bool _metile_v33_r11 = _metile_register_index___________ < 1024;\n bool _metile_v33_r12 = _metile_register_index____________ < 1024;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v33_r14 = _metile_register_index______________ < 1024;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n half _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n half _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n half _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n half _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n half _metile_v36_r8 = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n half _metile_v36_r9 = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n half _metile_v36_r10 = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n half _metile_v36_r11 = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n half _metile_v36_r12 = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n half _metile_v36_r13 = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n half _metile_v36_r14 = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n half _metile_v36_r15 = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v42_r8 = _metile_register_index________ < 1024;\n bool _metile_v42_r9 = _metile_register_index_________ < 1024;\n bool _metile_v42_r10 = _metile_register_index__________ < 1024;\n bool _metile_v42_r11 = _metile_register_index___________ < 1024;\n bool _metile_v42_r12 = _metile_register_index____________ < 1024;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v42_r14 = _metile_register_index______________ < 1024;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = _metile_v39_r8; }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = _metile_v39_r9; }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = _metile_v39_r10; }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = _metile_v39_r11; }\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = _metile_v39_r12; }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = _metile_v39_r13; }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = _metile_v39_r14; }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = _metile_v39_r15; }\n}", "source_sha256": "80e4ab993c9dda4e9764e5d0ae2ad910cd88a101c3d4ec77af99d486d6933bdb", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 64, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 64, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 16 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 2, "bytes": 8 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 16, "threads": 64, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 599, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.667, "control": 199.667, "speedup": 1.0050335486014286 }, "gpu_us": { "candidate": 1.9583385437726974, "control": 1.9166618585586548, "speedup": 0.9787183450243728 } } }, { "frozen_register4": { "pairs": 616, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.41649999999998, "control": 199.208, "speedup": 1.003989083569159 }, "gpu_us": { "candidate": 1.958280336111784, "control": 1.9166618585586548, "speedup": 0.9787474363166186 } } }, { "frozen_register4": { "pairs": 452, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.0, "control": 201.10399999999998, "speedup": 1.00552 }, "gpu_us": { "candidate": 1.9583385437726974, "control": 1.958280336111784, "speedup": 0.9999702770181904 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0048473410471181, "round_speedups": [ 1.0050335486014286, 1.003989083569159, 1.00552 ], "candidate": 199.02662170128946, "control": 199.99137161413125 }, "gpu_us": { "speedup": 0.9857614248351358, "round_speedups": [ 0.9787183450243728, 0.9787474363166186, 0.9999702770181904 ], "candidate": 1.9583191410268224, "control": 1.93043546674052 } } } }, { "name": "float16_32x1024", "dtype": "float16", "batches": 32, "width": 1024, "status": "measured", "variant": { "name": "register16_blocked4", "elements_per_thread": 16, "layout": "blocked4" }, "input_sha256": "6e821d0e3f7ad3cc0206f556836dd56fc15c5cc3181cc0547765f5bce1880ac4", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 63;\n int _metile_register_index = int((((_metile_bounded_thread >> 6) & 1u) << 0) | (((_metile_bounded_thread >> 7) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 8) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 64;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 6) & 1u) << 0) | (((_metile_register_packed_ >> 7) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 8) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 128;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 6) & 1u) << 0) | (((_metile_register_packed__ >> 7) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 8) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 192;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 6) & 1u) << 0) | (((_metile_register_packed___ >> 7) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 8) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 256;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 6) & 1u) << 0) | (((_metile_register_packed____ >> 7) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 5) & 1u) << 7) | (((_metile_register_packed____ >> 8) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 320;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 6) & 1u) << 0) | (((_metile_register_packed_____ >> 7) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 5) & 1u) << 7) | (((_metile_register_packed_____ >> 8) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 384;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 6) & 1u) << 0) | (((_metile_register_packed______ >> 7) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 5) & 1u) << 7) | (((_metile_register_packed______ >> 8) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 448;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 6) & 1u) << 0) | (((_metile_register_packed_______ >> 7) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 5) & 1u) << 7) | (((_metile_register_packed_______ >> 8) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n int _metile_register_packed________ = _metile_bounded_thread + 512;\n int _metile_register_index________ = int((((_metile_register_packed________ >> 6) & 1u) << 0) | (((_metile_register_packed________ >> 7) & 1u) << 1) | (((_metile_register_packed________ >> 0) & 1u) << 2) | (((_metile_register_packed________ >> 1) & 1u) << 3) | (((_metile_register_packed________ >> 2) & 1u) << 4) | (((_metile_register_packed________ >> 3) & 1u) << 5) | (((_metile_register_packed________ >> 4) & 1u) << 6) | (((_metile_register_packed________ >> 5) & 1u) << 7) | (((_metile_register_packed________ >> 8) & 1u) << 8) | (((_metile_register_packed________ >> 9) & 1u) << 9));\n int _metile_register_packed_________ = _metile_bounded_thread + 576;\n int _metile_register_index_________ = int((((_metile_register_packed_________ >> 6) & 1u) << 0) | (((_metile_register_packed_________ >> 7) & 1u) << 1) | (((_metile_register_packed_________ >> 0) & 1u) << 2) | (((_metile_register_packed_________ >> 1) & 1u) << 3) | (((_metile_register_packed_________ >> 2) & 1u) << 4) | (((_metile_register_packed_________ >> 3) & 1u) << 5) | (((_metile_register_packed_________ >> 4) & 1u) << 6) | (((_metile_register_packed_________ >> 5) & 1u) << 7) | (((_metile_register_packed_________ >> 8) & 1u) << 8) | (((_metile_register_packed_________ >> 9) & 1u) << 9));\n int _metile_register_packed__________ = _metile_bounded_thread + 640;\n int _metile_register_index__________ = int((((_metile_register_packed__________ >> 6) & 1u) << 0) | (((_metile_register_packed__________ >> 7) & 1u) << 1) | (((_metile_register_packed__________ >> 0) & 1u) << 2) | (((_metile_register_packed__________ >> 1) & 1u) << 3) | (((_metile_register_packed__________ >> 2) & 1u) << 4) | (((_metile_register_packed__________ >> 3) & 1u) << 5) | (((_metile_register_packed__________ >> 4) & 1u) << 6) | (((_metile_register_packed__________ >> 5) & 1u) << 7) | (((_metile_register_packed__________ >> 8) & 1u) << 8) | (((_metile_register_packed__________ >> 9) & 1u) << 9));\n int _metile_register_packed___________ = _metile_bounded_thread + 704;\n int _metile_register_index___________ = int((((_metile_register_packed___________ >> 6) & 1u) << 0) | (((_metile_register_packed___________ >> 7) & 1u) << 1) | (((_metile_register_packed___________ >> 0) & 1u) << 2) | (((_metile_register_packed___________ >> 1) & 1u) << 3) | (((_metile_register_packed___________ >> 2) & 1u) << 4) | (((_metile_register_packed___________ >> 3) & 1u) << 5) | (((_metile_register_packed___________ >> 4) & 1u) << 6) | (((_metile_register_packed___________ >> 5) & 1u) << 7) | (((_metile_register_packed___________ >> 8) & 1u) << 8) | (((_metile_register_packed___________ >> 9) & 1u) << 9));\n int _metile_register_packed____________ = _metile_bounded_thread + 768;\n int _metile_register_index____________ = int((((_metile_register_packed____________ >> 6) & 1u) << 0) | (((_metile_register_packed____________ >> 7) & 1u) << 1) | (((_metile_register_packed____________ >> 0) & 1u) << 2) | (((_metile_register_packed____________ >> 1) & 1u) << 3) | (((_metile_register_packed____________ >> 2) & 1u) << 4) | (((_metile_register_packed____________ >> 3) & 1u) << 5) | (((_metile_register_packed____________ >> 4) & 1u) << 6) | (((_metile_register_packed____________ >> 5) & 1u) << 7) | (((_metile_register_packed____________ >> 8) & 1u) << 8) | (((_metile_register_packed____________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________ = _metile_bounded_thread + 832;\n int _metile_register_index_____________ = int((((_metile_register_packed_____________ >> 6) & 1u) << 0) | (((_metile_register_packed_____________ >> 7) & 1u) << 1) | (((_metile_register_packed_____________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________ >> 5) & 1u) << 7) | (((_metile_register_packed_____________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________ >> 9) & 1u) << 9));\n int _metile_register_packed______________ = _metile_bounded_thread + 896;\n int _metile_register_index______________ = int((((_metile_register_packed______________ >> 6) & 1u) << 0) | (((_metile_register_packed______________ >> 7) & 1u) << 1) | (((_metile_register_packed______________ >> 0) & 1u) << 2) | (((_metile_register_packed______________ >> 1) & 1u) << 3) | (((_metile_register_packed______________ >> 2) & 1u) << 4) | (((_metile_register_packed______________ >> 3) & 1u) << 5) | (((_metile_register_packed______________ >> 4) & 1u) << 6) | (((_metile_register_packed______________ >> 5) & 1u) << 7) | (((_metile_register_packed______________ >> 8) & 1u) << 8) | (((_metile_register_packed______________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________ = _metile_bounded_thread + 960;\n int _metile_register_index_______________ = int((((_metile_register_packed_______________ >> 6) & 1u) << 0) | (((_metile_register_packed_______________ >> 7) & 1u) << 1) | (((_metile_register_packed_______________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________ >> 5) & 1u) << 7) | (((_metile_register_packed_______________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v17_r8 = _metile_register_index________ < 1024;\n bool _metile_v17_r9 = _metile_register_index_________ < 1024;\n bool _metile_v17_r10 = _metile_register_index__________ < 1024;\n bool _metile_v17_r11 = _metile_register_index___________ < 1024;\n bool _metile_v17_r12 = _metile_register_index____________ < 1024;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v17_r14 = _metile_register_index______________ < 1024;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n half4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = half4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n half _metile_v20_r0 = _metile_vector_load[0];\n half _metile_v20_r1 = _metile_vector_load[1];\n half _metile_v20_r2 = _metile_vector_load[2];\n half _metile_v20_r3 = _metile_vector_load[3];\n half4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = half4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n half _metile_v20_r4 = _metile_vector_load_[0];\n half _metile_v20_r5 = _metile_vector_load_[1];\n half _metile_v20_r6 = _metile_vector_load_[2];\n half _metile_v20_r7 = _metile_vector_load_[3];\n half4 _metile_vector_load__;\n if ((_metile_v18_r8) && (_metile_v18_r9) && (_metile_v18_r10) && (_metile_v18_r11) && (long(_off__metile_v19_r9) == long(_off__metile_v19_r8) + 1) && (long(_off__metile_v19_r10) == long(_off__metile_v19_r8) + 2) && (long(_off__metile_v19_r11) == long(_off__metile_v19_r8) + 3)) {\n _metile_vector_load__ = half4(*reinterpret_cast(X + _off__metile_v19_r8));\n } else {\n _metile_vector_load__[0] = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n _metile_vector_load__[1] = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n _metile_vector_load__[2] = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n _metile_vector_load__[3] = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n }\n half _metile_v20_r8 = _metile_vector_load__[0];\n half _metile_v20_r9 = _metile_vector_load__[1];\n half _metile_v20_r10 = _metile_vector_load__[2];\n half _metile_v20_r11 = _metile_vector_load__[3];\n half4 _metile_vector_load___;\n if ((_metile_v18_r12) && (_metile_v18_r13) && (_metile_v18_r14) && (_metile_v18_r15) && (long(_off__metile_v19_r13) == long(_off__metile_v19_r12) + 1) && (long(_off__metile_v19_r14) == long(_off__metile_v19_r12) + 2) && (long(_off__metile_v19_r15) == long(_off__metile_v19_r12) + 3)) {\n _metile_vector_load___ = half4(*reinterpret_cast(X + _off__metile_v19_r12));\n } else {\n _metile_vector_load___[0] = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n _metile_vector_load___[1] = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n _metile_vector_load___[2] = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n _metile_vector_load___[3] = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n }\n half _metile_v20_r12 = _metile_vector_load___[0];\n half _metile_v20_r13 = _metile_vector_load___[1];\n half _metile_v20_r14 = _metile_vector_load___[2];\n half _metile_v20_r15 = _metile_vector_load___[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________ = _metile_register_sum____________ + _metile_register_sum_____________;\n threadgroup float _metile_register_reduction[2];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______________);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 2u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v33_r8 = _metile_register_index________ < 1024;\n bool _metile_v33_r9 = _metile_register_index_________ < 1024;\n bool _metile_v33_r10 = _metile_register_index__________ < 1024;\n bool _metile_v33_r11 = _metile_register_index___________ < 1024;\n bool _metile_v33_r12 = _metile_register_index____________ < 1024;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v33_r14 = _metile_register_index______________ < 1024;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n half4 _metile_vector_load____;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load____ = half4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load____[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load____[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load____[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load____[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n half _metile_v36_r0 = _metile_vector_load____[0];\n half _metile_v36_r1 = _metile_vector_load____[1];\n half _metile_v36_r2 = _metile_vector_load____[2];\n half _metile_v36_r3 = _metile_vector_load____[3];\n half4 _metile_vector_load_____;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load_____ = half4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load_____[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load_____[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load_____[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load_____[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n half _metile_v36_r4 = _metile_vector_load_____[0];\n half _metile_v36_r5 = _metile_vector_load_____[1];\n half _metile_v36_r6 = _metile_vector_load_____[2];\n half _metile_v36_r7 = _metile_vector_load_____[3];\n half4 _metile_vector_load______;\n if ((_metile_v34_r8) && (_metile_v34_r9) && (_metile_v34_r10) && (_metile_v34_r11) && (long(_metile_register_index_________) == long(_metile_register_index________) + 1) && (long(_metile_register_index__________) == long(_metile_register_index________) + 2) && (long(_metile_register_index___________) == long(_metile_register_index________) + 3)) {\n _metile_vector_load______ = half4(*reinterpret_cast(W + _metile_register_index________));\n } else {\n _metile_vector_load______[0] = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n _metile_vector_load______[1] = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n _metile_vector_load______[2] = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n _metile_vector_load______[3] = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n }\n half _metile_v36_r8 = _metile_vector_load______[0];\n half _metile_v36_r9 = _metile_vector_load______[1];\n half _metile_v36_r10 = _metile_vector_load______[2];\n half _metile_v36_r11 = _metile_vector_load______[3];\n half4 _metile_vector_load_______;\n if ((_metile_v34_r12) && (_metile_v34_r13) && (_metile_v34_r14) && (_metile_v34_r15) && (long(_metile_register_index_____________) == long(_metile_register_index____________) + 1) && (long(_metile_register_index______________) == long(_metile_register_index____________) + 2) && (long(_metile_register_index_______________) == long(_metile_register_index____________) + 3)) {\n _metile_vector_load_______ = half4(*reinterpret_cast(W + _metile_register_index____________));\n } else {\n _metile_vector_load_______[0] = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n _metile_vector_load_______[1] = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n _metile_vector_load_______[2] = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n _metile_vector_load_______[3] = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n }\n half _metile_v36_r12 = _metile_vector_load_______[0];\n half _metile_v36_r13 = _metile_vector_load_______[1];\n half _metile_v36_r14 = _metile_vector_load_______[2];\n half _metile_v36_r15 = _metile_vector_load_______[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v42_r8 = _metile_register_index________ < 1024;\n bool _metile_v42_r9 = _metile_register_index_________ < 1024;\n bool _metile_v42_r10 = _metile_register_index__________ < 1024;\n bool _metile_v42_r11 = _metile_register_index___________ < 1024;\n bool _metile_v42_r12 = _metile_register_index____________ < 1024;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v42_r14 = _metile_register_index______________ < 1024;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_half4(half4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_half4(half4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n if ((_metile_v43_r8) && (_metile_v43_r9) && (_metile_v43_r10) && (_metile_v43_r11) && (long(_off__metile_v44_r9) == long(_off__metile_v44_r8) + 1) && (long(_off__metile_v44_r10) == long(_off__metile_v44_r8) + 2) && (long(_off__metile_v44_r11) == long(_off__metile_v44_r8) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r8) = packed_half4(half4(static_cast(_metile_v39_r8), static_cast(_metile_v39_r9), static_cast(_metile_v39_r10), static_cast(_metile_v39_r11)));\n } else {\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = static_cast(_metile_v39_r8); }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = static_cast(_metile_v39_r9); }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = static_cast(_metile_v39_r10); }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = static_cast(_metile_v39_r11); }\n }\n if ((_metile_v43_r12) && (_metile_v43_r13) && (_metile_v43_r14) && (_metile_v43_r15) && (long(_off__metile_v44_r13) == long(_off__metile_v44_r12) + 1) && (long(_off__metile_v44_r14) == long(_off__metile_v44_r12) + 2) && (long(_off__metile_v44_r15) == long(_off__metile_v44_r12) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r12) = packed_half4(half4(static_cast(_metile_v39_r12), static_cast(_metile_v39_r13), static_cast(_metile_v39_r14), static_cast(_metile_v39_r15)));\n } else {\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = static_cast(_metile_v39_r12); }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = static_cast(_metile_v39_r13); }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = static_cast(_metile_v39_r14); }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = static_cast(_metile_v39_r15); }\n }\n}", "source_sha256": "fd2a997847283829837787e56478df38b489706b6dd7fc7e98f217fcdab4f642", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 64, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 64, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 16 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 2, "bytes": 8 } ], "double_buffered": false, "vectorized_loads": 8, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 16, "threads": 64, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 8, "grouped_stores": 4 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 603, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.75, "control": 198.291, "speedup": 1.0027357774968395 }, "gpu_us": { "candidate": 2.500019036233425, "control": 1.9166618585586548, "speedup": 0.7666589057043073 } } }, { "frozen_register4": { "pairs": 596, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.0, "control": 197.7295, "speedup": 1.0037030456852791 }, "gpu_us": { "candidate": 2.500019036233425, "control": 1.9167200662195683, "speedup": 0.7666821885913854 } } }, { "frozen_register4": { "pairs": 604, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.667, "control": 199.04149999999998, "speedup": 1.0018850639512349 }, "gpu_us": { "candidate": 2.500019036233425, "control": 1.9166618585586548, "speedup": 0.7666589057043073 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0027743540193081, "round_speedups": [ 1.0027357774968395, 1.0037030456852791, 1.0018850639512349 ], "candidate": 197.8044923572368, "control": 198.35327204564544 }, "gpu_us": { "speedup": 0.766666666588103, "round_speedups": [ 0.7666589057043073, 0.7666821885913854, 0.7666589057043073 ], "candidate": 2.500019036233425, "control": 1.9166812609158819 } } } }, { "name": "float16_32x1024", "dtype": "float16", "batches": 32, "width": 1024, "status": "measured", "variant": { "name": "register32_striped", "elements_per_thread": 32, "layout": "striped" }, "input_sha256": "6e821d0e3f7ad3cc0206f556836dd56fc15c5cc3181cc0547765f5bce1880ac4", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 31;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 32;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 64;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 96;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 128;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 160;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 192;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 224;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n int _metile_register_packed________ = _metile_bounded_thread + 256;\n int _metile_register_index________ = int(_metile_register_packed________);\n int _metile_register_packed_________ = _metile_bounded_thread + 288;\n int _metile_register_index_________ = int(_metile_register_packed_________);\n int _metile_register_packed__________ = _metile_bounded_thread + 320;\n int _metile_register_index__________ = int(_metile_register_packed__________);\n int _metile_register_packed___________ = _metile_bounded_thread + 352;\n int _metile_register_index___________ = int(_metile_register_packed___________);\n int _metile_register_packed____________ = _metile_bounded_thread + 384;\n int _metile_register_index____________ = int(_metile_register_packed____________);\n int _metile_register_packed_____________ = _metile_bounded_thread + 416;\n int _metile_register_index_____________ = int(_metile_register_packed_____________);\n int _metile_register_packed______________ = _metile_bounded_thread + 448;\n int _metile_register_index______________ = int(_metile_register_packed______________);\n int _metile_register_packed_______________ = _metile_bounded_thread + 480;\n int _metile_register_index_______________ = int(_metile_register_packed_______________);\n int _metile_register_packed________________ = _metile_bounded_thread + 512;\n int _metile_register_index________________ = int(_metile_register_packed________________);\n int _metile_register_packed_________________ = _metile_bounded_thread + 544;\n int _metile_register_index_________________ = int(_metile_register_packed_________________);\n int _metile_register_packed__________________ = _metile_bounded_thread + 576;\n int _metile_register_index__________________ = int(_metile_register_packed__________________);\n int _metile_register_packed___________________ = _metile_bounded_thread + 608;\n int _metile_register_index___________________ = int(_metile_register_packed___________________);\n int _metile_register_packed____________________ = _metile_bounded_thread + 640;\n int _metile_register_index____________________ = int(_metile_register_packed____________________);\n int _metile_register_packed_____________________ = _metile_bounded_thread + 672;\n int _metile_register_index_____________________ = int(_metile_register_packed_____________________);\n int _metile_register_packed______________________ = _metile_bounded_thread + 704;\n int _metile_register_index______________________ = int(_metile_register_packed______________________);\n int _metile_register_packed_______________________ = _metile_bounded_thread + 736;\n int _metile_register_index_______________________ = int(_metile_register_packed_______________________);\n int _metile_register_packed________________________ = _metile_bounded_thread + 768;\n int _metile_register_index________________________ = int(_metile_register_packed________________________);\n int _metile_register_packed_________________________ = _metile_bounded_thread + 800;\n int _metile_register_index_________________________ = int(_metile_register_packed_________________________);\n int _metile_register_packed__________________________ = _metile_bounded_thread + 832;\n int _metile_register_index__________________________ = int(_metile_register_packed__________________________);\n int _metile_register_packed___________________________ = _metile_bounded_thread + 864;\n int _metile_register_index___________________________ = int(_metile_register_packed___________________________);\n int _metile_register_packed____________________________ = _metile_bounded_thread + 896;\n int _metile_register_index____________________________ = int(_metile_register_packed____________________________);\n int _metile_register_packed_____________________________ = _metile_bounded_thread + 928;\n int _metile_register_index_____________________________ = int(_metile_register_packed_____________________________);\n int _metile_register_packed______________________________ = _metile_bounded_thread + 960;\n int _metile_register_index______________________________ = int(_metile_register_packed______________________________);\n int _metile_register_packed_______________________________ = _metile_bounded_thread + 992;\n int _metile_register_index_______________________________ = int(_metile_register_packed_______________________________);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v16_r16 = _metile_register_index________________ >= 0;\n bool _metile_v16_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v16_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v16_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v16_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v16_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v16_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v16_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v16_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v16_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v16_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v16_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v16_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v16_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v16_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v16_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v17_r8 = _metile_register_index________ < 1024;\n bool _metile_v17_r9 = _metile_register_index_________ < 1024;\n bool _metile_v17_r10 = _metile_register_index__________ < 1024;\n bool _metile_v17_r11 = _metile_register_index___________ < 1024;\n bool _metile_v17_r12 = _metile_register_index____________ < 1024;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v17_r14 = _metile_register_index______________ < 1024;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v17_r16 = _metile_register_index________________ < 1024;\n bool _metile_v17_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v17_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v17_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v17_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v17_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v17_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v17_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v17_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v17_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v17_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v17_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v17_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v17_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v17_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v17_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n bool _metile_v18_r16 = _metile_v16_r16 & _metile_v17_r16;\n bool _metile_v18_r17 = _metile_v16_r17 & _metile_v17_r17;\n bool _metile_v18_r18 = _metile_v16_r18 & _metile_v17_r18;\n bool _metile_v18_r19 = _metile_v16_r19 & _metile_v17_r19;\n bool _metile_v18_r20 = _metile_v16_r20 & _metile_v17_r20;\n bool _metile_v18_r21 = _metile_v16_r21 & _metile_v17_r21;\n bool _metile_v18_r22 = _metile_v16_r22 & _metile_v17_r22;\n bool _metile_v18_r23 = _metile_v16_r23 & _metile_v17_r23;\n bool _metile_v18_r24 = _metile_v16_r24 & _metile_v17_r24;\n bool _metile_v18_r25 = _metile_v16_r25 & _metile_v17_r25;\n bool _metile_v18_r26 = _metile_v16_r26 & _metile_v17_r26;\n bool _metile_v18_r27 = _metile_v16_r27 & _metile_v17_r27;\n bool _metile_v18_r28 = _metile_v16_r28 & _metile_v17_r28;\n bool _metile_v18_r29 = _metile_v16_r29 & _metile_v17_r29;\n bool _metile_v18_r30 = _metile_v16_r30 & _metile_v17_r30;\n bool _metile_v18_r31 = _metile_v16_r31 & _metile_v17_r31;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n int _off__metile_v19_r16 = v2 + _metile_register_index________________;\n int _off__metile_v19_r17 = v2 + _metile_register_index_________________;\n int _off__metile_v19_r18 = v2 + _metile_register_index__________________;\n int _off__metile_v19_r19 = v2 + _metile_register_index___________________;\n int _off__metile_v19_r20 = v2 + _metile_register_index____________________;\n int _off__metile_v19_r21 = v2 + _metile_register_index_____________________;\n int _off__metile_v19_r22 = v2 + _metile_register_index______________________;\n int _off__metile_v19_r23 = v2 + _metile_register_index_______________________;\n int _off__metile_v19_r24 = v2 + _metile_register_index________________________;\n int _off__metile_v19_r25 = v2 + _metile_register_index_________________________;\n int _off__metile_v19_r26 = v2 + _metile_register_index__________________________;\n int _off__metile_v19_r27 = v2 + _metile_register_index___________________________;\n int _off__metile_v19_r28 = v2 + _metile_register_index____________________________;\n int _off__metile_v19_r29 = v2 + _metile_register_index_____________________________;\n int _off__metile_v19_r30 = v2 + _metile_register_index______________________________;\n int _off__metile_v19_r31 = v2 + _metile_register_index_______________________________;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n half _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n half _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n half _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n half _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n half _metile_v20_r8 = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n half _metile_v20_r9 = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n half _metile_v20_r10 = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n half _metile_v20_r11 = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n half _metile_v20_r12 = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n half _metile_v20_r13 = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n half _metile_v20_r14 = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n half _metile_v20_r15 = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n half _metile_v20_r16 = _metile_v18_r16 ? X[_off__metile_v19_r16] : static_cast(0);\n half _metile_v20_r17 = _metile_v18_r17 ? X[_off__metile_v19_r17] : static_cast(0);\n half _metile_v20_r18 = _metile_v18_r18 ? X[_off__metile_v19_r18] : static_cast(0);\n half _metile_v20_r19 = _metile_v18_r19 ? X[_off__metile_v19_r19] : static_cast(0);\n half _metile_v20_r20 = _metile_v18_r20 ? X[_off__metile_v19_r20] : static_cast(0);\n half _metile_v20_r21 = _metile_v18_r21 ? X[_off__metile_v19_r21] : static_cast(0);\n half _metile_v20_r22 = _metile_v18_r22 ? X[_off__metile_v19_r22] : static_cast(0);\n half _metile_v20_r23 = _metile_v18_r23 ? X[_off__metile_v19_r23] : static_cast(0);\n half _metile_v20_r24 = _metile_v18_r24 ? X[_off__metile_v19_r24] : static_cast(0);\n half _metile_v20_r25 = _metile_v18_r25 ? X[_off__metile_v19_r25] : static_cast(0);\n half _metile_v20_r26 = _metile_v18_r26 ? X[_off__metile_v19_r26] : static_cast(0);\n half _metile_v20_r27 = _metile_v18_r27 ? X[_off__metile_v19_r27] : static_cast(0);\n half _metile_v20_r28 = _metile_v18_r28 ? X[_off__metile_v19_r28] : static_cast(0);\n half _metile_v20_r29 = _metile_v18_r29 ? X[_off__metile_v19_r29] : static_cast(0);\n half _metile_v20_r30 = _metile_v18_r30 ? X[_off__metile_v19_r30] : static_cast(0);\n half _metile_v20_r31 = _metile_v18_r31 ? X[_off__metile_v19_r31] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v21_r16 = static_cast(_metile_v20_r16);\n float _metile_v21_r17 = static_cast(_metile_v20_r17);\n float _metile_v21_r18 = static_cast(_metile_v20_r18);\n float _metile_v21_r19 = static_cast(_metile_v20_r19);\n float _metile_v21_r20 = static_cast(_metile_v20_r20);\n float _metile_v21_r21 = static_cast(_metile_v20_r21);\n float _metile_v21_r22 = static_cast(_metile_v20_r22);\n float _metile_v21_r23 = static_cast(_metile_v20_r23);\n float _metile_v21_r24 = static_cast(_metile_v20_r24);\n float _metile_v21_r25 = static_cast(_metile_v20_r25);\n float _metile_v21_r26 = static_cast(_metile_v20_r26);\n float _metile_v21_r27 = static_cast(_metile_v20_r27);\n float _metile_v21_r28 = static_cast(_metile_v20_r28);\n float _metile_v21_r29 = static_cast(_metile_v20_r29);\n float _metile_v21_r30 = static_cast(_metile_v20_r30);\n float _metile_v21_r31 = static_cast(_metile_v20_r31);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_v22_r16 = _metile_v21_r16 * _metile_v21_r16;\n float _metile_v22_r17 = _metile_v21_r17 * _metile_v21_r17;\n float _metile_v22_r18 = _metile_v21_r18 * _metile_v21_r18;\n float _metile_v22_r19 = _metile_v21_r19 * _metile_v21_r19;\n float _metile_v22_r20 = _metile_v21_r20 * _metile_v21_r20;\n float _metile_v22_r21 = _metile_v21_r21 * _metile_v21_r21;\n float _metile_v22_r22 = _metile_v21_r22 * _metile_v21_r22;\n float _metile_v22_r23 = _metile_v21_r23 * _metile_v21_r23;\n float _metile_v22_r24 = _metile_v21_r24 * _metile_v21_r24;\n float _metile_v22_r25 = _metile_v21_r25 * _metile_v21_r25;\n float _metile_v22_r26 = _metile_v21_r26 * _metile_v21_r26;\n float _metile_v22_r27 = _metile_v21_r27 * _metile_v21_r27;\n float _metile_v22_r28 = _metile_v21_r28 * _metile_v21_r28;\n float _metile_v22_r29 = _metile_v21_r29 * _metile_v21_r29;\n float _metile_v22_r30 = _metile_v21_r30 * _metile_v21_r30;\n float _metile_v22_r31 = _metile_v21_r31 * _metile_v21_r31;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_v22_r16 + _metile_v22_r17;\n float _metile_register_sum_________ = _metile_v22_r18 + _metile_v22_r19;\n float _metile_register_sum__________ = _metile_v22_r20 + _metile_v22_r21;\n float _metile_register_sum___________ = _metile_v22_r22 + _metile_v22_r23;\n float _metile_register_sum____________ = _metile_v22_r24 + _metile_v22_r25;\n float _metile_register_sum_____________ = _metile_v22_r26 + _metile_v22_r27;\n float _metile_register_sum______________ = _metile_v22_r28 + _metile_v22_r29;\n float _metile_register_sum_______________ = _metile_v22_r30 + _metile_v22_r31;\n float _metile_register_sum________________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________________ = _metile_register_sum____________ + _metile_register_sum_____________;\n float _metile_register_sum_______________________ = _metile_register_sum______________ + _metile_register_sum_______________;\n float _metile_register_sum________________________ = _metile_register_sum________________ + _metile_register_sum_________________;\n float _metile_register_sum_________________________ = _metile_register_sum__________________ + _metile_register_sum___________________;\n float _metile_register_sum__________________________ = _metile_register_sum____________________ + _metile_register_sum_____________________;\n float _metile_register_sum___________________________ = _metile_register_sum______________________ + _metile_register_sum_______________________;\n float _metile_register_sum____________________________ = _metile_register_sum________________________ + _metile_register_sum_________________________;\n float _metile_register_sum_____________________________ = _metile_register_sum__________________________ + _metile_register_sum___________________________;\n float _metile_register_sum______________________________ = _metile_register_sum____________________________ + _metile_register_sum_____________________________;\n float v23 = simd_sum(_metile_register_sum______________________________);\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v32_r16 = _metile_register_index________________ >= 0;\n bool _metile_v32_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v32_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v32_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v32_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v32_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v32_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v32_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v32_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v32_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v32_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v32_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v32_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v32_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v32_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v32_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v33_r8 = _metile_register_index________ < 1024;\n bool _metile_v33_r9 = _metile_register_index_________ < 1024;\n bool _metile_v33_r10 = _metile_register_index__________ < 1024;\n bool _metile_v33_r11 = _metile_register_index___________ < 1024;\n bool _metile_v33_r12 = _metile_register_index____________ < 1024;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v33_r14 = _metile_register_index______________ < 1024;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v33_r16 = _metile_register_index________________ < 1024;\n bool _metile_v33_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v33_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v33_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v33_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v33_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v33_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v33_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v33_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v33_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v33_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v33_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v33_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v33_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v33_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v33_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n bool _metile_v34_r16 = _metile_v32_r16 & _metile_v33_r16;\n bool _metile_v34_r17 = _metile_v32_r17 & _metile_v33_r17;\n bool _metile_v34_r18 = _metile_v32_r18 & _metile_v33_r18;\n bool _metile_v34_r19 = _metile_v32_r19 & _metile_v33_r19;\n bool _metile_v34_r20 = _metile_v32_r20 & _metile_v33_r20;\n bool _metile_v34_r21 = _metile_v32_r21 & _metile_v33_r21;\n bool _metile_v34_r22 = _metile_v32_r22 & _metile_v33_r22;\n bool _metile_v34_r23 = _metile_v32_r23 & _metile_v33_r23;\n bool _metile_v34_r24 = _metile_v32_r24 & _metile_v33_r24;\n bool _metile_v34_r25 = _metile_v32_r25 & _metile_v33_r25;\n bool _metile_v34_r26 = _metile_v32_r26 & _metile_v33_r26;\n bool _metile_v34_r27 = _metile_v32_r27 & _metile_v33_r27;\n bool _metile_v34_r28 = _metile_v32_r28 & _metile_v33_r28;\n bool _metile_v34_r29 = _metile_v32_r29 & _metile_v33_r29;\n bool _metile_v34_r30 = _metile_v32_r30 & _metile_v33_r30;\n bool _metile_v34_r31 = _metile_v32_r31 & _metile_v33_r31;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n half _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n half _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n half _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n half _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n half _metile_v36_r8 = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n half _metile_v36_r9 = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n half _metile_v36_r10 = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n half _metile_v36_r11 = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n half _metile_v36_r12 = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n half _metile_v36_r13 = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n half _metile_v36_r14 = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n half _metile_v36_r15 = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n half _metile_v36_r16 = _metile_v34_r16 ? W[_metile_register_index________________] : static_cast(0);\n half _metile_v36_r17 = _metile_v34_r17 ? W[_metile_register_index_________________] : static_cast(0);\n half _metile_v36_r18 = _metile_v34_r18 ? W[_metile_register_index__________________] : static_cast(0);\n half _metile_v36_r19 = _metile_v34_r19 ? W[_metile_register_index___________________] : static_cast(0);\n half _metile_v36_r20 = _metile_v34_r20 ? W[_metile_register_index____________________] : static_cast(0);\n half _metile_v36_r21 = _metile_v34_r21 ? W[_metile_register_index_____________________] : static_cast(0);\n half _metile_v36_r22 = _metile_v34_r22 ? W[_metile_register_index______________________] : static_cast(0);\n half _metile_v36_r23 = _metile_v34_r23 ? W[_metile_register_index_______________________] : static_cast(0);\n half _metile_v36_r24 = _metile_v34_r24 ? W[_metile_register_index________________________] : static_cast(0);\n half _metile_v36_r25 = _metile_v34_r25 ? W[_metile_register_index_________________________] : static_cast(0);\n half _metile_v36_r26 = _metile_v34_r26 ? W[_metile_register_index__________________________] : static_cast(0);\n half _metile_v36_r27 = _metile_v34_r27 ? W[_metile_register_index___________________________] : static_cast(0);\n half _metile_v36_r28 = _metile_v34_r28 ? W[_metile_register_index____________________________] : static_cast(0);\n half _metile_v36_r29 = _metile_v34_r29 ? W[_metile_register_index_____________________________] : static_cast(0);\n half _metile_v36_r30 = _metile_v34_r30 ? W[_metile_register_index______________________________] : static_cast(0);\n half _metile_v36_r31 = _metile_v34_r31 ? W[_metile_register_index_______________________________] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v37_r16 = static_cast(_metile_v36_r16);\n float _metile_v37_r17 = static_cast(_metile_v36_r17);\n float _metile_v37_r18 = static_cast(_metile_v36_r18);\n float _metile_v37_r19 = static_cast(_metile_v36_r19);\n float _metile_v37_r20 = static_cast(_metile_v36_r20);\n float _metile_v37_r21 = static_cast(_metile_v36_r21);\n float _metile_v37_r22 = static_cast(_metile_v36_r22);\n float _metile_v37_r23 = static_cast(_metile_v36_r23);\n float _metile_v37_r24 = static_cast(_metile_v36_r24);\n float _metile_v37_r25 = static_cast(_metile_v36_r25);\n float _metile_v37_r26 = static_cast(_metile_v36_r26);\n float _metile_v37_r27 = static_cast(_metile_v36_r27);\n float _metile_v37_r28 = static_cast(_metile_v36_r28);\n float _metile_v37_r29 = static_cast(_metile_v36_r29);\n float _metile_v37_r30 = static_cast(_metile_v36_r30);\n float _metile_v37_r31 = static_cast(_metile_v36_r31);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v38_r16 = _metile_v21_r16 * v29;\n float _metile_v38_r17 = _metile_v21_r17 * v29;\n float _metile_v38_r18 = _metile_v21_r18 * v29;\n float _metile_v38_r19 = _metile_v21_r19 * v29;\n float _metile_v38_r20 = _metile_v21_r20 * v29;\n float _metile_v38_r21 = _metile_v21_r21 * v29;\n float _metile_v38_r22 = _metile_v21_r22 * v29;\n float _metile_v38_r23 = _metile_v21_r23 * v29;\n float _metile_v38_r24 = _metile_v21_r24 * v29;\n float _metile_v38_r25 = _metile_v21_r25 * v29;\n float _metile_v38_r26 = _metile_v21_r26 * v29;\n float _metile_v38_r27 = _metile_v21_r27 * v29;\n float _metile_v38_r28 = _metile_v21_r28 * v29;\n float _metile_v38_r29 = _metile_v21_r29 * v29;\n float _metile_v38_r30 = _metile_v21_r30 * v29;\n float _metile_v38_r31 = _metile_v21_r31 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n float _metile_v39_r16 = _metile_v38_r16 * _metile_v37_r16;\n float _metile_v39_r17 = _metile_v38_r17 * _metile_v37_r17;\n float _metile_v39_r18 = _metile_v38_r18 * _metile_v37_r18;\n float _metile_v39_r19 = _metile_v38_r19 * _metile_v37_r19;\n float _metile_v39_r20 = _metile_v38_r20 * _metile_v37_r20;\n float _metile_v39_r21 = _metile_v38_r21 * _metile_v37_r21;\n float _metile_v39_r22 = _metile_v38_r22 * _metile_v37_r22;\n float _metile_v39_r23 = _metile_v38_r23 * _metile_v37_r23;\n float _metile_v39_r24 = _metile_v38_r24 * _metile_v37_r24;\n float _metile_v39_r25 = _metile_v38_r25 * _metile_v37_r25;\n float _metile_v39_r26 = _metile_v38_r26 * _metile_v37_r26;\n float _metile_v39_r27 = _metile_v38_r27 * _metile_v37_r27;\n float _metile_v39_r28 = _metile_v38_r28 * _metile_v37_r28;\n float _metile_v39_r29 = _metile_v38_r29 * _metile_v37_r29;\n float _metile_v39_r30 = _metile_v38_r30 * _metile_v37_r30;\n float _metile_v39_r31 = _metile_v38_r31 * _metile_v37_r31;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v41_r16 = _metile_register_index________________ >= 0;\n bool _metile_v41_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v41_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v41_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v41_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v41_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v41_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v41_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v41_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v41_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v41_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v41_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v41_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v41_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v41_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v41_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v42_r8 = _metile_register_index________ < 1024;\n bool _metile_v42_r9 = _metile_register_index_________ < 1024;\n bool _metile_v42_r10 = _metile_register_index__________ < 1024;\n bool _metile_v42_r11 = _metile_register_index___________ < 1024;\n bool _metile_v42_r12 = _metile_register_index____________ < 1024;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v42_r14 = _metile_register_index______________ < 1024;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v42_r16 = _metile_register_index________________ < 1024;\n bool _metile_v42_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v42_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v42_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v42_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v42_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v42_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v42_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v42_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v42_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v42_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v42_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v42_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v42_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v42_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v42_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n bool _metile_v43_r16 = _metile_v41_r16 & _metile_v42_r16;\n bool _metile_v43_r17 = _metile_v41_r17 & _metile_v42_r17;\n bool _metile_v43_r18 = _metile_v41_r18 & _metile_v42_r18;\n bool _metile_v43_r19 = _metile_v41_r19 & _metile_v42_r19;\n bool _metile_v43_r20 = _metile_v41_r20 & _metile_v42_r20;\n bool _metile_v43_r21 = _metile_v41_r21 & _metile_v42_r21;\n bool _metile_v43_r22 = _metile_v41_r22 & _metile_v42_r22;\n bool _metile_v43_r23 = _metile_v41_r23 & _metile_v42_r23;\n bool _metile_v43_r24 = _metile_v41_r24 & _metile_v42_r24;\n bool _metile_v43_r25 = _metile_v41_r25 & _metile_v42_r25;\n bool _metile_v43_r26 = _metile_v41_r26 & _metile_v42_r26;\n bool _metile_v43_r27 = _metile_v41_r27 & _metile_v42_r27;\n bool _metile_v43_r28 = _metile_v41_r28 & _metile_v42_r28;\n bool _metile_v43_r29 = _metile_v41_r29 & _metile_v42_r29;\n bool _metile_v43_r30 = _metile_v41_r30 & _metile_v42_r30;\n bool _metile_v43_r31 = _metile_v41_r31 & _metile_v42_r31;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n int _off__metile_v44_r16 = v9 + _metile_register_index________________;\n int _off__metile_v44_r17 = v9 + _metile_register_index_________________;\n int _off__metile_v44_r18 = v9 + _metile_register_index__________________;\n int _off__metile_v44_r19 = v9 + _metile_register_index___________________;\n int _off__metile_v44_r20 = v9 + _metile_register_index____________________;\n int _off__metile_v44_r21 = v9 + _metile_register_index_____________________;\n int _off__metile_v44_r22 = v9 + _metile_register_index______________________;\n int _off__metile_v44_r23 = v9 + _metile_register_index_______________________;\n int _off__metile_v44_r24 = v9 + _metile_register_index________________________;\n int _off__metile_v44_r25 = v9 + _metile_register_index_________________________;\n int _off__metile_v44_r26 = v9 + _metile_register_index__________________________;\n int _off__metile_v44_r27 = v9 + _metile_register_index___________________________;\n int _off__metile_v44_r28 = v9 + _metile_register_index____________________________;\n int _off__metile_v44_r29 = v9 + _metile_register_index_____________________________;\n int _off__metile_v44_r30 = v9 + _metile_register_index______________________________;\n int _off__metile_v44_r31 = v9 + _metile_register_index_______________________________;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = _metile_v39_r8; }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = _metile_v39_r9; }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = _metile_v39_r10; }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = _metile_v39_r11; }\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = _metile_v39_r12; }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = _metile_v39_r13; }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = _metile_v39_r14; }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = _metile_v39_r15; }\n if (_metile_v43_r16) { Out[_off__metile_v44_r16] = _metile_v39_r16; }\n if (_metile_v43_r17) { Out[_off__metile_v44_r17] = _metile_v39_r17; }\n if (_metile_v43_r18) { Out[_off__metile_v44_r18] = _metile_v39_r18; }\n if (_metile_v43_r19) { Out[_off__metile_v44_r19] = _metile_v39_r19; }\n if (_metile_v43_r20) { Out[_off__metile_v44_r20] = _metile_v39_r20; }\n if (_metile_v43_r21) { Out[_off__metile_v44_r21] = _metile_v39_r21; }\n if (_metile_v43_r22) { Out[_off__metile_v44_r22] = _metile_v39_r22; }\n if (_metile_v43_r23) { Out[_off__metile_v44_r23] = _metile_v39_r23; }\n if (_metile_v43_r24) { Out[_off__metile_v44_r24] = _metile_v39_r24; }\n if (_metile_v43_r25) { Out[_off__metile_v44_r25] = _metile_v39_r25; }\n if (_metile_v43_r26) { Out[_off__metile_v44_r26] = _metile_v39_r26; }\n if (_metile_v43_r27) { Out[_off__metile_v44_r27] = _metile_v39_r27; }\n if (_metile_v43_r28) { Out[_off__metile_v44_r28] = _metile_v39_r28; }\n if (_metile_v43_r29) { Out[_off__metile_v44_r29] = _metile_v39_r29; }\n if (_metile_v43_r30) { Out[_off__metile_v44_r30] = _metile_v39_r30; }\n if (_metile_v43_r31) { Out[_off__metile_v44_r31] = _metile_v39_r31; }\n}", "source_sha256": "a52a8c0239924732be4213a7549695361b8367e8f1fc6ffa94dbf8f3a8880747", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 32, 1, 1 ], "is_gemm": false, "prefer_ordered": false, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 32, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 32 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 32, "threads": 32, "scratch": null, "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 505, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.875, "control": 203.167, "speedup": 1.0164702939337085 }, "gpu_us": { "candidate": 2.3333122953772545, "control": 1.9583385437726974, "speedup": 0.8392955146435165 } } }, { "frozen_register4": { "pairs": 352, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 287.60450000000003, "control": 289.0625, "speedup": 1.0050694617087006 }, "gpu_us": { "candidate": 9.083305485546589, "control": 7.6249707490205765, "speedup": 0.8394488945850689 } } }, { "frozen_register4": { "pairs": 435, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 289.04200000000003, "control": 291.541, "speedup": 1.0086458023401441 }, "gpu_us": { "candidate": 9.124982170760632, "control": 7.62502895668149, "speedup": 0.8356212444024852 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0100506473515583, "round_speedups": [ 1.0164702939337085, 1.0050694617087006, 1.0086458023401441 ], "candidate": 255.1751443452611, "control": 257.7398197339584 }, "gpu_us": { "speedup": 0.8381200151101741, "round_speedups": [ 0.8392955146435165, 0.8394488945850689, 0.8356212444024852 ], "candidate": 5.7829522302152, "control": 4.8468080105693785 } } } }, { "name": "float16_32x1024", "dtype": "float16", "batches": 32, "width": 1024, "status": "measured", "variant": { "name": "register32_blocked4", "elements_per_thread": 32, "layout": "blocked4" }, "input_sha256": "6e821d0e3f7ad3cc0206f556836dd56fc15c5cc3181cc0547765f5bce1880ac4", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 31;\n int _metile_register_index = int((((_metile_bounded_thread >> 5) & 1u) << 0) | (((_metile_bounded_thread >> 6) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 7) & 1u) << 7) | (((_metile_bounded_thread >> 8) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 32;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 5) & 1u) << 0) | (((_metile_register_packed_ >> 6) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 7) & 1u) << 7) | (((_metile_register_packed_ >> 8) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 64;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 5) & 1u) << 0) | (((_metile_register_packed__ >> 6) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 7) & 1u) << 7) | (((_metile_register_packed__ >> 8) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 96;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 5) & 1u) << 0) | (((_metile_register_packed___ >> 6) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 7) & 1u) << 7) | (((_metile_register_packed___ >> 8) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 128;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 5) & 1u) << 0) | (((_metile_register_packed____ >> 6) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 7) & 1u) << 7) | (((_metile_register_packed____ >> 8) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 160;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 5) & 1u) << 0) | (((_metile_register_packed_____ >> 6) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 7) & 1u) << 7) | (((_metile_register_packed_____ >> 8) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 192;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 5) & 1u) << 0) | (((_metile_register_packed______ >> 6) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 7) & 1u) << 7) | (((_metile_register_packed______ >> 8) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 224;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 5) & 1u) << 0) | (((_metile_register_packed_______ >> 6) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 7) & 1u) << 7) | (((_metile_register_packed_______ >> 8) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n int _metile_register_packed________ = _metile_bounded_thread + 256;\n int _metile_register_index________ = int((((_metile_register_packed________ >> 5) & 1u) << 0) | (((_metile_register_packed________ >> 6) & 1u) << 1) | (((_metile_register_packed________ >> 0) & 1u) << 2) | (((_metile_register_packed________ >> 1) & 1u) << 3) | (((_metile_register_packed________ >> 2) & 1u) << 4) | (((_metile_register_packed________ >> 3) & 1u) << 5) | (((_metile_register_packed________ >> 4) & 1u) << 6) | (((_metile_register_packed________ >> 7) & 1u) << 7) | (((_metile_register_packed________ >> 8) & 1u) << 8) | (((_metile_register_packed________ >> 9) & 1u) << 9));\n int _metile_register_packed_________ = _metile_bounded_thread + 288;\n int _metile_register_index_________ = int((((_metile_register_packed_________ >> 5) & 1u) << 0) | (((_metile_register_packed_________ >> 6) & 1u) << 1) | (((_metile_register_packed_________ >> 0) & 1u) << 2) | (((_metile_register_packed_________ >> 1) & 1u) << 3) | (((_metile_register_packed_________ >> 2) & 1u) << 4) | (((_metile_register_packed_________ >> 3) & 1u) << 5) | (((_metile_register_packed_________ >> 4) & 1u) << 6) | (((_metile_register_packed_________ >> 7) & 1u) << 7) | (((_metile_register_packed_________ >> 8) & 1u) << 8) | (((_metile_register_packed_________ >> 9) & 1u) << 9));\n int _metile_register_packed__________ = _metile_bounded_thread + 320;\n int _metile_register_index__________ = int((((_metile_register_packed__________ >> 5) & 1u) << 0) | (((_metile_register_packed__________ >> 6) & 1u) << 1) | (((_metile_register_packed__________ >> 0) & 1u) << 2) | (((_metile_register_packed__________ >> 1) & 1u) << 3) | (((_metile_register_packed__________ >> 2) & 1u) << 4) | (((_metile_register_packed__________ >> 3) & 1u) << 5) | (((_metile_register_packed__________ >> 4) & 1u) << 6) | (((_metile_register_packed__________ >> 7) & 1u) << 7) | (((_metile_register_packed__________ >> 8) & 1u) << 8) | (((_metile_register_packed__________ >> 9) & 1u) << 9));\n int _metile_register_packed___________ = _metile_bounded_thread + 352;\n int _metile_register_index___________ = int((((_metile_register_packed___________ >> 5) & 1u) << 0) | (((_metile_register_packed___________ >> 6) & 1u) << 1) | (((_metile_register_packed___________ >> 0) & 1u) << 2) | (((_metile_register_packed___________ >> 1) & 1u) << 3) | (((_metile_register_packed___________ >> 2) & 1u) << 4) | (((_metile_register_packed___________ >> 3) & 1u) << 5) | (((_metile_register_packed___________ >> 4) & 1u) << 6) | (((_metile_register_packed___________ >> 7) & 1u) << 7) | (((_metile_register_packed___________ >> 8) & 1u) << 8) | (((_metile_register_packed___________ >> 9) & 1u) << 9));\n int _metile_register_packed____________ = _metile_bounded_thread + 384;\n int _metile_register_index____________ = int((((_metile_register_packed____________ >> 5) & 1u) << 0) | (((_metile_register_packed____________ >> 6) & 1u) << 1) | (((_metile_register_packed____________ >> 0) & 1u) << 2) | (((_metile_register_packed____________ >> 1) & 1u) << 3) | (((_metile_register_packed____________ >> 2) & 1u) << 4) | (((_metile_register_packed____________ >> 3) & 1u) << 5) | (((_metile_register_packed____________ >> 4) & 1u) << 6) | (((_metile_register_packed____________ >> 7) & 1u) << 7) | (((_metile_register_packed____________ >> 8) & 1u) << 8) | (((_metile_register_packed____________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________ = _metile_bounded_thread + 416;\n int _metile_register_index_____________ = int((((_metile_register_packed_____________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________ >> 9) & 1u) << 9));\n int _metile_register_packed______________ = _metile_bounded_thread + 448;\n int _metile_register_index______________ = int((((_metile_register_packed______________ >> 5) & 1u) << 0) | (((_metile_register_packed______________ >> 6) & 1u) << 1) | (((_metile_register_packed______________ >> 0) & 1u) << 2) | (((_metile_register_packed______________ >> 1) & 1u) << 3) | (((_metile_register_packed______________ >> 2) & 1u) << 4) | (((_metile_register_packed______________ >> 3) & 1u) << 5) | (((_metile_register_packed______________ >> 4) & 1u) << 6) | (((_metile_register_packed______________ >> 7) & 1u) << 7) | (((_metile_register_packed______________ >> 8) & 1u) << 8) | (((_metile_register_packed______________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________ = _metile_bounded_thread + 480;\n int _metile_register_index_______________ = int((((_metile_register_packed_______________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________ >> 9) & 1u) << 9));\n int _metile_register_packed________________ = _metile_bounded_thread + 512;\n int _metile_register_index________________ = int((((_metile_register_packed________________ >> 5) & 1u) << 0) | (((_metile_register_packed________________ >> 6) & 1u) << 1) | (((_metile_register_packed________________ >> 0) & 1u) << 2) | (((_metile_register_packed________________ >> 1) & 1u) << 3) | (((_metile_register_packed________________ >> 2) & 1u) << 4) | (((_metile_register_packed________________ >> 3) & 1u) << 5) | (((_metile_register_packed________________ >> 4) & 1u) << 6) | (((_metile_register_packed________________ >> 7) & 1u) << 7) | (((_metile_register_packed________________ >> 8) & 1u) << 8) | (((_metile_register_packed________________ >> 9) & 1u) << 9));\n int _metile_register_packed_________________ = _metile_bounded_thread + 544;\n int _metile_register_index_________________ = int((((_metile_register_packed_________________ >> 5) & 1u) << 0) | (((_metile_register_packed_________________ >> 6) & 1u) << 1) | (((_metile_register_packed_________________ >> 0) & 1u) << 2) | (((_metile_register_packed_________________ >> 1) & 1u) << 3) | (((_metile_register_packed_________________ >> 2) & 1u) << 4) | (((_metile_register_packed_________________ >> 3) & 1u) << 5) | (((_metile_register_packed_________________ >> 4) & 1u) << 6) | (((_metile_register_packed_________________ >> 7) & 1u) << 7) | (((_metile_register_packed_________________ >> 8) & 1u) << 8) | (((_metile_register_packed_________________ >> 9) & 1u) << 9));\n int _metile_register_packed__________________ = _metile_bounded_thread + 576;\n int _metile_register_index__________________ = int((((_metile_register_packed__________________ >> 5) & 1u) << 0) | (((_metile_register_packed__________________ >> 6) & 1u) << 1) | (((_metile_register_packed__________________ >> 0) & 1u) << 2) | (((_metile_register_packed__________________ >> 1) & 1u) << 3) | (((_metile_register_packed__________________ >> 2) & 1u) << 4) | (((_metile_register_packed__________________ >> 3) & 1u) << 5) | (((_metile_register_packed__________________ >> 4) & 1u) << 6) | (((_metile_register_packed__________________ >> 7) & 1u) << 7) | (((_metile_register_packed__________________ >> 8) & 1u) << 8) | (((_metile_register_packed__________________ >> 9) & 1u) << 9));\n int _metile_register_packed___________________ = _metile_bounded_thread + 608;\n int _metile_register_index___________________ = int((((_metile_register_packed___________________ >> 5) & 1u) << 0) | (((_metile_register_packed___________________ >> 6) & 1u) << 1) | (((_metile_register_packed___________________ >> 0) & 1u) << 2) | (((_metile_register_packed___________________ >> 1) & 1u) << 3) | (((_metile_register_packed___________________ >> 2) & 1u) << 4) | (((_metile_register_packed___________________ >> 3) & 1u) << 5) | (((_metile_register_packed___________________ >> 4) & 1u) << 6) | (((_metile_register_packed___________________ >> 7) & 1u) << 7) | (((_metile_register_packed___________________ >> 8) & 1u) << 8) | (((_metile_register_packed___________________ >> 9) & 1u) << 9));\n int _metile_register_packed____________________ = _metile_bounded_thread + 640;\n int _metile_register_index____________________ = int((((_metile_register_packed____________________ >> 5) & 1u) << 0) | (((_metile_register_packed____________________ >> 6) & 1u) << 1) | (((_metile_register_packed____________________ >> 0) & 1u) << 2) | (((_metile_register_packed____________________ >> 1) & 1u) << 3) | (((_metile_register_packed____________________ >> 2) & 1u) << 4) | (((_metile_register_packed____________________ >> 3) & 1u) << 5) | (((_metile_register_packed____________________ >> 4) & 1u) << 6) | (((_metile_register_packed____________________ >> 7) & 1u) << 7) | (((_metile_register_packed____________________ >> 8) & 1u) << 8) | (((_metile_register_packed____________________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________________ = _metile_bounded_thread + 672;\n int _metile_register_index_____________________ = int((((_metile_register_packed_____________________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________________ >> 9) & 1u) << 9));\n int _metile_register_packed______________________ = _metile_bounded_thread + 704;\n int _metile_register_index______________________ = int((((_metile_register_packed______________________ >> 5) & 1u) << 0) | (((_metile_register_packed______________________ >> 6) & 1u) << 1) | (((_metile_register_packed______________________ >> 0) & 1u) << 2) | (((_metile_register_packed______________________ >> 1) & 1u) << 3) | (((_metile_register_packed______________________ >> 2) & 1u) << 4) | (((_metile_register_packed______________________ >> 3) & 1u) << 5) | (((_metile_register_packed______________________ >> 4) & 1u) << 6) | (((_metile_register_packed______________________ >> 7) & 1u) << 7) | (((_metile_register_packed______________________ >> 8) & 1u) << 8) | (((_metile_register_packed______________________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________________ = _metile_bounded_thread + 736;\n int _metile_register_index_______________________ = int((((_metile_register_packed_______________________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________________ >> 9) & 1u) << 9));\n int _metile_register_packed________________________ = _metile_bounded_thread + 768;\n int _metile_register_index________________________ = int((((_metile_register_packed________________________ >> 5) & 1u) << 0) | (((_metile_register_packed________________________ >> 6) & 1u) << 1) | (((_metile_register_packed________________________ >> 0) & 1u) << 2) | (((_metile_register_packed________________________ >> 1) & 1u) << 3) | (((_metile_register_packed________________________ >> 2) & 1u) << 4) | (((_metile_register_packed________________________ >> 3) & 1u) << 5) | (((_metile_register_packed________________________ >> 4) & 1u) << 6) | (((_metile_register_packed________________________ >> 7) & 1u) << 7) | (((_metile_register_packed________________________ >> 8) & 1u) << 8) | (((_metile_register_packed________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_________________________ = _metile_bounded_thread + 800;\n int _metile_register_index_________________________ = int((((_metile_register_packed_________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_________________________ >> 9) & 1u) << 9));\n int _metile_register_packed__________________________ = _metile_bounded_thread + 832;\n int _metile_register_index__________________________ = int((((_metile_register_packed__________________________ >> 5) & 1u) << 0) | (((_metile_register_packed__________________________ >> 6) & 1u) << 1) | (((_metile_register_packed__________________________ >> 0) & 1u) << 2) | (((_metile_register_packed__________________________ >> 1) & 1u) << 3) | (((_metile_register_packed__________________________ >> 2) & 1u) << 4) | (((_metile_register_packed__________________________ >> 3) & 1u) << 5) | (((_metile_register_packed__________________________ >> 4) & 1u) << 6) | (((_metile_register_packed__________________________ >> 7) & 1u) << 7) | (((_metile_register_packed__________________________ >> 8) & 1u) << 8) | (((_metile_register_packed__________________________ >> 9) & 1u) << 9));\n int _metile_register_packed___________________________ = _metile_bounded_thread + 864;\n int _metile_register_index___________________________ = int((((_metile_register_packed___________________________ >> 5) & 1u) << 0) | (((_metile_register_packed___________________________ >> 6) & 1u) << 1) | (((_metile_register_packed___________________________ >> 0) & 1u) << 2) | (((_metile_register_packed___________________________ >> 1) & 1u) << 3) | (((_metile_register_packed___________________________ >> 2) & 1u) << 4) | (((_metile_register_packed___________________________ >> 3) & 1u) << 5) | (((_metile_register_packed___________________________ >> 4) & 1u) << 6) | (((_metile_register_packed___________________________ >> 7) & 1u) << 7) | (((_metile_register_packed___________________________ >> 8) & 1u) << 8) | (((_metile_register_packed___________________________ >> 9) & 1u) << 9));\n int _metile_register_packed____________________________ = _metile_bounded_thread + 896;\n int _metile_register_index____________________________ = int((((_metile_register_packed____________________________ >> 5) & 1u) << 0) | (((_metile_register_packed____________________________ >> 6) & 1u) << 1) | (((_metile_register_packed____________________________ >> 0) & 1u) << 2) | (((_metile_register_packed____________________________ >> 1) & 1u) << 3) | (((_metile_register_packed____________________________ >> 2) & 1u) << 4) | (((_metile_register_packed____________________________ >> 3) & 1u) << 5) | (((_metile_register_packed____________________________ >> 4) & 1u) << 6) | (((_metile_register_packed____________________________ >> 7) & 1u) << 7) | (((_metile_register_packed____________________________ >> 8) & 1u) << 8) | (((_metile_register_packed____________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________________________ = _metile_bounded_thread + 928;\n int _metile_register_index_____________________________ = int((((_metile_register_packed_____________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________________________ >> 9) & 1u) << 9));\n int _metile_register_packed______________________________ = _metile_bounded_thread + 960;\n int _metile_register_index______________________________ = int((((_metile_register_packed______________________________ >> 5) & 1u) << 0) | (((_metile_register_packed______________________________ >> 6) & 1u) << 1) | (((_metile_register_packed______________________________ >> 0) & 1u) << 2) | (((_metile_register_packed______________________________ >> 1) & 1u) << 3) | (((_metile_register_packed______________________________ >> 2) & 1u) << 4) | (((_metile_register_packed______________________________ >> 3) & 1u) << 5) | (((_metile_register_packed______________________________ >> 4) & 1u) << 6) | (((_metile_register_packed______________________________ >> 7) & 1u) << 7) | (((_metile_register_packed______________________________ >> 8) & 1u) << 8) | (((_metile_register_packed______________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________________________ = _metile_bounded_thread + 992;\n int _metile_register_index_______________________________ = int((((_metile_register_packed_______________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________________________ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v16_r16 = _metile_register_index________________ >= 0;\n bool _metile_v16_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v16_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v16_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v16_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v16_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v16_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v16_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v16_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v16_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v16_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v16_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v16_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v16_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v16_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v16_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v17_r8 = _metile_register_index________ < 1024;\n bool _metile_v17_r9 = _metile_register_index_________ < 1024;\n bool _metile_v17_r10 = _metile_register_index__________ < 1024;\n bool _metile_v17_r11 = _metile_register_index___________ < 1024;\n bool _metile_v17_r12 = _metile_register_index____________ < 1024;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v17_r14 = _metile_register_index______________ < 1024;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v17_r16 = _metile_register_index________________ < 1024;\n bool _metile_v17_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v17_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v17_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v17_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v17_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v17_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v17_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v17_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v17_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v17_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v17_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v17_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v17_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v17_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v17_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n bool _metile_v18_r16 = _metile_v16_r16 & _metile_v17_r16;\n bool _metile_v18_r17 = _metile_v16_r17 & _metile_v17_r17;\n bool _metile_v18_r18 = _metile_v16_r18 & _metile_v17_r18;\n bool _metile_v18_r19 = _metile_v16_r19 & _metile_v17_r19;\n bool _metile_v18_r20 = _metile_v16_r20 & _metile_v17_r20;\n bool _metile_v18_r21 = _metile_v16_r21 & _metile_v17_r21;\n bool _metile_v18_r22 = _metile_v16_r22 & _metile_v17_r22;\n bool _metile_v18_r23 = _metile_v16_r23 & _metile_v17_r23;\n bool _metile_v18_r24 = _metile_v16_r24 & _metile_v17_r24;\n bool _metile_v18_r25 = _metile_v16_r25 & _metile_v17_r25;\n bool _metile_v18_r26 = _metile_v16_r26 & _metile_v17_r26;\n bool _metile_v18_r27 = _metile_v16_r27 & _metile_v17_r27;\n bool _metile_v18_r28 = _metile_v16_r28 & _metile_v17_r28;\n bool _metile_v18_r29 = _metile_v16_r29 & _metile_v17_r29;\n bool _metile_v18_r30 = _metile_v16_r30 & _metile_v17_r30;\n bool _metile_v18_r31 = _metile_v16_r31 & _metile_v17_r31;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n int _off__metile_v19_r16 = v2 + _metile_register_index________________;\n int _off__metile_v19_r17 = v2 + _metile_register_index_________________;\n int _off__metile_v19_r18 = v2 + _metile_register_index__________________;\n int _off__metile_v19_r19 = v2 + _metile_register_index___________________;\n int _off__metile_v19_r20 = v2 + _metile_register_index____________________;\n int _off__metile_v19_r21 = v2 + _metile_register_index_____________________;\n int _off__metile_v19_r22 = v2 + _metile_register_index______________________;\n int _off__metile_v19_r23 = v2 + _metile_register_index_______________________;\n int _off__metile_v19_r24 = v2 + _metile_register_index________________________;\n int _off__metile_v19_r25 = v2 + _metile_register_index_________________________;\n int _off__metile_v19_r26 = v2 + _metile_register_index__________________________;\n int _off__metile_v19_r27 = v2 + _metile_register_index___________________________;\n int _off__metile_v19_r28 = v2 + _metile_register_index____________________________;\n int _off__metile_v19_r29 = v2 + _metile_register_index_____________________________;\n int _off__metile_v19_r30 = v2 + _metile_register_index______________________________;\n int _off__metile_v19_r31 = v2 + _metile_register_index_______________________________;\n half4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = half4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n half _metile_v20_r0 = _metile_vector_load[0];\n half _metile_v20_r1 = _metile_vector_load[1];\n half _metile_v20_r2 = _metile_vector_load[2];\n half _metile_v20_r3 = _metile_vector_load[3];\n half4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = half4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n half _metile_v20_r4 = _metile_vector_load_[0];\n half _metile_v20_r5 = _metile_vector_load_[1];\n half _metile_v20_r6 = _metile_vector_load_[2];\n half _metile_v20_r7 = _metile_vector_load_[3];\n half4 _metile_vector_load__;\n if ((_metile_v18_r8) && (_metile_v18_r9) && (_metile_v18_r10) && (_metile_v18_r11) && (long(_off__metile_v19_r9) == long(_off__metile_v19_r8) + 1) && (long(_off__metile_v19_r10) == long(_off__metile_v19_r8) + 2) && (long(_off__metile_v19_r11) == long(_off__metile_v19_r8) + 3)) {\n _metile_vector_load__ = half4(*reinterpret_cast(X + _off__metile_v19_r8));\n } else {\n _metile_vector_load__[0] = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n _metile_vector_load__[1] = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n _metile_vector_load__[2] = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n _metile_vector_load__[3] = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n }\n half _metile_v20_r8 = _metile_vector_load__[0];\n half _metile_v20_r9 = _metile_vector_load__[1];\n half _metile_v20_r10 = _metile_vector_load__[2];\n half _metile_v20_r11 = _metile_vector_load__[3];\n half4 _metile_vector_load___;\n if ((_metile_v18_r12) && (_metile_v18_r13) && (_metile_v18_r14) && (_metile_v18_r15) && (long(_off__metile_v19_r13) == long(_off__metile_v19_r12) + 1) && (long(_off__metile_v19_r14) == long(_off__metile_v19_r12) + 2) && (long(_off__metile_v19_r15) == long(_off__metile_v19_r12) + 3)) {\n _metile_vector_load___ = half4(*reinterpret_cast(X + _off__metile_v19_r12));\n } else {\n _metile_vector_load___[0] = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n _metile_vector_load___[1] = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n _metile_vector_load___[2] = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n _metile_vector_load___[3] = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n }\n half _metile_v20_r12 = _metile_vector_load___[0];\n half _metile_v20_r13 = _metile_vector_load___[1];\n half _metile_v20_r14 = _metile_vector_load___[2];\n half _metile_v20_r15 = _metile_vector_load___[3];\n half4 _metile_vector_load____;\n if ((_metile_v18_r16) && (_metile_v18_r17) && (_metile_v18_r18) && (_metile_v18_r19) && (long(_off__metile_v19_r17) == long(_off__metile_v19_r16) + 1) && (long(_off__metile_v19_r18) == long(_off__metile_v19_r16) + 2) && (long(_off__metile_v19_r19) == long(_off__metile_v19_r16) + 3)) {\n _metile_vector_load____ = half4(*reinterpret_cast(X + _off__metile_v19_r16));\n } else {\n _metile_vector_load____[0] = _metile_v18_r16 ? X[_off__metile_v19_r16] : static_cast(0);\n _metile_vector_load____[1] = _metile_v18_r17 ? X[_off__metile_v19_r17] : static_cast(0);\n _metile_vector_load____[2] = _metile_v18_r18 ? X[_off__metile_v19_r18] : static_cast(0);\n _metile_vector_load____[3] = _metile_v18_r19 ? X[_off__metile_v19_r19] : static_cast(0);\n }\n half _metile_v20_r16 = _metile_vector_load____[0];\n half _metile_v20_r17 = _metile_vector_load____[1];\n half _metile_v20_r18 = _metile_vector_load____[2];\n half _metile_v20_r19 = _metile_vector_load____[3];\n half4 _metile_vector_load_____;\n if ((_metile_v18_r20) && (_metile_v18_r21) && (_metile_v18_r22) && (_metile_v18_r23) && (long(_off__metile_v19_r21) == long(_off__metile_v19_r20) + 1) && (long(_off__metile_v19_r22) == long(_off__metile_v19_r20) + 2) && (long(_off__metile_v19_r23) == long(_off__metile_v19_r20) + 3)) {\n _metile_vector_load_____ = half4(*reinterpret_cast(X + _off__metile_v19_r20));\n } else {\n _metile_vector_load_____[0] = _metile_v18_r20 ? X[_off__metile_v19_r20] : static_cast(0);\n _metile_vector_load_____[1] = _metile_v18_r21 ? X[_off__metile_v19_r21] : static_cast(0);\n _metile_vector_load_____[2] = _metile_v18_r22 ? X[_off__metile_v19_r22] : static_cast(0);\n _metile_vector_load_____[3] = _metile_v18_r23 ? X[_off__metile_v19_r23] : static_cast(0);\n }\n half _metile_v20_r20 = _metile_vector_load_____[0];\n half _metile_v20_r21 = _metile_vector_load_____[1];\n half _metile_v20_r22 = _metile_vector_load_____[2];\n half _metile_v20_r23 = _metile_vector_load_____[3];\n half4 _metile_vector_load______;\n if ((_metile_v18_r24) && (_metile_v18_r25) && (_metile_v18_r26) && (_metile_v18_r27) && (long(_off__metile_v19_r25) == long(_off__metile_v19_r24) + 1) && (long(_off__metile_v19_r26) == long(_off__metile_v19_r24) + 2) && (long(_off__metile_v19_r27) == long(_off__metile_v19_r24) + 3)) {\n _metile_vector_load______ = half4(*reinterpret_cast(X + _off__metile_v19_r24));\n } else {\n _metile_vector_load______[0] = _metile_v18_r24 ? X[_off__metile_v19_r24] : static_cast(0);\n _metile_vector_load______[1] = _metile_v18_r25 ? X[_off__metile_v19_r25] : static_cast(0);\n _metile_vector_load______[2] = _metile_v18_r26 ? X[_off__metile_v19_r26] : static_cast(0);\n _metile_vector_load______[3] = _metile_v18_r27 ? X[_off__metile_v19_r27] : static_cast(0);\n }\n half _metile_v20_r24 = _metile_vector_load______[0];\n half _metile_v20_r25 = _metile_vector_load______[1];\n half _metile_v20_r26 = _metile_vector_load______[2];\n half _metile_v20_r27 = _metile_vector_load______[3];\n half4 _metile_vector_load_______;\n if ((_metile_v18_r28) && (_metile_v18_r29) && (_metile_v18_r30) && (_metile_v18_r31) && (long(_off__metile_v19_r29) == long(_off__metile_v19_r28) + 1) && (long(_off__metile_v19_r30) == long(_off__metile_v19_r28) + 2) && (long(_off__metile_v19_r31) == long(_off__metile_v19_r28) + 3)) {\n _metile_vector_load_______ = half4(*reinterpret_cast(X + _off__metile_v19_r28));\n } else {\n _metile_vector_load_______[0] = _metile_v18_r28 ? X[_off__metile_v19_r28] : static_cast(0);\n _metile_vector_load_______[1] = _metile_v18_r29 ? X[_off__metile_v19_r29] : static_cast(0);\n _metile_vector_load_______[2] = _metile_v18_r30 ? X[_off__metile_v19_r30] : static_cast(0);\n _metile_vector_load_______[3] = _metile_v18_r31 ? X[_off__metile_v19_r31] : static_cast(0);\n }\n half _metile_v20_r28 = _metile_vector_load_______[0];\n half _metile_v20_r29 = _metile_vector_load_______[1];\n half _metile_v20_r30 = _metile_vector_load_______[2];\n half _metile_v20_r31 = _metile_vector_load_______[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v21_r16 = static_cast(_metile_v20_r16);\n float _metile_v21_r17 = static_cast(_metile_v20_r17);\n float _metile_v21_r18 = static_cast(_metile_v20_r18);\n float _metile_v21_r19 = static_cast(_metile_v20_r19);\n float _metile_v21_r20 = static_cast(_metile_v20_r20);\n float _metile_v21_r21 = static_cast(_metile_v20_r21);\n float _metile_v21_r22 = static_cast(_metile_v20_r22);\n float _metile_v21_r23 = static_cast(_metile_v20_r23);\n float _metile_v21_r24 = static_cast(_metile_v20_r24);\n float _metile_v21_r25 = static_cast(_metile_v20_r25);\n float _metile_v21_r26 = static_cast(_metile_v20_r26);\n float _metile_v21_r27 = static_cast(_metile_v20_r27);\n float _metile_v21_r28 = static_cast(_metile_v20_r28);\n float _metile_v21_r29 = static_cast(_metile_v20_r29);\n float _metile_v21_r30 = static_cast(_metile_v20_r30);\n float _metile_v21_r31 = static_cast(_metile_v20_r31);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_v22_r16 = _metile_v21_r16 * _metile_v21_r16;\n float _metile_v22_r17 = _metile_v21_r17 * _metile_v21_r17;\n float _metile_v22_r18 = _metile_v21_r18 * _metile_v21_r18;\n float _metile_v22_r19 = _metile_v21_r19 * _metile_v21_r19;\n float _metile_v22_r20 = _metile_v21_r20 * _metile_v21_r20;\n float _metile_v22_r21 = _metile_v21_r21 * _metile_v21_r21;\n float _metile_v22_r22 = _metile_v21_r22 * _metile_v21_r22;\n float _metile_v22_r23 = _metile_v21_r23 * _metile_v21_r23;\n float _metile_v22_r24 = _metile_v21_r24 * _metile_v21_r24;\n float _metile_v22_r25 = _metile_v21_r25 * _metile_v21_r25;\n float _metile_v22_r26 = _metile_v21_r26 * _metile_v21_r26;\n float _metile_v22_r27 = _metile_v21_r27 * _metile_v21_r27;\n float _metile_v22_r28 = _metile_v21_r28 * _metile_v21_r28;\n float _metile_v22_r29 = _metile_v21_r29 * _metile_v21_r29;\n float _metile_v22_r30 = _metile_v21_r30 * _metile_v21_r30;\n float _metile_v22_r31 = _metile_v21_r31 * _metile_v21_r31;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_v22_r16 + _metile_v22_r17;\n float _metile_register_sum_________ = _metile_v22_r18 + _metile_v22_r19;\n float _metile_register_sum__________ = _metile_v22_r20 + _metile_v22_r21;\n float _metile_register_sum___________ = _metile_v22_r22 + _metile_v22_r23;\n float _metile_register_sum____________ = _metile_v22_r24 + _metile_v22_r25;\n float _metile_register_sum_____________ = _metile_v22_r26 + _metile_v22_r27;\n float _metile_register_sum______________ = _metile_v22_r28 + _metile_v22_r29;\n float _metile_register_sum_______________ = _metile_v22_r30 + _metile_v22_r31;\n float _metile_register_sum________________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________________ = _metile_register_sum____________ + _metile_register_sum_____________;\n float _metile_register_sum_______________________ = _metile_register_sum______________ + _metile_register_sum_______________;\n float _metile_register_sum________________________ = _metile_register_sum________________ + _metile_register_sum_________________;\n float _metile_register_sum_________________________ = _metile_register_sum__________________ + _metile_register_sum___________________;\n float _metile_register_sum__________________________ = _metile_register_sum____________________ + _metile_register_sum_____________________;\n float _metile_register_sum___________________________ = _metile_register_sum______________________ + _metile_register_sum_______________________;\n float _metile_register_sum____________________________ = _metile_register_sum________________________ + _metile_register_sum_________________________;\n float _metile_register_sum_____________________________ = _metile_register_sum__________________________ + _metile_register_sum___________________________;\n float _metile_register_sum______________________________ = _metile_register_sum____________________________ + _metile_register_sum_____________________________;\n float v23 = simd_sum(_metile_register_sum______________________________);\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v32_r16 = _metile_register_index________________ >= 0;\n bool _metile_v32_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v32_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v32_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v32_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v32_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v32_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v32_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v32_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v32_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v32_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v32_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v32_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v32_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v32_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v32_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v33_r8 = _metile_register_index________ < 1024;\n bool _metile_v33_r9 = _metile_register_index_________ < 1024;\n bool _metile_v33_r10 = _metile_register_index__________ < 1024;\n bool _metile_v33_r11 = _metile_register_index___________ < 1024;\n bool _metile_v33_r12 = _metile_register_index____________ < 1024;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v33_r14 = _metile_register_index______________ < 1024;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v33_r16 = _metile_register_index________________ < 1024;\n bool _metile_v33_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v33_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v33_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v33_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v33_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v33_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v33_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v33_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v33_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v33_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v33_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v33_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v33_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v33_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v33_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n bool _metile_v34_r16 = _metile_v32_r16 & _metile_v33_r16;\n bool _metile_v34_r17 = _metile_v32_r17 & _metile_v33_r17;\n bool _metile_v34_r18 = _metile_v32_r18 & _metile_v33_r18;\n bool _metile_v34_r19 = _metile_v32_r19 & _metile_v33_r19;\n bool _metile_v34_r20 = _metile_v32_r20 & _metile_v33_r20;\n bool _metile_v34_r21 = _metile_v32_r21 & _metile_v33_r21;\n bool _metile_v34_r22 = _metile_v32_r22 & _metile_v33_r22;\n bool _metile_v34_r23 = _metile_v32_r23 & _metile_v33_r23;\n bool _metile_v34_r24 = _metile_v32_r24 & _metile_v33_r24;\n bool _metile_v34_r25 = _metile_v32_r25 & _metile_v33_r25;\n bool _metile_v34_r26 = _metile_v32_r26 & _metile_v33_r26;\n bool _metile_v34_r27 = _metile_v32_r27 & _metile_v33_r27;\n bool _metile_v34_r28 = _metile_v32_r28 & _metile_v33_r28;\n bool _metile_v34_r29 = _metile_v32_r29 & _metile_v33_r29;\n bool _metile_v34_r30 = _metile_v32_r30 & _metile_v33_r30;\n bool _metile_v34_r31 = _metile_v32_r31 & _metile_v33_r31;\n half4 _metile_vector_load________;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load________ = half4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load________[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load________[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load________[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load________[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n half _metile_v36_r0 = _metile_vector_load________[0];\n half _metile_v36_r1 = _metile_vector_load________[1];\n half _metile_v36_r2 = _metile_vector_load________[2];\n half _metile_v36_r3 = _metile_vector_load________[3];\n half4 _metile_vector_load_________;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load_________ = half4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load_________[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load_________[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load_________[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load_________[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n half _metile_v36_r4 = _metile_vector_load_________[0];\n half _metile_v36_r5 = _metile_vector_load_________[1];\n half _metile_v36_r6 = _metile_vector_load_________[2];\n half _metile_v36_r7 = _metile_vector_load_________[3];\n half4 _metile_vector_load__________;\n if ((_metile_v34_r8) && (_metile_v34_r9) && (_metile_v34_r10) && (_metile_v34_r11) && (long(_metile_register_index_________) == long(_metile_register_index________) + 1) && (long(_metile_register_index__________) == long(_metile_register_index________) + 2) && (long(_metile_register_index___________) == long(_metile_register_index________) + 3)) {\n _metile_vector_load__________ = half4(*reinterpret_cast(W + _metile_register_index________));\n } else {\n _metile_vector_load__________[0] = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n _metile_vector_load__________[1] = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n _metile_vector_load__________[2] = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n _metile_vector_load__________[3] = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n }\n half _metile_v36_r8 = _metile_vector_load__________[0];\n half _metile_v36_r9 = _metile_vector_load__________[1];\n half _metile_v36_r10 = _metile_vector_load__________[2];\n half _metile_v36_r11 = _metile_vector_load__________[3];\n half4 _metile_vector_load___________;\n if ((_metile_v34_r12) && (_metile_v34_r13) && (_metile_v34_r14) && (_metile_v34_r15) && (long(_metile_register_index_____________) == long(_metile_register_index____________) + 1) && (long(_metile_register_index______________) == long(_metile_register_index____________) + 2) && (long(_metile_register_index_______________) == long(_metile_register_index____________) + 3)) {\n _metile_vector_load___________ = half4(*reinterpret_cast(W + _metile_register_index____________));\n } else {\n _metile_vector_load___________[0] = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n _metile_vector_load___________[1] = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n _metile_vector_load___________[2] = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n _metile_vector_load___________[3] = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n }\n half _metile_v36_r12 = _metile_vector_load___________[0];\n half _metile_v36_r13 = _metile_vector_load___________[1];\n half _metile_v36_r14 = _metile_vector_load___________[2];\n half _metile_v36_r15 = _metile_vector_load___________[3];\n half4 _metile_vector_load____________;\n if ((_metile_v34_r16) && (_metile_v34_r17) && (_metile_v34_r18) && (_metile_v34_r19) && (long(_metile_register_index_________________) == long(_metile_register_index________________) + 1) && (long(_metile_register_index__________________) == long(_metile_register_index________________) + 2) && (long(_metile_register_index___________________) == long(_metile_register_index________________) + 3)) {\n _metile_vector_load____________ = half4(*reinterpret_cast(W + _metile_register_index________________));\n } else {\n _metile_vector_load____________[0] = _metile_v34_r16 ? W[_metile_register_index________________] : static_cast(0);\n _metile_vector_load____________[1] = _metile_v34_r17 ? W[_metile_register_index_________________] : static_cast(0);\n _metile_vector_load____________[2] = _metile_v34_r18 ? W[_metile_register_index__________________] : static_cast(0);\n _metile_vector_load____________[3] = _metile_v34_r19 ? W[_metile_register_index___________________] : static_cast(0);\n }\n half _metile_v36_r16 = _metile_vector_load____________[0];\n half _metile_v36_r17 = _metile_vector_load____________[1];\n half _metile_v36_r18 = _metile_vector_load____________[2];\n half _metile_v36_r19 = _metile_vector_load____________[3];\n half4 _metile_vector_load_____________;\n if ((_metile_v34_r20) && (_metile_v34_r21) && (_metile_v34_r22) && (_metile_v34_r23) && (long(_metile_register_index_____________________) == long(_metile_register_index____________________) + 1) && (long(_metile_register_index______________________) == long(_metile_register_index____________________) + 2) && (long(_metile_register_index_______________________) == long(_metile_register_index____________________) + 3)) {\n _metile_vector_load_____________ = half4(*reinterpret_cast(W + _metile_register_index____________________));\n } else {\n _metile_vector_load_____________[0] = _metile_v34_r20 ? W[_metile_register_index____________________] : static_cast(0);\n _metile_vector_load_____________[1] = _metile_v34_r21 ? W[_metile_register_index_____________________] : static_cast(0);\n _metile_vector_load_____________[2] = _metile_v34_r22 ? W[_metile_register_index______________________] : static_cast(0);\n _metile_vector_load_____________[3] = _metile_v34_r23 ? W[_metile_register_index_______________________] : static_cast(0);\n }\n half _metile_v36_r20 = _metile_vector_load_____________[0];\n half _metile_v36_r21 = _metile_vector_load_____________[1];\n half _metile_v36_r22 = _metile_vector_load_____________[2];\n half _metile_v36_r23 = _metile_vector_load_____________[3];\n half4 _metile_vector_load______________;\n if ((_metile_v34_r24) && (_metile_v34_r25) && (_metile_v34_r26) && (_metile_v34_r27) && (long(_metile_register_index_________________________) == long(_metile_register_index________________________) + 1) && (long(_metile_register_index__________________________) == long(_metile_register_index________________________) + 2) && (long(_metile_register_index___________________________) == long(_metile_register_index________________________) + 3)) {\n _metile_vector_load______________ = half4(*reinterpret_cast(W + _metile_register_index________________________));\n } else {\n _metile_vector_load______________[0] = _metile_v34_r24 ? W[_metile_register_index________________________] : static_cast(0);\n _metile_vector_load______________[1] = _metile_v34_r25 ? W[_metile_register_index_________________________] : static_cast(0);\n _metile_vector_load______________[2] = _metile_v34_r26 ? W[_metile_register_index__________________________] : static_cast(0);\n _metile_vector_load______________[3] = _metile_v34_r27 ? W[_metile_register_index___________________________] : static_cast(0);\n }\n half _metile_v36_r24 = _metile_vector_load______________[0];\n half _metile_v36_r25 = _metile_vector_load______________[1];\n half _metile_v36_r26 = _metile_vector_load______________[2];\n half _metile_v36_r27 = _metile_vector_load______________[3];\n half4 _metile_vector_load_______________;\n if ((_metile_v34_r28) && (_metile_v34_r29) && (_metile_v34_r30) && (_metile_v34_r31) && (long(_metile_register_index_____________________________) == long(_metile_register_index____________________________) + 1) && (long(_metile_register_index______________________________) == long(_metile_register_index____________________________) + 2) && (long(_metile_register_index_______________________________) == long(_metile_register_index____________________________) + 3)) {\n _metile_vector_load_______________ = half4(*reinterpret_cast(W + _metile_register_index____________________________));\n } else {\n _metile_vector_load_______________[0] = _metile_v34_r28 ? W[_metile_register_index____________________________] : static_cast(0);\n _metile_vector_load_______________[1] = _metile_v34_r29 ? W[_metile_register_index_____________________________] : static_cast(0);\n _metile_vector_load_______________[2] = _metile_v34_r30 ? W[_metile_register_index______________________________] : static_cast(0);\n _metile_vector_load_______________[3] = _metile_v34_r31 ? W[_metile_register_index_______________________________] : static_cast(0);\n }\n half _metile_v36_r28 = _metile_vector_load_______________[0];\n half _metile_v36_r29 = _metile_vector_load_______________[1];\n half _metile_v36_r30 = _metile_vector_load_______________[2];\n half _metile_v36_r31 = _metile_vector_load_______________[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v37_r16 = static_cast(_metile_v36_r16);\n float _metile_v37_r17 = static_cast(_metile_v36_r17);\n float _metile_v37_r18 = static_cast(_metile_v36_r18);\n float _metile_v37_r19 = static_cast(_metile_v36_r19);\n float _metile_v37_r20 = static_cast(_metile_v36_r20);\n float _metile_v37_r21 = static_cast(_metile_v36_r21);\n float _metile_v37_r22 = static_cast(_metile_v36_r22);\n float _metile_v37_r23 = static_cast(_metile_v36_r23);\n float _metile_v37_r24 = static_cast(_metile_v36_r24);\n float _metile_v37_r25 = static_cast(_metile_v36_r25);\n float _metile_v37_r26 = static_cast(_metile_v36_r26);\n float _metile_v37_r27 = static_cast(_metile_v36_r27);\n float _metile_v37_r28 = static_cast(_metile_v36_r28);\n float _metile_v37_r29 = static_cast(_metile_v36_r29);\n float _metile_v37_r30 = static_cast(_metile_v36_r30);\n float _metile_v37_r31 = static_cast(_metile_v36_r31);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v38_r16 = _metile_v21_r16 * v29;\n float _metile_v38_r17 = _metile_v21_r17 * v29;\n float _metile_v38_r18 = _metile_v21_r18 * v29;\n float _metile_v38_r19 = _metile_v21_r19 * v29;\n float _metile_v38_r20 = _metile_v21_r20 * v29;\n float _metile_v38_r21 = _metile_v21_r21 * v29;\n float _metile_v38_r22 = _metile_v21_r22 * v29;\n float _metile_v38_r23 = _metile_v21_r23 * v29;\n float _metile_v38_r24 = _metile_v21_r24 * v29;\n float _metile_v38_r25 = _metile_v21_r25 * v29;\n float _metile_v38_r26 = _metile_v21_r26 * v29;\n float _metile_v38_r27 = _metile_v21_r27 * v29;\n float _metile_v38_r28 = _metile_v21_r28 * v29;\n float _metile_v38_r29 = _metile_v21_r29 * v29;\n float _metile_v38_r30 = _metile_v21_r30 * v29;\n float _metile_v38_r31 = _metile_v21_r31 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n float _metile_v39_r16 = _metile_v38_r16 * _metile_v37_r16;\n float _metile_v39_r17 = _metile_v38_r17 * _metile_v37_r17;\n float _metile_v39_r18 = _metile_v38_r18 * _metile_v37_r18;\n float _metile_v39_r19 = _metile_v38_r19 * _metile_v37_r19;\n float _metile_v39_r20 = _metile_v38_r20 * _metile_v37_r20;\n float _metile_v39_r21 = _metile_v38_r21 * _metile_v37_r21;\n float _metile_v39_r22 = _metile_v38_r22 * _metile_v37_r22;\n float _metile_v39_r23 = _metile_v38_r23 * _metile_v37_r23;\n float _metile_v39_r24 = _metile_v38_r24 * _metile_v37_r24;\n float _metile_v39_r25 = _metile_v38_r25 * _metile_v37_r25;\n float _metile_v39_r26 = _metile_v38_r26 * _metile_v37_r26;\n float _metile_v39_r27 = _metile_v38_r27 * _metile_v37_r27;\n float _metile_v39_r28 = _metile_v38_r28 * _metile_v37_r28;\n float _metile_v39_r29 = _metile_v38_r29 * _metile_v37_r29;\n float _metile_v39_r30 = _metile_v38_r30 * _metile_v37_r30;\n float _metile_v39_r31 = _metile_v38_r31 * _metile_v37_r31;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v41_r16 = _metile_register_index________________ >= 0;\n bool _metile_v41_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v41_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v41_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v41_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v41_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v41_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v41_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v41_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v41_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v41_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v41_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v41_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v41_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v41_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v41_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v42_r8 = _metile_register_index________ < 1024;\n bool _metile_v42_r9 = _metile_register_index_________ < 1024;\n bool _metile_v42_r10 = _metile_register_index__________ < 1024;\n bool _metile_v42_r11 = _metile_register_index___________ < 1024;\n bool _metile_v42_r12 = _metile_register_index____________ < 1024;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v42_r14 = _metile_register_index______________ < 1024;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v42_r16 = _metile_register_index________________ < 1024;\n bool _metile_v42_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v42_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v42_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v42_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v42_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v42_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v42_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v42_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v42_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v42_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v42_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v42_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v42_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v42_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v42_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n bool _metile_v43_r16 = _metile_v41_r16 & _metile_v42_r16;\n bool _metile_v43_r17 = _metile_v41_r17 & _metile_v42_r17;\n bool _metile_v43_r18 = _metile_v41_r18 & _metile_v42_r18;\n bool _metile_v43_r19 = _metile_v41_r19 & _metile_v42_r19;\n bool _metile_v43_r20 = _metile_v41_r20 & _metile_v42_r20;\n bool _metile_v43_r21 = _metile_v41_r21 & _metile_v42_r21;\n bool _metile_v43_r22 = _metile_v41_r22 & _metile_v42_r22;\n bool _metile_v43_r23 = _metile_v41_r23 & _metile_v42_r23;\n bool _metile_v43_r24 = _metile_v41_r24 & _metile_v42_r24;\n bool _metile_v43_r25 = _metile_v41_r25 & _metile_v42_r25;\n bool _metile_v43_r26 = _metile_v41_r26 & _metile_v42_r26;\n bool _metile_v43_r27 = _metile_v41_r27 & _metile_v42_r27;\n bool _metile_v43_r28 = _metile_v41_r28 & _metile_v42_r28;\n bool _metile_v43_r29 = _metile_v41_r29 & _metile_v42_r29;\n bool _metile_v43_r30 = _metile_v41_r30 & _metile_v42_r30;\n bool _metile_v43_r31 = _metile_v41_r31 & _metile_v42_r31;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n int _off__metile_v44_r16 = v9 + _metile_register_index________________;\n int _off__metile_v44_r17 = v9 + _metile_register_index_________________;\n int _off__metile_v44_r18 = v9 + _metile_register_index__________________;\n int _off__metile_v44_r19 = v9 + _metile_register_index___________________;\n int _off__metile_v44_r20 = v9 + _metile_register_index____________________;\n int _off__metile_v44_r21 = v9 + _metile_register_index_____________________;\n int _off__metile_v44_r22 = v9 + _metile_register_index______________________;\n int _off__metile_v44_r23 = v9 + _metile_register_index_______________________;\n int _off__metile_v44_r24 = v9 + _metile_register_index________________________;\n int _off__metile_v44_r25 = v9 + _metile_register_index_________________________;\n int _off__metile_v44_r26 = v9 + _metile_register_index__________________________;\n int _off__metile_v44_r27 = v9 + _metile_register_index___________________________;\n int _off__metile_v44_r28 = v9 + _metile_register_index____________________________;\n int _off__metile_v44_r29 = v9 + _metile_register_index_____________________________;\n int _off__metile_v44_r30 = v9 + _metile_register_index______________________________;\n int _off__metile_v44_r31 = v9 + _metile_register_index_______________________________;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_half4(half4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_half4(half4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n if ((_metile_v43_r8) && (_metile_v43_r9) && (_metile_v43_r10) && (_metile_v43_r11) && (long(_off__metile_v44_r9) == long(_off__metile_v44_r8) + 1) && (long(_off__metile_v44_r10) == long(_off__metile_v44_r8) + 2) && (long(_off__metile_v44_r11) == long(_off__metile_v44_r8) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r8) = packed_half4(half4(static_cast(_metile_v39_r8), static_cast(_metile_v39_r9), static_cast(_metile_v39_r10), static_cast(_metile_v39_r11)));\n } else {\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = static_cast(_metile_v39_r8); }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = static_cast(_metile_v39_r9); }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = static_cast(_metile_v39_r10); }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = static_cast(_metile_v39_r11); }\n }\n if ((_metile_v43_r12) && (_metile_v43_r13) && (_metile_v43_r14) && (_metile_v43_r15) && (long(_off__metile_v44_r13) == long(_off__metile_v44_r12) + 1) && (long(_off__metile_v44_r14) == long(_off__metile_v44_r12) + 2) && (long(_off__metile_v44_r15) == long(_off__metile_v44_r12) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r12) = packed_half4(half4(static_cast(_metile_v39_r12), static_cast(_metile_v39_r13), static_cast(_metile_v39_r14), static_cast(_metile_v39_r15)));\n } else {\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = static_cast(_metile_v39_r12); }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = static_cast(_metile_v39_r13); }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = static_cast(_metile_v39_r14); }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = static_cast(_metile_v39_r15); }\n }\n if ((_metile_v43_r16) && (_metile_v43_r17) && (_metile_v43_r18) && (_metile_v43_r19) && (long(_off__metile_v44_r17) == long(_off__metile_v44_r16) + 1) && (long(_off__metile_v44_r18) == long(_off__metile_v44_r16) + 2) && (long(_off__metile_v44_r19) == long(_off__metile_v44_r16) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r16) = packed_half4(half4(static_cast(_metile_v39_r16), static_cast(_metile_v39_r17), static_cast(_metile_v39_r18), static_cast(_metile_v39_r19)));\n } else {\n if (_metile_v43_r16) { Out[_off__metile_v44_r16] = static_cast(_metile_v39_r16); }\n if (_metile_v43_r17) { Out[_off__metile_v44_r17] = static_cast(_metile_v39_r17); }\n if (_metile_v43_r18) { Out[_off__metile_v44_r18] = static_cast(_metile_v39_r18); }\n if (_metile_v43_r19) { Out[_off__metile_v44_r19] = static_cast(_metile_v39_r19); }\n }\n if ((_metile_v43_r20) && (_metile_v43_r21) && (_metile_v43_r22) && (_metile_v43_r23) && (long(_off__metile_v44_r21) == long(_off__metile_v44_r20) + 1) && (long(_off__metile_v44_r22) == long(_off__metile_v44_r20) + 2) && (long(_off__metile_v44_r23) == long(_off__metile_v44_r20) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r20) = packed_half4(half4(static_cast(_metile_v39_r20), static_cast(_metile_v39_r21), static_cast(_metile_v39_r22), static_cast(_metile_v39_r23)));\n } else {\n if (_metile_v43_r20) { Out[_off__metile_v44_r20] = static_cast(_metile_v39_r20); }\n if (_metile_v43_r21) { Out[_off__metile_v44_r21] = static_cast(_metile_v39_r21); }\n if (_metile_v43_r22) { Out[_off__metile_v44_r22] = static_cast(_metile_v39_r22); }\n if (_metile_v43_r23) { Out[_off__metile_v44_r23] = static_cast(_metile_v39_r23); }\n }\n if ((_metile_v43_r24) && (_metile_v43_r25) && (_metile_v43_r26) && (_metile_v43_r27) && (long(_off__metile_v44_r25) == long(_off__metile_v44_r24) + 1) && (long(_off__metile_v44_r26) == long(_off__metile_v44_r24) + 2) && (long(_off__metile_v44_r27) == long(_off__metile_v44_r24) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r24) = packed_half4(half4(static_cast(_metile_v39_r24), static_cast(_metile_v39_r25), static_cast(_metile_v39_r26), static_cast(_metile_v39_r27)));\n } else {\n if (_metile_v43_r24) { Out[_off__metile_v44_r24] = static_cast(_metile_v39_r24); }\n if (_metile_v43_r25) { Out[_off__metile_v44_r25] = static_cast(_metile_v39_r25); }\n if (_metile_v43_r26) { Out[_off__metile_v44_r26] = static_cast(_metile_v39_r26); }\n if (_metile_v43_r27) { Out[_off__metile_v44_r27] = static_cast(_metile_v39_r27); }\n }\n if ((_metile_v43_r28) && (_metile_v43_r29) && (_metile_v43_r30) && (_metile_v43_r31) && (long(_off__metile_v44_r29) == long(_off__metile_v44_r28) + 1) && (long(_off__metile_v44_r30) == long(_off__metile_v44_r28) + 2) && (long(_off__metile_v44_r31) == long(_off__metile_v44_r28) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r28) = packed_half4(half4(static_cast(_metile_v39_r28), static_cast(_metile_v39_r29), static_cast(_metile_v39_r30), static_cast(_metile_v39_r31)));\n } else {\n if (_metile_v43_r28) { Out[_off__metile_v44_r28] = static_cast(_metile_v39_r28); }\n if (_metile_v43_r29) { Out[_off__metile_v44_r29] = static_cast(_metile_v39_r29); }\n if (_metile_v43_r30) { Out[_off__metile_v44_r30] = static_cast(_metile_v39_r30); }\n if (_metile_v43_r31) { Out[_off__metile_v44_r31] = static_cast(_metile_v39_r31); }\n }\n}", "source_sha256": "e71f6e91f3f76564671db8d5ee10d9f8eb51e2c1e61e3c1f613552152e99fce6", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 32, 1, 1 ], "is_gemm": false, "prefer_ordered": false, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 32, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 32 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [], "double_buffered": false, "vectorized_loads": 16, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 32, "threads": 32, "scratch": null, "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 16, "grouped_stores": 8 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 583, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.375, "control": 199.708, "speedup": 0.9966712414223331 }, "gpu_us": { "candidate": 3.374996595084667, "control": 1.9167200662195683, "speedup": 0.567917629609189 } } }, { "frozen_register4": { "pairs": 608, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.3125, "control": 199.20850000000002, "speedup": 0.9994782063342741 }, "gpu_us": { "candidate": 3.374996595084667, "control": 1.9166618585586548, "speedup": 0.5679003828774447 } } }, { "frozen_register4": { "pairs": 599, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.292, "control": 199.875, "speedup": 1.0029253557593882 }, "gpu_us": { "candidate": 3.374996595084667, "control": 1.9166618585586548, "speedup": 0.5679003828774447 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9996883299675752, "round_speedups": [ 0.9966712414223331, 0.9994782063342741, 1.0029253557593882 ], "candidate": 199.6591935014495, "control": 199.59696571413699 }, "gpu_us": { "speedup": 0.5679061317298304, "round_speedups": [ 0.567917629609189, 0.5679003828774447, 0.5679003828774447 ], "candidate": 3.374996595084667, "control": 1.9166812609158819 } } } }, { "name": "float16_32x1024", "dtype": "float16", "batches": 32, "width": 1024, "status": "measured", "variant": { "name": "register2_striped", "elements_per_thread": 2, "layout": "striped" }, "input_sha256": "6e821d0e3f7ad3cc0206f556836dd56fc15c5cc3181cc0547765f5bce1880ac4", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 511;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 512;\n int _metile_register_index_ = int(_metile_register_packed_);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n threadgroup float _metile_register_reduction[16];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 16u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n}", "source_sha256": "7904a94ae16a9a4d931c40f756c878c87106b2c4dc49872d49e6df50e4e1317d", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 512, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 512, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 2 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 16, "bytes": 64 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 2, "threads": 512, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 610, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.313, "control": 198.16649999999998, "speedup": 0.9892842701172665 }, "gpu_us": { "candidate": 1.833366695791483, "control": 1.9166618585586548, "speedup": 1.0454328983712735 } } }, { "frozen_register4": { "pairs": 579, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.5, "control": 201.083, "speedup": 1.007934837092732 }, "gpu_us": { "candidate": 1.8749851733446121, "control": 1.9166618585586548, "speedup": 1.0222277412144543 } } }, { "frozen_register4": { "pairs": 498, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.10399999999998, "control": 206.25, "speedup": 1.010514247638459 }, "gpu_us": { "candidate": 1.8749851733446121, "control": 1.9166618585586548, "speedup": 1.0222277412144543 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0025329767055478, "round_speedups": [ 0.9892842701172665, 1.007934837092732, 1.010514247638459 ], "candidate": 201.2957089647912, "control": 201.8055863065257 }, "gpu_us": { "speedup": 1.0299049907147462, "round_speedups": [ 1.0454328983712735, 1.0222277412144543, 1.0222277412144543 ], "candidate": 1.8610084190664096, "control": 1.9166618585586548 } } } }, { "name": "float16_32x1024", "dtype": "float16", "batches": 32, "width": 1024, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "6e821d0e3f7ad3cc0206f556836dd56fc15c5cc3181cc0547765f5bce1880ac4", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "a30e8c10d04f7806837b7362bac4a0f599f0d6d17735fc2e88198ca5dcb4e73d", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 611, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.458, "control": 198.875, "speedup": 0.9970770788837751 }, "gpu_us": { "candidate": 1.7916900105774403, "control": 1.9166618585586548, "speedup": 1.069750820311231 } } }, { "frozen_register4": { "pairs": 616, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.08350000000002, "control": 199.97899999999998, "speedup": 1.00956919682861 }, "gpu_us": { "candidate": 1.7916900105774403, "control": 1.9166618585586548, "speedup": 1.069750820311231 } } }, { "frozen_register4": { "pairs": 609, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.5, "control": 199.833, "speedup": 1.0016691729323308 }, "gpu_us": { "candidate": 1.7916900105774403, "control": 1.9166618585586548, "speedup": 1.069750820311231 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0027585586018826, "round_speedups": [ 0.9970770788837751, 1.00956919682861, 1.0016691729323308 ], "candidate": 199.01274363672195, "control": 199.56173195256505 }, "gpu_us": { "speedup": 1.069750820311231, "round_speedups": [ 1.069750820311231, 1.069750820311231, 1.069750820311231 ], "candidate": 1.7916900105774403, "control": 1.9166618585586548 } } } }, { "name": "float16_32x1024", "dtype": "float16", "batches": 32, "width": 1024, "status": "measured", "variant": { "name": "register4_blocked4", "elements_per_thread": 4, "layout": "blocked4" }, "input_sha256": "6e821d0e3f7ad3cc0206f556836dd56fc15c5cc3181cc0547765f5bce1880ac4", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int((((_metile_bounded_thread >> 8) & 1u) << 0) | (((_metile_bounded_thread >> 9) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 6) & 1u) << 8) | (((_metile_bounded_thread >> 7) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 8) & 1u) << 0) | (((_metile_register_packed_ >> 9) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 6) & 1u) << 8) | (((_metile_register_packed_ >> 7) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 8) & 1u) << 0) | (((_metile_register_packed__ >> 9) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 6) & 1u) << 8) | (((_metile_register_packed__ >> 7) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 8) & 1u) << 0) | (((_metile_register_packed___ >> 9) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 6) & 1u) << 8) | (((_metile_register_packed___ >> 7) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = half4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n half _metile_v20_r0 = _metile_vector_load[0];\n half _metile_v20_r1 = _metile_vector_load[1];\n half _metile_v20_r2 = _metile_vector_load[2];\n half _metile_v20_r3 = _metile_vector_load[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half4 _metile_vector_load_;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load_ = half4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load_[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load_[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load_[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load_[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n half _metile_v36_r0 = _metile_vector_load_[0];\n half _metile_v36_r1 = _metile_vector_load_[1];\n half _metile_v36_r2 = _metile_vector_load_[2];\n half _metile_v36_r3 = _metile_vector_load_[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_half4(half4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n}", "source_sha256": "2f5456f3b5088f163701ddb7dda6355b247755e6037315115cb7598baca96276", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 2, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 2, "grouped_stores": 1 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 609, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.292, "control": 200.75, "speedup": 1.0073158982799109 }, "gpu_us": { "candidate": 1.9583385437726974, "control": 1.9166618585586548, "speedup": 0.9787183450243728 } } }, { "frozen_register4": { "pairs": 610, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.688, "control": 198.6875, "speedup": 0.9949896839068948 }, "gpu_us": { "candidate": 1.9583385437726974, "control": 1.9166618585586548, "speedup": 0.9787183450243728 } } }, { "frozen_register4": { "pairs": 604, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.2495, "control": 198.91649999999998, "speedup": 0.9983287285538983 }, "gpu_us": { "candidate": 1.9583385437726974, "control": 1.9166618585586548, "speedup": 0.9787183450243728 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0001979154217464, "round_speedups": [ 1.0073158982799109, 0.9949896839068948, 0.9983287285538983 ], "candidate": 199.40973561538763, "control": 199.44920187731248 }, "gpu_us": { "speedup": 0.9787183450243728, "round_speedups": [ 0.9787183450243728, 0.9787183450243728, 0.9787183450243728 ], "candidate": 1.9583385437726972, "control": 1.9166618585586548 } } } }, { "name": "float16_32x1024", "dtype": "float16", "batches": 32, "width": 1024, "status": "measured", "variant": { "name": "register8_striped", "elements_per_thread": 8, "layout": "striped" }, "input_sha256": "6e821d0e3f7ad3cc0206f556836dd56fc15c5cc3181cc0547765f5bce1880ac4", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 127;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 128;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 256;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 384;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 512;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 640;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 768;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 896;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n half _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n half _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n half _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n half _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_____ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum______ = _metile_register_sum____ + _metile_register_sum_____;\n threadgroup float _metile_register_reduction[4];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 4u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n half _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n half _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n half _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n half _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n}", "source_sha256": "c52eee1a22cd9b99c0ecec2256f602f592be4c6e60d377eb925a553835a7a584", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 128, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 128, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 8 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 4, "bytes": 16 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 8, "threads": 128, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 532, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.72899999999998, "control": 200.58350000000002, "speedup": 1.0042782970925606 }, "gpu_us": { "candidate": 1.8333084881305695, "control": 1.9166618585586548, "speedup": 1.0454660909321818 } } }, { "frozen_register4": { "pairs": 595, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 196.916, "control": 198.958, "speedup": 1.0103699039184222 }, "gpu_us": { "candidate": 1.8333084881305695, "control": 1.9166618585586548, "speedup": 1.0454660909321818 } } }, { "frozen_register4": { "pairs": 579, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.417, "control": 198.0, "speedup": 0.987940144798096 }, "gpu_us": { "candidate": 1.8749851733446121, "control": 1.9583385437726974, "speedup": 1.0444554824289085 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0008178379966175, "round_speedups": [ 1.0042782970925606, 1.0103699039184222, 0.987940144798096 ], "candidate": 199.01488650968588, "control": 199.17764844576593 }, "gpu_us": { "speedup": 1.0451291128268576, "round_speedups": [ 1.0454660909321818, 1.0454660909321818, 1.0444554824289085 ], "candidate": 1.8470967553448585, "control": 1.9304545932189392 } } } }, { "name": "float16_32x1024", "dtype": "float16", "batches": 32, "width": 1024, "status": "measured", "variant": { "name": "register8_blocked4", "elements_per_thread": 8, "layout": "blocked4" }, "input_sha256": "6e821d0e3f7ad3cc0206f556836dd56fc15c5cc3181cc0547765f5bce1880ac4", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 127;\n int _metile_register_index = int((((_metile_bounded_thread >> 7) & 1u) << 0) | (((_metile_bounded_thread >> 8) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 6) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 128;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 7) & 1u) << 0) | (((_metile_register_packed_ >> 8) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 6) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 256;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 7) & 1u) << 0) | (((_metile_register_packed__ >> 8) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 6) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 384;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 7) & 1u) << 0) | (((_metile_register_packed___ >> 8) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 6) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 512;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 7) & 1u) << 0) | (((_metile_register_packed____ >> 8) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 5) & 1u) << 7) | (((_metile_register_packed____ >> 6) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 640;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 7) & 1u) << 0) | (((_metile_register_packed_____ >> 8) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 5) & 1u) << 7) | (((_metile_register_packed_____ >> 6) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 768;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 7) & 1u) << 0) | (((_metile_register_packed______ >> 8) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 5) & 1u) << 7) | (((_metile_register_packed______ >> 6) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 896;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 7) & 1u) << 0) | (((_metile_register_packed_______ >> 8) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 5) & 1u) << 7) | (((_metile_register_packed_______ >> 6) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n half4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = half4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n half _metile_v20_r0 = _metile_vector_load[0];\n half _metile_v20_r1 = _metile_vector_load[1];\n half _metile_v20_r2 = _metile_vector_load[2];\n half _metile_v20_r3 = _metile_vector_load[3];\n half4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = half4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n half _metile_v20_r4 = _metile_vector_load_[0];\n half _metile_v20_r5 = _metile_vector_load_[1];\n half _metile_v20_r6 = _metile_vector_load_[2];\n half _metile_v20_r7 = _metile_vector_load_[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_____ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum______ = _metile_register_sum____ + _metile_register_sum_____;\n threadgroup float _metile_register_reduction[4];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 4u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n half4 _metile_vector_load__;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load__ = half4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load__[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load__[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load__[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load__[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n half _metile_v36_r0 = _metile_vector_load__[0];\n half _metile_v36_r1 = _metile_vector_load__[1];\n half _metile_v36_r2 = _metile_vector_load__[2];\n half _metile_v36_r3 = _metile_vector_load__[3];\n half4 _metile_vector_load___;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load___ = half4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load___[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load___[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load___[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load___[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n half _metile_v36_r4 = _metile_vector_load___[0];\n half _metile_v36_r5 = _metile_vector_load___[1];\n half _metile_v36_r6 = _metile_vector_load___[2];\n half _metile_v36_r7 = _metile_vector_load___[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_half4(half4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_half4(half4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n}", "source_sha256": "0795515dc02028985d5e8efef00cea1dcab53425817a6bcfdff5ade2f974789f", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 128, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 128, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 8 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 4, "bytes": 16 } ], "double_buffered": false, "vectorized_loads": 4, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 8, "threads": 128, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 4, "grouped_stores": 2 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 599, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.959, "control": 199.208, "speedup": 1.001251514131052 }, "gpu_us": { "candidate": 2.083310391753912, "control": 1.958280336111784, "speedup": 0.9399849124081473 } } }, { "frozen_register4": { "pairs": 606, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.708, "control": 197.6875, "speedup": 0.9948643235300039 }, "gpu_us": { "candidate": 2.083310391753912, "control": 1.9166618585586548, "speedup": 0.9200078231957755 } } }, { "frozen_register4": { "pairs": 599, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.75, "control": 198.041, "speedup": 0.9964327044025157 }, "gpu_us": { "candidate": 2.083310391753912, "control": 1.9167200662195683, "speedup": 0.9200357631806879 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.997512481909608, "round_speedups": [ 1.001251514131052, 0.9948643235300039, 0.9964327044025157 ], "candidate": 198.80563636883326, "control": 198.31110375189385 }, "gpu_us": { "speedup": 0.9266286080888217, "round_speedups": [ 0.9399849124081473, 0.9200078231957755, 0.9200357631806879 ], "candidate": 2.083310391753912, "control": 1.9304550085279055 } } } }, { "name": "float16_256x1024", "dtype": "float16", "batches": 256, "width": 1024, "status": "measured", "variant": { "name": "register16_blocked4", "elements_per_thread": 16, "layout": "blocked4" }, "input_sha256": "fcaf7de00cd83d1d1e75063d1ab252906b9f1076e1f1c8a88d773ec19ed2a30c", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 63;\n int _metile_register_index = int((((_metile_bounded_thread >> 6) & 1u) << 0) | (((_metile_bounded_thread >> 7) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 8) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 64;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 6) & 1u) << 0) | (((_metile_register_packed_ >> 7) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 8) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 128;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 6) & 1u) << 0) | (((_metile_register_packed__ >> 7) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 8) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 192;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 6) & 1u) << 0) | (((_metile_register_packed___ >> 7) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 8) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 256;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 6) & 1u) << 0) | (((_metile_register_packed____ >> 7) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 5) & 1u) << 7) | (((_metile_register_packed____ >> 8) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 320;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 6) & 1u) << 0) | (((_metile_register_packed_____ >> 7) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 5) & 1u) << 7) | (((_metile_register_packed_____ >> 8) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 384;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 6) & 1u) << 0) | (((_metile_register_packed______ >> 7) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 5) & 1u) << 7) | (((_metile_register_packed______ >> 8) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 448;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 6) & 1u) << 0) | (((_metile_register_packed_______ >> 7) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 5) & 1u) << 7) | (((_metile_register_packed_______ >> 8) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n int _metile_register_packed________ = _metile_bounded_thread + 512;\n int _metile_register_index________ = int((((_metile_register_packed________ >> 6) & 1u) << 0) | (((_metile_register_packed________ >> 7) & 1u) << 1) | (((_metile_register_packed________ >> 0) & 1u) << 2) | (((_metile_register_packed________ >> 1) & 1u) << 3) | (((_metile_register_packed________ >> 2) & 1u) << 4) | (((_metile_register_packed________ >> 3) & 1u) << 5) | (((_metile_register_packed________ >> 4) & 1u) << 6) | (((_metile_register_packed________ >> 5) & 1u) << 7) | (((_metile_register_packed________ >> 8) & 1u) << 8) | (((_metile_register_packed________ >> 9) & 1u) << 9));\n int _metile_register_packed_________ = _metile_bounded_thread + 576;\n int _metile_register_index_________ = int((((_metile_register_packed_________ >> 6) & 1u) << 0) | (((_metile_register_packed_________ >> 7) & 1u) << 1) | (((_metile_register_packed_________ >> 0) & 1u) << 2) | (((_metile_register_packed_________ >> 1) & 1u) << 3) | (((_metile_register_packed_________ >> 2) & 1u) << 4) | (((_metile_register_packed_________ >> 3) & 1u) << 5) | (((_metile_register_packed_________ >> 4) & 1u) << 6) | (((_metile_register_packed_________ >> 5) & 1u) << 7) | (((_metile_register_packed_________ >> 8) & 1u) << 8) | (((_metile_register_packed_________ >> 9) & 1u) << 9));\n int _metile_register_packed__________ = _metile_bounded_thread + 640;\n int _metile_register_index__________ = int((((_metile_register_packed__________ >> 6) & 1u) << 0) | (((_metile_register_packed__________ >> 7) & 1u) << 1) | (((_metile_register_packed__________ >> 0) & 1u) << 2) | (((_metile_register_packed__________ >> 1) & 1u) << 3) | (((_metile_register_packed__________ >> 2) & 1u) << 4) | (((_metile_register_packed__________ >> 3) & 1u) << 5) | (((_metile_register_packed__________ >> 4) & 1u) << 6) | (((_metile_register_packed__________ >> 5) & 1u) << 7) | (((_metile_register_packed__________ >> 8) & 1u) << 8) | (((_metile_register_packed__________ >> 9) & 1u) << 9));\n int _metile_register_packed___________ = _metile_bounded_thread + 704;\n int _metile_register_index___________ = int((((_metile_register_packed___________ >> 6) & 1u) << 0) | (((_metile_register_packed___________ >> 7) & 1u) << 1) | (((_metile_register_packed___________ >> 0) & 1u) << 2) | (((_metile_register_packed___________ >> 1) & 1u) << 3) | (((_metile_register_packed___________ >> 2) & 1u) << 4) | (((_metile_register_packed___________ >> 3) & 1u) << 5) | (((_metile_register_packed___________ >> 4) & 1u) << 6) | (((_metile_register_packed___________ >> 5) & 1u) << 7) | (((_metile_register_packed___________ >> 8) & 1u) << 8) | (((_metile_register_packed___________ >> 9) & 1u) << 9));\n int _metile_register_packed____________ = _metile_bounded_thread + 768;\n int _metile_register_index____________ = int((((_metile_register_packed____________ >> 6) & 1u) << 0) | (((_metile_register_packed____________ >> 7) & 1u) << 1) | (((_metile_register_packed____________ >> 0) & 1u) << 2) | (((_metile_register_packed____________ >> 1) & 1u) << 3) | (((_metile_register_packed____________ >> 2) & 1u) << 4) | (((_metile_register_packed____________ >> 3) & 1u) << 5) | (((_metile_register_packed____________ >> 4) & 1u) << 6) | (((_metile_register_packed____________ >> 5) & 1u) << 7) | (((_metile_register_packed____________ >> 8) & 1u) << 8) | (((_metile_register_packed____________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________ = _metile_bounded_thread + 832;\n int _metile_register_index_____________ = int((((_metile_register_packed_____________ >> 6) & 1u) << 0) | (((_metile_register_packed_____________ >> 7) & 1u) << 1) | (((_metile_register_packed_____________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________ >> 5) & 1u) << 7) | (((_metile_register_packed_____________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________ >> 9) & 1u) << 9));\n int _metile_register_packed______________ = _metile_bounded_thread + 896;\n int _metile_register_index______________ = int((((_metile_register_packed______________ >> 6) & 1u) << 0) | (((_metile_register_packed______________ >> 7) & 1u) << 1) | (((_metile_register_packed______________ >> 0) & 1u) << 2) | (((_metile_register_packed______________ >> 1) & 1u) << 3) | (((_metile_register_packed______________ >> 2) & 1u) << 4) | (((_metile_register_packed______________ >> 3) & 1u) << 5) | (((_metile_register_packed______________ >> 4) & 1u) << 6) | (((_metile_register_packed______________ >> 5) & 1u) << 7) | (((_metile_register_packed______________ >> 8) & 1u) << 8) | (((_metile_register_packed______________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________ = _metile_bounded_thread + 960;\n int _metile_register_index_______________ = int((((_metile_register_packed_______________ >> 6) & 1u) << 0) | (((_metile_register_packed_______________ >> 7) & 1u) << 1) | (((_metile_register_packed_______________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________ >> 5) & 1u) << 7) | (((_metile_register_packed_______________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v17_r8 = _metile_register_index________ < 1024;\n bool _metile_v17_r9 = _metile_register_index_________ < 1024;\n bool _metile_v17_r10 = _metile_register_index__________ < 1024;\n bool _metile_v17_r11 = _metile_register_index___________ < 1024;\n bool _metile_v17_r12 = _metile_register_index____________ < 1024;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v17_r14 = _metile_register_index______________ < 1024;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n half4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = half4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n half _metile_v20_r0 = _metile_vector_load[0];\n half _metile_v20_r1 = _metile_vector_load[1];\n half _metile_v20_r2 = _metile_vector_load[2];\n half _metile_v20_r3 = _metile_vector_load[3];\n half4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = half4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n half _metile_v20_r4 = _metile_vector_load_[0];\n half _metile_v20_r5 = _metile_vector_load_[1];\n half _metile_v20_r6 = _metile_vector_load_[2];\n half _metile_v20_r7 = _metile_vector_load_[3];\n half4 _metile_vector_load__;\n if ((_metile_v18_r8) && (_metile_v18_r9) && (_metile_v18_r10) && (_metile_v18_r11) && (long(_off__metile_v19_r9) == long(_off__metile_v19_r8) + 1) && (long(_off__metile_v19_r10) == long(_off__metile_v19_r8) + 2) && (long(_off__metile_v19_r11) == long(_off__metile_v19_r8) + 3)) {\n _metile_vector_load__ = half4(*reinterpret_cast(X + _off__metile_v19_r8));\n } else {\n _metile_vector_load__[0] = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n _metile_vector_load__[1] = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n _metile_vector_load__[2] = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n _metile_vector_load__[3] = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n }\n half _metile_v20_r8 = _metile_vector_load__[0];\n half _metile_v20_r9 = _metile_vector_load__[1];\n half _metile_v20_r10 = _metile_vector_load__[2];\n half _metile_v20_r11 = _metile_vector_load__[3];\n half4 _metile_vector_load___;\n if ((_metile_v18_r12) && (_metile_v18_r13) && (_metile_v18_r14) && (_metile_v18_r15) && (long(_off__metile_v19_r13) == long(_off__metile_v19_r12) + 1) && (long(_off__metile_v19_r14) == long(_off__metile_v19_r12) + 2) && (long(_off__metile_v19_r15) == long(_off__metile_v19_r12) + 3)) {\n _metile_vector_load___ = half4(*reinterpret_cast(X + _off__metile_v19_r12));\n } else {\n _metile_vector_load___[0] = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n _metile_vector_load___[1] = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n _metile_vector_load___[2] = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n _metile_vector_load___[3] = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n }\n half _metile_v20_r12 = _metile_vector_load___[0];\n half _metile_v20_r13 = _metile_vector_load___[1];\n half _metile_v20_r14 = _metile_vector_load___[2];\n half _metile_v20_r15 = _metile_vector_load___[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________ = _metile_register_sum____________ + _metile_register_sum_____________;\n threadgroup float _metile_register_reduction[2];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______________);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 2u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v33_r8 = _metile_register_index________ < 1024;\n bool _metile_v33_r9 = _metile_register_index_________ < 1024;\n bool _metile_v33_r10 = _metile_register_index__________ < 1024;\n bool _metile_v33_r11 = _metile_register_index___________ < 1024;\n bool _metile_v33_r12 = _metile_register_index____________ < 1024;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v33_r14 = _metile_register_index______________ < 1024;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n half4 _metile_vector_load____;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load____ = half4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load____[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load____[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load____[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load____[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n half _metile_v36_r0 = _metile_vector_load____[0];\n half _metile_v36_r1 = _metile_vector_load____[1];\n half _metile_v36_r2 = _metile_vector_load____[2];\n half _metile_v36_r3 = _metile_vector_load____[3];\n half4 _metile_vector_load_____;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load_____ = half4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load_____[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load_____[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load_____[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load_____[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n half _metile_v36_r4 = _metile_vector_load_____[0];\n half _metile_v36_r5 = _metile_vector_load_____[1];\n half _metile_v36_r6 = _metile_vector_load_____[2];\n half _metile_v36_r7 = _metile_vector_load_____[3];\n half4 _metile_vector_load______;\n if ((_metile_v34_r8) && (_metile_v34_r9) && (_metile_v34_r10) && (_metile_v34_r11) && (long(_metile_register_index_________) == long(_metile_register_index________) + 1) && (long(_metile_register_index__________) == long(_metile_register_index________) + 2) && (long(_metile_register_index___________) == long(_metile_register_index________) + 3)) {\n _metile_vector_load______ = half4(*reinterpret_cast(W + _metile_register_index________));\n } else {\n _metile_vector_load______[0] = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n _metile_vector_load______[1] = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n _metile_vector_load______[2] = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n _metile_vector_load______[3] = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n }\n half _metile_v36_r8 = _metile_vector_load______[0];\n half _metile_v36_r9 = _metile_vector_load______[1];\n half _metile_v36_r10 = _metile_vector_load______[2];\n half _metile_v36_r11 = _metile_vector_load______[3];\n half4 _metile_vector_load_______;\n if ((_metile_v34_r12) && (_metile_v34_r13) && (_metile_v34_r14) && (_metile_v34_r15) && (long(_metile_register_index_____________) == long(_metile_register_index____________) + 1) && (long(_metile_register_index______________) == long(_metile_register_index____________) + 2) && (long(_metile_register_index_______________) == long(_metile_register_index____________) + 3)) {\n _metile_vector_load_______ = half4(*reinterpret_cast(W + _metile_register_index____________));\n } else {\n _metile_vector_load_______[0] = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n _metile_vector_load_______[1] = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n _metile_vector_load_______[2] = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n _metile_vector_load_______[3] = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n }\n half _metile_v36_r12 = _metile_vector_load_______[0];\n half _metile_v36_r13 = _metile_vector_load_______[1];\n half _metile_v36_r14 = _metile_vector_load_______[2];\n half _metile_v36_r15 = _metile_vector_load_______[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v42_r8 = _metile_register_index________ < 1024;\n bool _metile_v42_r9 = _metile_register_index_________ < 1024;\n bool _metile_v42_r10 = _metile_register_index__________ < 1024;\n bool _metile_v42_r11 = _metile_register_index___________ < 1024;\n bool _metile_v42_r12 = _metile_register_index____________ < 1024;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v42_r14 = _metile_register_index______________ < 1024;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_half4(half4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_half4(half4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n if ((_metile_v43_r8) && (_metile_v43_r9) && (_metile_v43_r10) && (_metile_v43_r11) && (long(_off__metile_v44_r9) == long(_off__metile_v44_r8) + 1) && (long(_off__metile_v44_r10) == long(_off__metile_v44_r8) + 2) && (long(_off__metile_v44_r11) == long(_off__metile_v44_r8) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r8) = packed_half4(half4(static_cast(_metile_v39_r8), static_cast(_metile_v39_r9), static_cast(_metile_v39_r10), static_cast(_metile_v39_r11)));\n } else {\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = static_cast(_metile_v39_r8); }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = static_cast(_metile_v39_r9); }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = static_cast(_metile_v39_r10); }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = static_cast(_metile_v39_r11); }\n }\n if ((_metile_v43_r12) && (_metile_v43_r13) && (_metile_v43_r14) && (_metile_v43_r15) && (long(_off__metile_v44_r13) == long(_off__metile_v44_r12) + 1) && (long(_off__metile_v44_r14) == long(_off__metile_v44_r12) + 2) && (long(_off__metile_v44_r15) == long(_off__metile_v44_r12) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r12) = packed_half4(half4(static_cast(_metile_v39_r12), static_cast(_metile_v39_r13), static_cast(_metile_v39_r14), static_cast(_metile_v39_r15)));\n } else {\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = static_cast(_metile_v39_r12); }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = static_cast(_metile_v39_r13); }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = static_cast(_metile_v39_r14); }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = static_cast(_metile_v39_r15); }\n }\n}", "source_sha256": "fd2a997847283829837787e56478df38b489706b6dd7fc7e98f217fcdab4f642", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 64, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 64, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 16 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 2, "bytes": 8 } ], "double_buffered": false, "vectorized_loads": 8, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 16, "threads": 64, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 8, "grouped_stores": 4 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 587, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 207.25, "control": 203.209, "speedup": 0.9805018094089264 }, "gpu_us": { "candidate": 5.62501372769475, "control": 4.916684702038765, "speedup": 0.8740751472003477 } } }, { "frozen_register4": { "pairs": 586, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 208.083, "control": 203.45850000000002, "speedup": 0.9777756952754431 }, "gpu_us": { "candidate": 5.62501372769475, "control": 4.9166264943778515, "speedup": 0.874064799196995 } } }, { "frozen_register4": { "pairs": 587, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 206.167, "control": 204.75, "speedup": 0.9931269310801437 }, "gpu_us": { "candidate": 5.62501372769475, "control": 4.9166264943778515, "speedup": 0.874064799196995 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9837788134321462, "round_speedups": [ 0.9805018094089264, 0.9777756952754431, 0.9931269310801437 ], "candidate": 207.1651809909956, "control": 203.8047159397773 }, "gpu_us": { "speedup": 0.8740682485178338, "round_speedups": [ 0.8740751472003477, 0.874064799196995, 0.874064799196995 ], "candidate": 5.62501372769475, "control": 4.916645896854922 } } } }, { "name": "float16_256x1024", "dtype": "float16", "batches": 256, "width": 1024, "status": "measured", "variant": { "name": "register32_striped", "elements_per_thread": 32, "layout": "striped" }, "input_sha256": "fcaf7de00cd83d1d1e75063d1ab252906b9f1076e1f1c8a88d773ec19ed2a30c", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 31;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 32;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 64;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 96;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 128;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 160;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 192;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 224;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n int _metile_register_packed________ = _metile_bounded_thread + 256;\n int _metile_register_index________ = int(_metile_register_packed________);\n int _metile_register_packed_________ = _metile_bounded_thread + 288;\n int _metile_register_index_________ = int(_metile_register_packed_________);\n int _metile_register_packed__________ = _metile_bounded_thread + 320;\n int _metile_register_index__________ = int(_metile_register_packed__________);\n int _metile_register_packed___________ = _metile_bounded_thread + 352;\n int _metile_register_index___________ = int(_metile_register_packed___________);\n int _metile_register_packed____________ = _metile_bounded_thread + 384;\n int _metile_register_index____________ = int(_metile_register_packed____________);\n int _metile_register_packed_____________ = _metile_bounded_thread + 416;\n int _metile_register_index_____________ = int(_metile_register_packed_____________);\n int _metile_register_packed______________ = _metile_bounded_thread + 448;\n int _metile_register_index______________ = int(_metile_register_packed______________);\n int _metile_register_packed_______________ = _metile_bounded_thread + 480;\n int _metile_register_index_______________ = int(_metile_register_packed_______________);\n int _metile_register_packed________________ = _metile_bounded_thread + 512;\n int _metile_register_index________________ = int(_metile_register_packed________________);\n int _metile_register_packed_________________ = _metile_bounded_thread + 544;\n int _metile_register_index_________________ = int(_metile_register_packed_________________);\n int _metile_register_packed__________________ = _metile_bounded_thread + 576;\n int _metile_register_index__________________ = int(_metile_register_packed__________________);\n int _metile_register_packed___________________ = _metile_bounded_thread + 608;\n int _metile_register_index___________________ = int(_metile_register_packed___________________);\n int _metile_register_packed____________________ = _metile_bounded_thread + 640;\n int _metile_register_index____________________ = int(_metile_register_packed____________________);\n int _metile_register_packed_____________________ = _metile_bounded_thread + 672;\n int _metile_register_index_____________________ = int(_metile_register_packed_____________________);\n int _metile_register_packed______________________ = _metile_bounded_thread + 704;\n int _metile_register_index______________________ = int(_metile_register_packed______________________);\n int _metile_register_packed_______________________ = _metile_bounded_thread + 736;\n int _metile_register_index_______________________ = int(_metile_register_packed_______________________);\n int _metile_register_packed________________________ = _metile_bounded_thread + 768;\n int _metile_register_index________________________ = int(_metile_register_packed________________________);\n int _metile_register_packed_________________________ = _metile_bounded_thread + 800;\n int _metile_register_index_________________________ = int(_metile_register_packed_________________________);\n int _metile_register_packed__________________________ = _metile_bounded_thread + 832;\n int _metile_register_index__________________________ = int(_metile_register_packed__________________________);\n int _metile_register_packed___________________________ = _metile_bounded_thread + 864;\n int _metile_register_index___________________________ = int(_metile_register_packed___________________________);\n int _metile_register_packed____________________________ = _metile_bounded_thread + 896;\n int _metile_register_index____________________________ = int(_metile_register_packed____________________________);\n int _metile_register_packed_____________________________ = _metile_bounded_thread + 928;\n int _metile_register_index_____________________________ = int(_metile_register_packed_____________________________);\n int _metile_register_packed______________________________ = _metile_bounded_thread + 960;\n int _metile_register_index______________________________ = int(_metile_register_packed______________________________);\n int _metile_register_packed_______________________________ = _metile_bounded_thread + 992;\n int _metile_register_index_______________________________ = int(_metile_register_packed_______________________________);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v16_r16 = _metile_register_index________________ >= 0;\n bool _metile_v16_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v16_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v16_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v16_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v16_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v16_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v16_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v16_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v16_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v16_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v16_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v16_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v16_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v16_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v16_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v17_r8 = _metile_register_index________ < 1024;\n bool _metile_v17_r9 = _metile_register_index_________ < 1024;\n bool _metile_v17_r10 = _metile_register_index__________ < 1024;\n bool _metile_v17_r11 = _metile_register_index___________ < 1024;\n bool _metile_v17_r12 = _metile_register_index____________ < 1024;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v17_r14 = _metile_register_index______________ < 1024;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v17_r16 = _metile_register_index________________ < 1024;\n bool _metile_v17_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v17_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v17_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v17_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v17_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v17_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v17_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v17_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v17_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v17_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v17_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v17_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v17_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v17_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v17_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n bool _metile_v18_r16 = _metile_v16_r16 & _metile_v17_r16;\n bool _metile_v18_r17 = _metile_v16_r17 & _metile_v17_r17;\n bool _metile_v18_r18 = _metile_v16_r18 & _metile_v17_r18;\n bool _metile_v18_r19 = _metile_v16_r19 & _metile_v17_r19;\n bool _metile_v18_r20 = _metile_v16_r20 & _metile_v17_r20;\n bool _metile_v18_r21 = _metile_v16_r21 & _metile_v17_r21;\n bool _metile_v18_r22 = _metile_v16_r22 & _metile_v17_r22;\n bool _metile_v18_r23 = _metile_v16_r23 & _metile_v17_r23;\n bool _metile_v18_r24 = _metile_v16_r24 & _metile_v17_r24;\n bool _metile_v18_r25 = _metile_v16_r25 & _metile_v17_r25;\n bool _metile_v18_r26 = _metile_v16_r26 & _metile_v17_r26;\n bool _metile_v18_r27 = _metile_v16_r27 & _metile_v17_r27;\n bool _metile_v18_r28 = _metile_v16_r28 & _metile_v17_r28;\n bool _metile_v18_r29 = _metile_v16_r29 & _metile_v17_r29;\n bool _metile_v18_r30 = _metile_v16_r30 & _metile_v17_r30;\n bool _metile_v18_r31 = _metile_v16_r31 & _metile_v17_r31;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n int _off__metile_v19_r16 = v2 + _metile_register_index________________;\n int _off__metile_v19_r17 = v2 + _metile_register_index_________________;\n int _off__metile_v19_r18 = v2 + _metile_register_index__________________;\n int _off__metile_v19_r19 = v2 + _metile_register_index___________________;\n int _off__metile_v19_r20 = v2 + _metile_register_index____________________;\n int _off__metile_v19_r21 = v2 + _metile_register_index_____________________;\n int _off__metile_v19_r22 = v2 + _metile_register_index______________________;\n int _off__metile_v19_r23 = v2 + _metile_register_index_______________________;\n int _off__metile_v19_r24 = v2 + _metile_register_index________________________;\n int _off__metile_v19_r25 = v2 + _metile_register_index_________________________;\n int _off__metile_v19_r26 = v2 + _metile_register_index__________________________;\n int _off__metile_v19_r27 = v2 + _metile_register_index___________________________;\n int _off__metile_v19_r28 = v2 + _metile_register_index____________________________;\n int _off__metile_v19_r29 = v2 + _metile_register_index_____________________________;\n int _off__metile_v19_r30 = v2 + _metile_register_index______________________________;\n int _off__metile_v19_r31 = v2 + _metile_register_index_______________________________;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n half _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n half _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n half _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n half _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n half _metile_v20_r8 = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n half _metile_v20_r9 = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n half _metile_v20_r10 = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n half _metile_v20_r11 = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n half _metile_v20_r12 = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n half _metile_v20_r13 = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n half _metile_v20_r14 = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n half _metile_v20_r15 = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n half _metile_v20_r16 = _metile_v18_r16 ? X[_off__metile_v19_r16] : static_cast(0);\n half _metile_v20_r17 = _metile_v18_r17 ? X[_off__metile_v19_r17] : static_cast(0);\n half _metile_v20_r18 = _metile_v18_r18 ? X[_off__metile_v19_r18] : static_cast(0);\n half _metile_v20_r19 = _metile_v18_r19 ? X[_off__metile_v19_r19] : static_cast(0);\n half _metile_v20_r20 = _metile_v18_r20 ? X[_off__metile_v19_r20] : static_cast(0);\n half _metile_v20_r21 = _metile_v18_r21 ? X[_off__metile_v19_r21] : static_cast(0);\n half _metile_v20_r22 = _metile_v18_r22 ? X[_off__metile_v19_r22] : static_cast(0);\n half _metile_v20_r23 = _metile_v18_r23 ? X[_off__metile_v19_r23] : static_cast(0);\n half _metile_v20_r24 = _metile_v18_r24 ? X[_off__metile_v19_r24] : static_cast(0);\n half _metile_v20_r25 = _metile_v18_r25 ? X[_off__metile_v19_r25] : static_cast(0);\n half _metile_v20_r26 = _metile_v18_r26 ? X[_off__metile_v19_r26] : static_cast(0);\n half _metile_v20_r27 = _metile_v18_r27 ? X[_off__metile_v19_r27] : static_cast(0);\n half _metile_v20_r28 = _metile_v18_r28 ? X[_off__metile_v19_r28] : static_cast(0);\n half _metile_v20_r29 = _metile_v18_r29 ? X[_off__metile_v19_r29] : static_cast(0);\n half _metile_v20_r30 = _metile_v18_r30 ? X[_off__metile_v19_r30] : static_cast(0);\n half _metile_v20_r31 = _metile_v18_r31 ? X[_off__metile_v19_r31] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v21_r16 = static_cast(_metile_v20_r16);\n float _metile_v21_r17 = static_cast(_metile_v20_r17);\n float _metile_v21_r18 = static_cast(_metile_v20_r18);\n float _metile_v21_r19 = static_cast(_metile_v20_r19);\n float _metile_v21_r20 = static_cast(_metile_v20_r20);\n float _metile_v21_r21 = static_cast(_metile_v20_r21);\n float _metile_v21_r22 = static_cast(_metile_v20_r22);\n float _metile_v21_r23 = static_cast(_metile_v20_r23);\n float _metile_v21_r24 = static_cast(_metile_v20_r24);\n float _metile_v21_r25 = static_cast(_metile_v20_r25);\n float _metile_v21_r26 = static_cast(_metile_v20_r26);\n float _metile_v21_r27 = static_cast(_metile_v20_r27);\n float _metile_v21_r28 = static_cast(_metile_v20_r28);\n float _metile_v21_r29 = static_cast(_metile_v20_r29);\n float _metile_v21_r30 = static_cast(_metile_v20_r30);\n float _metile_v21_r31 = static_cast(_metile_v20_r31);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_v22_r16 = _metile_v21_r16 * _metile_v21_r16;\n float _metile_v22_r17 = _metile_v21_r17 * _metile_v21_r17;\n float _metile_v22_r18 = _metile_v21_r18 * _metile_v21_r18;\n float _metile_v22_r19 = _metile_v21_r19 * _metile_v21_r19;\n float _metile_v22_r20 = _metile_v21_r20 * _metile_v21_r20;\n float _metile_v22_r21 = _metile_v21_r21 * _metile_v21_r21;\n float _metile_v22_r22 = _metile_v21_r22 * _metile_v21_r22;\n float _metile_v22_r23 = _metile_v21_r23 * _metile_v21_r23;\n float _metile_v22_r24 = _metile_v21_r24 * _metile_v21_r24;\n float _metile_v22_r25 = _metile_v21_r25 * _metile_v21_r25;\n float _metile_v22_r26 = _metile_v21_r26 * _metile_v21_r26;\n float _metile_v22_r27 = _metile_v21_r27 * _metile_v21_r27;\n float _metile_v22_r28 = _metile_v21_r28 * _metile_v21_r28;\n float _metile_v22_r29 = _metile_v21_r29 * _metile_v21_r29;\n float _metile_v22_r30 = _metile_v21_r30 * _metile_v21_r30;\n float _metile_v22_r31 = _metile_v21_r31 * _metile_v21_r31;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_v22_r16 + _metile_v22_r17;\n float _metile_register_sum_________ = _metile_v22_r18 + _metile_v22_r19;\n float _metile_register_sum__________ = _metile_v22_r20 + _metile_v22_r21;\n float _metile_register_sum___________ = _metile_v22_r22 + _metile_v22_r23;\n float _metile_register_sum____________ = _metile_v22_r24 + _metile_v22_r25;\n float _metile_register_sum_____________ = _metile_v22_r26 + _metile_v22_r27;\n float _metile_register_sum______________ = _metile_v22_r28 + _metile_v22_r29;\n float _metile_register_sum_______________ = _metile_v22_r30 + _metile_v22_r31;\n float _metile_register_sum________________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________________ = _metile_register_sum____________ + _metile_register_sum_____________;\n float _metile_register_sum_______________________ = _metile_register_sum______________ + _metile_register_sum_______________;\n float _metile_register_sum________________________ = _metile_register_sum________________ + _metile_register_sum_________________;\n float _metile_register_sum_________________________ = _metile_register_sum__________________ + _metile_register_sum___________________;\n float _metile_register_sum__________________________ = _metile_register_sum____________________ + _metile_register_sum_____________________;\n float _metile_register_sum___________________________ = _metile_register_sum______________________ + _metile_register_sum_______________________;\n float _metile_register_sum____________________________ = _metile_register_sum________________________ + _metile_register_sum_________________________;\n float _metile_register_sum_____________________________ = _metile_register_sum__________________________ + _metile_register_sum___________________________;\n float _metile_register_sum______________________________ = _metile_register_sum____________________________ + _metile_register_sum_____________________________;\n float v23 = simd_sum(_metile_register_sum______________________________);\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v32_r16 = _metile_register_index________________ >= 0;\n bool _metile_v32_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v32_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v32_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v32_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v32_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v32_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v32_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v32_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v32_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v32_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v32_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v32_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v32_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v32_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v32_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v33_r8 = _metile_register_index________ < 1024;\n bool _metile_v33_r9 = _metile_register_index_________ < 1024;\n bool _metile_v33_r10 = _metile_register_index__________ < 1024;\n bool _metile_v33_r11 = _metile_register_index___________ < 1024;\n bool _metile_v33_r12 = _metile_register_index____________ < 1024;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v33_r14 = _metile_register_index______________ < 1024;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v33_r16 = _metile_register_index________________ < 1024;\n bool _metile_v33_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v33_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v33_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v33_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v33_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v33_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v33_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v33_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v33_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v33_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v33_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v33_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v33_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v33_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v33_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n bool _metile_v34_r16 = _metile_v32_r16 & _metile_v33_r16;\n bool _metile_v34_r17 = _metile_v32_r17 & _metile_v33_r17;\n bool _metile_v34_r18 = _metile_v32_r18 & _metile_v33_r18;\n bool _metile_v34_r19 = _metile_v32_r19 & _metile_v33_r19;\n bool _metile_v34_r20 = _metile_v32_r20 & _metile_v33_r20;\n bool _metile_v34_r21 = _metile_v32_r21 & _metile_v33_r21;\n bool _metile_v34_r22 = _metile_v32_r22 & _metile_v33_r22;\n bool _metile_v34_r23 = _metile_v32_r23 & _metile_v33_r23;\n bool _metile_v34_r24 = _metile_v32_r24 & _metile_v33_r24;\n bool _metile_v34_r25 = _metile_v32_r25 & _metile_v33_r25;\n bool _metile_v34_r26 = _metile_v32_r26 & _metile_v33_r26;\n bool _metile_v34_r27 = _metile_v32_r27 & _metile_v33_r27;\n bool _metile_v34_r28 = _metile_v32_r28 & _metile_v33_r28;\n bool _metile_v34_r29 = _metile_v32_r29 & _metile_v33_r29;\n bool _metile_v34_r30 = _metile_v32_r30 & _metile_v33_r30;\n bool _metile_v34_r31 = _metile_v32_r31 & _metile_v33_r31;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n half _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n half _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n half _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n half _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n half _metile_v36_r8 = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n half _metile_v36_r9 = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n half _metile_v36_r10 = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n half _metile_v36_r11 = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n half _metile_v36_r12 = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n half _metile_v36_r13 = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n half _metile_v36_r14 = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n half _metile_v36_r15 = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n half _metile_v36_r16 = _metile_v34_r16 ? W[_metile_register_index________________] : static_cast(0);\n half _metile_v36_r17 = _metile_v34_r17 ? W[_metile_register_index_________________] : static_cast(0);\n half _metile_v36_r18 = _metile_v34_r18 ? W[_metile_register_index__________________] : static_cast(0);\n half _metile_v36_r19 = _metile_v34_r19 ? W[_metile_register_index___________________] : static_cast(0);\n half _metile_v36_r20 = _metile_v34_r20 ? W[_metile_register_index____________________] : static_cast(0);\n half _metile_v36_r21 = _metile_v34_r21 ? W[_metile_register_index_____________________] : static_cast(0);\n half _metile_v36_r22 = _metile_v34_r22 ? W[_metile_register_index______________________] : static_cast(0);\n half _metile_v36_r23 = _metile_v34_r23 ? W[_metile_register_index_______________________] : static_cast(0);\n half _metile_v36_r24 = _metile_v34_r24 ? W[_metile_register_index________________________] : static_cast(0);\n half _metile_v36_r25 = _metile_v34_r25 ? W[_metile_register_index_________________________] : static_cast(0);\n half _metile_v36_r26 = _metile_v34_r26 ? W[_metile_register_index__________________________] : static_cast(0);\n half _metile_v36_r27 = _metile_v34_r27 ? W[_metile_register_index___________________________] : static_cast(0);\n half _metile_v36_r28 = _metile_v34_r28 ? W[_metile_register_index____________________________] : static_cast(0);\n half _metile_v36_r29 = _metile_v34_r29 ? W[_metile_register_index_____________________________] : static_cast(0);\n half _metile_v36_r30 = _metile_v34_r30 ? W[_metile_register_index______________________________] : static_cast(0);\n half _metile_v36_r31 = _metile_v34_r31 ? W[_metile_register_index_______________________________] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v37_r16 = static_cast(_metile_v36_r16);\n float _metile_v37_r17 = static_cast(_metile_v36_r17);\n float _metile_v37_r18 = static_cast(_metile_v36_r18);\n float _metile_v37_r19 = static_cast(_metile_v36_r19);\n float _metile_v37_r20 = static_cast(_metile_v36_r20);\n float _metile_v37_r21 = static_cast(_metile_v36_r21);\n float _metile_v37_r22 = static_cast(_metile_v36_r22);\n float _metile_v37_r23 = static_cast(_metile_v36_r23);\n float _metile_v37_r24 = static_cast(_metile_v36_r24);\n float _metile_v37_r25 = static_cast(_metile_v36_r25);\n float _metile_v37_r26 = static_cast(_metile_v36_r26);\n float _metile_v37_r27 = static_cast(_metile_v36_r27);\n float _metile_v37_r28 = static_cast(_metile_v36_r28);\n float _metile_v37_r29 = static_cast(_metile_v36_r29);\n float _metile_v37_r30 = static_cast(_metile_v36_r30);\n float _metile_v37_r31 = static_cast(_metile_v36_r31);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v38_r16 = _metile_v21_r16 * v29;\n float _metile_v38_r17 = _metile_v21_r17 * v29;\n float _metile_v38_r18 = _metile_v21_r18 * v29;\n float _metile_v38_r19 = _metile_v21_r19 * v29;\n float _metile_v38_r20 = _metile_v21_r20 * v29;\n float _metile_v38_r21 = _metile_v21_r21 * v29;\n float _metile_v38_r22 = _metile_v21_r22 * v29;\n float _metile_v38_r23 = _metile_v21_r23 * v29;\n float _metile_v38_r24 = _metile_v21_r24 * v29;\n float _metile_v38_r25 = _metile_v21_r25 * v29;\n float _metile_v38_r26 = _metile_v21_r26 * v29;\n float _metile_v38_r27 = _metile_v21_r27 * v29;\n float _metile_v38_r28 = _metile_v21_r28 * v29;\n float _metile_v38_r29 = _metile_v21_r29 * v29;\n float _metile_v38_r30 = _metile_v21_r30 * v29;\n float _metile_v38_r31 = _metile_v21_r31 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n float _metile_v39_r16 = _metile_v38_r16 * _metile_v37_r16;\n float _metile_v39_r17 = _metile_v38_r17 * _metile_v37_r17;\n float _metile_v39_r18 = _metile_v38_r18 * _metile_v37_r18;\n float _metile_v39_r19 = _metile_v38_r19 * _metile_v37_r19;\n float _metile_v39_r20 = _metile_v38_r20 * _metile_v37_r20;\n float _metile_v39_r21 = _metile_v38_r21 * _metile_v37_r21;\n float _metile_v39_r22 = _metile_v38_r22 * _metile_v37_r22;\n float _metile_v39_r23 = _metile_v38_r23 * _metile_v37_r23;\n float _metile_v39_r24 = _metile_v38_r24 * _metile_v37_r24;\n float _metile_v39_r25 = _metile_v38_r25 * _metile_v37_r25;\n float _metile_v39_r26 = _metile_v38_r26 * _metile_v37_r26;\n float _metile_v39_r27 = _metile_v38_r27 * _metile_v37_r27;\n float _metile_v39_r28 = _metile_v38_r28 * _metile_v37_r28;\n float _metile_v39_r29 = _metile_v38_r29 * _metile_v37_r29;\n float _metile_v39_r30 = _metile_v38_r30 * _metile_v37_r30;\n float _metile_v39_r31 = _metile_v38_r31 * _metile_v37_r31;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v41_r16 = _metile_register_index________________ >= 0;\n bool _metile_v41_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v41_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v41_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v41_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v41_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v41_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v41_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v41_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v41_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v41_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v41_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v41_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v41_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v41_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v41_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v42_r8 = _metile_register_index________ < 1024;\n bool _metile_v42_r9 = _metile_register_index_________ < 1024;\n bool _metile_v42_r10 = _metile_register_index__________ < 1024;\n bool _metile_v42_r11 = _metile_register_index___________ < 1024;\n bool _metile_v42_r12 = _metile_register_index____________ < 1024;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v42_r14 = _metile_register_index______________ < 1024;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v42_r16 = _metile_register_index________________ < 1024;\n bool _metile_v42_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v42_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v42_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v42_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v42_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v42_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v42_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v42_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v42_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v42_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v42_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v42_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v42_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v42_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v42_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n bool _metile_v43_r16 = _metile_v41_r16 & _metile_v42_r16;\n bool _metile_v43_r17 = _metile_v41_r17 & _metile_v42_r17;\n bool _metile_v43_r18 = _metile_v41_r18 & _metile_v42_r18;\n bool _metile_v43_r19 = _metile_v41_r19 & _metile_v42_r19;\n bool _metile_v43_r20 = _metile_v41_r20 & _metile_v42_r20;\n bool _metile_v43_r21 = _metile_v41_r21 & _metile_v42_r21;\n bool _metile_v43_r22 = _metile_v41_r22 & _metile_v42_r22;\n bool _metile_v43_r23 = _metile_v41_r23 & _metile_v42_r23;\n bool _metile_v43_r24 = _metile_v41_r24 & _metile_v42_r24;\n bool _metile_v43_r25 = _metile_v41_r25 & _metile_v42_r25;\n bool _metile_v43_r26 = _metile_v41_r26 & _metile_v42_r26;\n bool _metile_v43_r27 = _metile_v41_r27 & _metile_v42_r27;\n bool _metile_v43_r28 = _metile_v41_r28 & _metile_v42_r28;\n bool _metile_v43_r29 = _metile_v41_r29 & _metile_v42_r29;\n bool _metile_v43_r30 = _metile_v41_r30 & _metile_v42_r30;\n bool _metile_v43_r31 = _metile_v41_r31 & _metile_v42_r31;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n int _off__metile_v44_r16 = v9 + _metile_register_index________________;\n int _off__metile_v44_r17 = v9 + _metile_register_index_________________;\n int _off__metile_v44_r18 = v9 + _metile_register_index__________________;\n int _off__metile_v44_r19 = v9 + _metile_register_index___________________;\n int _off__metile_v44_r20 = v9 + _metile_register_index____________________;\n int _off__metile_v44_r21 = v9 + _metile_register_index_____________________;\n int _off__metile_v44_r22 = v9 + _metile_register_index______________________;\n int _off__metile_v44_r23 = v9 + _metile_register_index_______________________;\n int _off__metile_v44_r24 = v9 + _metile_register_index________________________;\n int _off__metile_v44_r25 = v9 + _metile_register_index_________________________;\n int _off__metile_v44_r26 = v9 + _metile_register_index__________________________;\n int _off__metile_v44_r27 = v9 + _metile_register_index___________________________;\n int _off__metile_v44_r28 = v9 + _metile_register_index____________________________;\n int _off__metile_v44_r29 = v9 + _metile_register_index_____________________________;\n int _off__metile_v44_r30 = v9 + _metile_register_index______________________________;\n int _off__metile_v44_r31 = v9 + _metile_register_index_______________________________;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = _metile_v39_r8; }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = _metile_v39_r9; }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = _metile_v39_r10; }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = _metile_v39_r11; }\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = _metile_v39_r12; }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = _metile_v39_r13; }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = _metile_v39_r14; }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = _metile_v39_r15; }\n if (_metile_v43_r16) { Out[_off__metile_v44_r16] = _metile_v39_r16; }\n if (_metile_v43_r17) { Out[_off__metile_v44_r17] = _metile_v39_r17; }\n if (_metile_v43_r18) { Out[_off__metile_v44_r18] = _metile_v39_r18; }\n if (_metile_v43_r19) { Out[_off__metile_v44_r19] = _metile_v39_r19; }\n if (_metile_v43_r20) { Out[_off__metile_v44_r20] = _metile_v39_r20; }\n if (_metile_v43_r21) { Out[_off__metile_v44_r21] = _metile_v39_r21; }\n if (_metile_v43_r22) { Out[_off__metile_v44_r22] = _metile_v39_r22; }\n if (_metile_v43_r23) { Out[_off__metile_v44_r23] = _metile_v39_r23; }\n if (_metile_v43_r24) { Out[_off__metile_v44_r24] = _metile_v39_r24; }\n if (_metile_v43_r25) { Out[_off__metile_v44_r25] = _metile_v39_r25; }\n if (_metile_v43_r26) { Out[_off__metile_v44_r26] = _metile_v39_r26; }\n if (_metile_v43_r27) { Out[_off__metile_v44_r27] = _metile_v39_r27; }\n if (_metile_v43_r28) { Out[_off__metile_v44_r28] = _metile_v39_r28; }\n if (_metile_v43_r29) { Out[_off__metile_v44_r29] = _metile_v39_r29; }\n if (_metile_v43_r30) { Out[_off__metile_v44_r30] = _metile_v39_r30; }\n if (_metile_v43_r31) { Out[_off__metile_v44_r31] = _metile_v39_r31; }\n}", "source_sha256": "a52a8c0239924732be4213a7549695361b8367e8f1fc6ffa94dbf8f3a8880747", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 32, 1, 1 ], "is_gemm": false, "prefer_ordered": false, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 32, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 32 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 32, "threads": 32, "scratch": null, "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 524, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 206.375, "control": 206.10399999999998, "speedup": 0.9986868564506359 }, "gpu_us": { "candidate": 4.875008016824722, "control": 4.999979864805937, "speedup": 1.0256352087114338 } } }, { "frozen_register4": { "pairs": 494, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 207.417, "control": 208.83350000000002, "speedup": 1.006829237719184 }, "gpu_us": { "candidate": 4.875008016824722, "control": 4.999979864805937, "speedup": 1.0256352087114338 } } }, { "frozen_register4": { "pairs": 583, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 207.167, "control": 202.375, "speedup": 0.9768689028658039 }, "gpu_us": { "candidate": 4.875008016824722, "control": 4.999979864805937, "speedup": 1.0256352087114338 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9940475194077695, "round_speedups": [ 0.9986868564506359, 1.006829237719184, 0.9768689028658039 ], "candidate": 206.98585640680741, "control": 205.7537771136795 }, "gpu_us": { "speedup": 1.0256352087114338, "round_speedups": [ 1.0256352087114338, 1.0256352087114338, 1.0256352087114338 ], "candidate": 4.875008016824721, "control": 4.999979864805936 } } } }, { "name": "float16_256x1024", "dtype": "float16", "batches": 256, "width": 1024, "status": "measured", "variant": { "name": "register32_blocked4", "elements_per_thread": 32, "layout": "blocked4" }, "input_sha256": "fcaf7de00cd83d1d1e75063d1ab252906b9f1076e1f1c8a88d773ec19ed2a30c", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 31;\n int _metile_register_index = int((((_metile_bounded_thread >> 5) & 1u) << 0) | (((_metile_bounded_thread >> 6) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 7) & 1u) << 7) | (((_metile_bounded_thread >> 8) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 32;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 5) & 1u) << 0) | (((_metile_register_packed_ >> 6) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 7) & 1u) << 7) | (((_metile_register_packed_ >> 8) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 64;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 5) & 1u) << 0) | (((_metile_register_packed__ >> 6) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 7) & 1u) << 7) | (((_metile_register_packed__ >> 8) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 96;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 5) & 1u) << 0) | (((_metile_register_packed___ >> 6) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 7) & 1u) << 7) | (((_metile_register_packed___ >> 8) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 128;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 5) & 1u) << 0) | (((_metile_register_packed____ >> 6) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 7) & 1u) << 7) | (((_metile_register_packed____ >> 8) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 160;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 5) & 1u) << 0) | (((_metile_register_packed_____ >> 6) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 7) & 1u) << 7) | (((_metile_register_packed_____ >> 8) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 192;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 5) & 1u) << 0) | (((_metile_register_packed______ >> 6) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 7) & 1u) << 7) | (((_metile_register_packed______ >> 8) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 224;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 5) & 1u) << 0) | (((_metile_register_packed_______ >> 6) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 7) & 1u) << 7) | (((_metile_register_packed_______ >> 8) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n int _metile_register_packed________ = _metile_bounded_thread + 256;\n int _metile_register_index________ = int((((_metile_register_packed________ >> 5) & 1u) << 0) | (((_metile_register_packed________ >> 6) & 1u) << 1) | (((_metile_register_packed________ >> 0) & 1u) << 2) | (((_metile_register_packed________ >> 1) & 1u) << 3) | (((_metile_register_packed________ >> 2) & 1u) << 4) | (((_metile_register_packed________ >> 3) & 1u) << 5) | (((_metile_register_packed________ >> 4) & 1u) << 6) | (((_metile_register_packed________ >> 7) & 1u) << 7) | (((_metile_register_packed________ >> 8) & 1u) << 8) | (((_metile_register_packed________ >> 9) & 1u) << 9));\n int _metile_register_packed_________ = _metile_bounded_thread + 288;\n int _metile_register_index_________ = int((((_metile_register_packed_________ >> 5) & 1u) << 0) | (((_metile_register_packed_________ >> 6) & 1u) << 1) | (((_metile_register_packed_________ >> 0) & 1u) << 2) | (((_metile_register_packed_________ >> 1) & 1u) << 3) | (((_metile_register_packed_________ >> 2) & 1u) << 4) | (((_metile_register_packed_________ >> 3) & 1u) << 5) | (((_metile_register_packed_________ >> 4) & 1u) << 6) | (((_metile_register_packed_________ >> 7) & 1u) << 7) | (((_metile_register_packed_________ >> 8) & 1u) << 8) | (((_metile_register_packed_________ >> 9) & 1u) << 9));\n int _metile_register_packed__________ = _metile_bounded_thread + 320;\n int _metile_register_index__________ = int((((_metile_register_packed__________ >> 5) & 1u) << 0) | (((_metile_register_packed__________ >> 6) & 1u) << 1) | (((_metile_register_packed__________ >> 0) & 1u) << 2) | (((_metile_register_packed__________ >> 1) & 1u) << 3) | (((_metile_register_packed__________ >> 2) & 1u) << 4) | (((_metile_register_packed__________ >> 3) & 1u) << 5) | (((_metile_register_packed__________ >> 4) & 1u) << 6) | (((_metile_register_packed__________ >> 7) & 1u) << 7) | (((_metile_register_packed__________ >> 8) & 1u) << 8) | (((_metile_register_packed__________ >> 9) & 1u) << 9));\n int _metile_register_packed___________ = _metile_bounded_thread + 352;\n int _metile_register_index___________ = int((((_metile_register_packed___________ >> 5) & 1u) << 0) | (((_metile_register_packed___________ >> 6) & 1u) << 1) | (((_metile_register_packed___________ >> 0) & 1u) << 2) | (((_metile_register_packed___________ >> 1) & 1u) << 3) | (((_metile_register_packed___________ >> 2) & 1u) << 4) | (((_metile_register_packed___________ >> 3) & 1u) << 5) | (((_metile_register_packed___________ >> 4) & 1u) << 6) | (((_metile_register_packed___________ >> 7) & 1u) << 7) | (((_metile_register_packed___________ >> 8) & 1u) << 8) | (((_metile_register_packed___________ >> 9) & 1u) << 9));\n int _metile_register_packed____________ = _metile_bounded_thread + 384;\n int _metile_register_index____________ = int((((_metile_register_packed____________ >> 5) & 1u) << 0) | (((_metile_register_packed____________ >> 6) & 1u) << 1) | (((_metile_register_packed____________ >> 0) & 1u) << 2) | (((_metile_register_packed____________ >> 1) & 1u) << 3) | (((_metile_register_packed____________ >> 2) & 1u) << 4) | (((_metile_register_packed____________ >> 3) & 1u) << 5) | (((_metile_register_packed____________ >> 4) & 1u) << 6) | (((_metile_register_packed____________ >> 7) & 1u) << 7) | (((_metile_register_packed____________ >> 8) & 1u) << 8) | (((_metile_register_packed____________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________ = _metile_bounded_thread + 416;\n int _metile_register_index_____________ = int((((_metile_register_packed_____________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________ >> 9) & 1u) << 9));\n int _metile_register_packed______________ = _metile_bounded_thread + 448;\n int _metile_register_index______________ = int((((_metile_register_packed______________ >> 5) & 1u) << 0) | (((_metile_register_packed______________ >> 6) & 1u) << 1) | (((_metile_register_packed______________ >> 0) & 1u) << 2) | (((_metile_register_packed______________ >> 1) & 1u) << 3) | (((_metile_register_packed______________ >> 2) & 1u) << 4) | (((_metile_register_packed______________ >> 3) & 1u) << 5) | (((_metile_register_packed______________ >> 4) & 1u) << 6) | (((_metile_register_packed______________ >> 7) & 1u) << 7) | (((_metile_register_packed______________ >> 8) & 1u) << 8) | (((_metile_register_packed______________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________ = _metile_bounded_thread + 480;\n int _metile_register_index_______________ = int((((_metile_register_packed_______________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________ >> 9) & 1u) << 9));\n int _metile_register_packed________________ = _metile_bounded_thread + 512;\n int _metile_register_index________________ = int((((_metile_register_packed________________ >> 5) & 1u) << 0) | (((_metile_register_packed________________ >> 6) & 1u) << 1) | (((_metile_register_packed________________ >> 0) & 1u) << 2) | (((_metile_register_packed________________ >> 1) & 1u) << 3) | (((_metile_register_packed________________ >> 2) & 1u) << 4) | (((_metile_register_packed________________ >> 3) & 1u) << 5) | (((_metile_register_packed________________ >> 4) & 1u) << 6) | (((_metile_register_packed________________ >> 7) & 1u) << 7) | (((_metile_register_packed________________ >> 8) & 1u) << 8) | (((_metile_register_packed________________ >> 9) & 1u) << 9));\n int _metile_register_packed_________________ = _metile_bounded_thread + 544;\n int _metile_register_index_________________ = int((((_metile_register_packed_________________ >> 5) & 1u) << 0) | (((_metile_register_packed_________________ >> 6) & 1u) << 1) | (((_metile_register_packed_________________ >> 0) & 1u) << 2) | (((_metile_register_packed_________________ >> 1) & 1u) << 3) | (((_metile_register_packed_________________ >> 2) & 1u) << 4) | (((_metile_register_packed_________________ >> 3) & 1u) << 5) | (((_metile_register_packed_________________ >> 4) & 1u) << 6) | (((_metile_register_packed_________________ >> 7) & 1u) << 7) | (((_metile_register_packed_________________ >> 8) & 1u) << 8) | (((_metile_register_packed_________________ >> 9) & 1u) << 9));\n int _metile_register_packed__________________ = _metile_bounded_thread + 576;\n int _metile_register_index__________________ = int((((_metile_register_packed__________________ >> 5) & 1u) << 0) | (((_metile_register_packed__________________ >> 6) & 1u) << 1) | (((_metile_register_packed__________________ >> 0) & 1u) << 2) | (((_metile_register_packed__________________ >> 1) & 1u) << 3) | (((_metile_register_packed__________________ >> 2) & 1u) << 4) | (((_metile_register_packed__________________ >> 3) & 1u) << 5) | (((_metile_register_packed__________________ >> 4) & 1u) << 6) | (((_metile_register_packed__________________ >> 7) & 1u) << 7) | (((_metile_register_packed__________________ >> 8) & 1u) << 8) | (((_metile_register_packed__________________ >> 9) & 1u) << 9));\n int _metile_register_packed___________________ = _metile_bounded_thread + 608;\n int _metile_register_index___________________ = int((((_metile_register_packed___________________ >> 5) & 1u) << 0) | (((_metile_register_packed___________________ >> 6) & 1u) << 1) | (((_metile_register_packed___________________ >> 0) & 1u) << 2) | (((_metile_register_packed___________________ >> 1) & 1u) << 3) | (((_metile_register_packed___________________ >> 2) & 1u) << 4) | (((_metile_register_packed___________________ >> 3) & 1u) << 5) | (((_metile_register_packed___________________ >> 4) & 1u) << 6) | (((_metile_register_packed___________________ >> 7) & 1u) << 7) | (((_metile_register_packed___________________ >> 8) & 1u) << 8) | (((_metile_register_packed___________________ >> 9) & 1u) << 9));\n int _metile_register_packed____________________ = _metile_bounded_thread + 640;\n int _metile_register_index____________________ = int((((_metile_register_packed____________________ >> 5) & 1u) << 0) | (((_metile_register_packed____________________ >> 6) & 1u) << 1) | (((_metile_register_packed____________________ >> 0) & 1u) << 2) | (((_metile_register_packed____________________ >> 1) & 1u) << 3) | (((_metile_register_packed____________________ >> 2) & 1u) << 4) | (((_metile_register_packed____________________ >> 3) & 1u) << 5) | (((_metile_register_packed____________________ >> 4) & 1u) << 6) | (((_metile_register_packed____________________ >> 7) & 1u) << 7) | (((_metile_register_packed____________________ >> 8) & 1u) << 8) | (((_metile_register_packed____________________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________________ = _metile_bounded_thread + 672;\n int _metile_register_index_____________________ = int((((_metile_register_packed_____________________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________________ >> 9) & 1u) << 9));\n int _metile_register_packed______________________ = _metile_bounded_thread + 704;\n int _metile_register_index______________________ = int((((_metile_register_packed______________________ >> 5) & 1u) << 0) | (((_metile_register_packed______________________ >> 6) & 1u) << 1) | (((_metile_register_packed______________________ >> 0) & 1u) << 2) | (((_metile_register_packed______________________ >> 1) & 1u) << 3) | (((_metile_register_packed______________________ >> 2) & 1u) << 4) | (((_metile_register_packed______________________ >> 3) & 1u) << 5) | (((_metile_register_packed______________________ >> 4) & 1u) << 6) | (((_metile_register_packed______________________ >> 7) & 1u) << 7) | (((_metile_register_packed______________________ >> 8) & 1u) << 8) | (((_metile_register_packed______________________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________________ = _metile_bounded_thread + 736;\n int _metile_register_index_______________________ = int((((_metile_register_packed_______________________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________________ >> 9) & 1u) << 9));\n int _metile_register_packed________________________ = _metile_bounded_thread + 768;\n int _metile_register_index________________________ = int((((_metile_register_packed________________________ >> 5) & 1u) << 0) | (((_metile_register_packed________________________ >> 6) & 1u) << 1) | (((_metile_register_packed________________________ >> 0) & 1u) << 2) | (((_metile_register_packed________________________ >> 1) & 1u) << 3) | (((_metile_register_packed________________________ >> 2) & 1u) << 4) | (((_metile_register_packed________________________ >> 3) & 1u) << 5) | (((_metile_register_packed________________________ >> 4) & 1u) << 6) | (((_metile_register_packed________________________ >> 7) & 1u) << 7) | (((_metile_register_packed________________________ >> 8) & 1u) << 8) | (((_metile_register_packed________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_________________________ = _metile_bounded_thread + 800;\n int _metile_register_index_________________________ = int((((_metile_register_packed_________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_________________________ >> 9) & 1u) << 9));\n int _metile_register_packed__________________________ = _metile_bounded_thread + 832;\n int _metile_register_index__________________________ = int((((_metile_register_packed__________________________ >> 5) & 1u) << 0) | (((_metile_register_packed__________________________ >> 6) & 1u) << 1) | (((_metile_register_packed__________________________ >> 0) & 1u) << 2) | (((_metile_register_packed__________________________ >> 1) & 1u) << 3) | (((_metile_register_packed__________________________ >> 2) & 1u) << 4) | (((_metile_register_packed__________________________ >> 3) & 1u) << 5) | (((_metile_register_packed__________________________ >> 4) & 1u) << 6) | (((_metile_register_packed__________________________ >> 7) & 1u) << 7) | (((_metile_register_packed__________________________ >> 8) & 1u) << 8) | (((_metile_register_packed__________________________ >> 9) & 1u) << 9));\n int _metile_register_packed___________________________ = _metile_bounded_thread + 864;\n int _metile_register_index___________________________ = int((((_metile_register_packed___________________________ >> 5) & 1u) << 0) | (((_metile_register_packed___________________________ >> 6) & 1u) << 1) | (((_metile_register_packed___________________________ >> 0) & 1u) << 2) | (((_metile_register_packed___________________________ >> 1) & 1u) << 3) | (((_metile_register_packed___________________________ >> 2) & 1u) << 4) | (((_metile_register_packed___________________________ >> 3) & 1u) << 5) | (((_metile_register_packed___________________________ >> 4) & 1u) << 6) | (((_metile_register_packed___________________________ >> 7) & 1u) << 7) | (((_metile_register_packed___________________________ >> 8) & 1u) << 8) | (((_metile_register_packed___________________________ >> 9) & 1u) << 9));\n int _metile_register_packed____________________________ = _metile_bounded_thread + 896;\n int _metile_register_index____________________________ = int((((_metile_register_packed____________________________ >> 5) & 1u) << 0) | (((_metile_register_packed____________________________ >> 6) & 1u) << 1) | (((_metile_register_packed____________________________ >> 0) & 1u) << 2) | (((_metile_register_packed____________________________ >> 1) & 1u) << 3) | (((_metile_register_packed____________________________ >> 2) & 1u) << 4) | (((_metile_register_packed____________________________ >> 3) & 1u) << 5) | (((_metile_register_packed____________________________ >> 4) & 1u) << 6) | (((_metile_register_packed____________________________ >> 7) & 1u) << 7) | (((_metile_register_packed____________________________ >> 8) & 1u) << 8) | (((_metile_register_packed____________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________________________ = _metile_bounded_thread + 928;\n int _metile_register_index_____________________________ = int((((_metile_register_packed_____________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________________________ >> 9) & 1u) << 9));\n int _metile_register_packed______________________________ = _metile_bounded_thread + 960;\n int _metile_register_index______________________________ = int((((_metile_register_packed______________________________ >> 5) & 1u) << 0) | (((_metile_register_packed______________________________ >> 6) & 1u) << 1) | (((_metile_register_packed______________________________ >> 0) & 1u) << 2) | (((_metile_register_packed______________________________ >> 1) & 1u) << 3) | (((_metile_register_packed______________________________ >> 2) & 1u) << 4) | (((_metile_register_packed______________________________ >> 3) & 1u) << 5) | (((_metile_register_packed______________________________ >> 4) & 1u) << 6) | (((_metile_register_packed______________________________ >> 7) & 1u) << 7) | (((_metile_register_packed______________________________ >> 8) & 1u) << 8) | (((_metile_register_packed______________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________________________ = _metile_bounded_thread + 992;\n int _metile_register_index_______________________________ = int((((_metile_register_packed_______________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________________________ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v16_r16 = _metile_register_index________________ >= 0;\n bool _metile_v16_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v16_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v16_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v16_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v16_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v16_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v16_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v16_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v16_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v16_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v16_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v16_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v16_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v16_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v16_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v17_r8 = _metile_register_index________ < 1024;\n bool _metile_v17_r9 = _metile_register_index_________ < 1024;\n bool _metile_v17_r10 = _metile_register_index__________ < 1024;\n bool _metile_v17_r11 = _metile_register_index___________ < 1024;\n bool _metile_v17_r12 = _metile_register_index____________ < 1024;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v17_r14 = _metile_register_index______________ < 1024;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v17_r16 = _metile_register_index________________ < 1024;\n bool _metile_v17_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v17_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v17_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v17_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v17_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v17_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v17_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v17_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v17_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v17_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v17_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v17_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v17_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v17_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v17_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n bool _metile_v18_r16 = _metile_v16_r16 & _metile_v17_r16;\n bool _metile_v18_r17 = _metile_v16_r17 & _metile_v17_r17;\n bool _metile_v18_r18 = _metile_v16_r18 & _metile_v17_r18;\n bool _metile_v18_r19 = _metile_v16_r19 & _metile_v17_r19;\n bool _metile_v18_r20 = _metile_v16_r20 & _metile_v17_r20;\n bool _metile_v18_r21 = _metile_v16_r21 & _metile_v17_r21;\n bool _metile_v18_r22 = _metile_v16_r22 & _metile_v17_r22;\n bool _metile_v18_r23 = _metile_v16_r23 & _metile_v17_r23;\n bool _metile_v18_r24 = _metile_v16_r24 & _metile_v17_r24;\n bool _metile_v18_r25 = _metile_v16_r25 & _metile_v17_r25;\n bool _metile_v18_r26 = _metile_v16_r26 & _metile_v17_r26;\n bool _metile_v18_r27 = _metile_v16_r27 & _metile_v17_r27;\n bool _metile_v18_r28 = _metile_v16_r28 & _metile_v17_r28;\n bool _metile_v18_r29 = _metile_v16_r29 & _metile_v17_r29;\n bool _metile_v18_r30 = _metile_v16_r30 & _metile_v17_r30;\n bool _metile_v18_r31 = _metile_v16_r31 & _metile_v17_r31;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n int _off__metile_v19_r16 = v2 + _metile_register_index________________;\n int _off__metile_v19_r17 = v2 + _metile_register_index_________________;\n int _off__metile_v19_r18 = v2 + _metile_register_index__________________;\n int _off__metile_v19_r19 = v2 + _metile_register_index___________________;\n int _off__metile_v19_r20 = v2 + _metile_register_index____________________;\n int _off__metile_v19_r21 = v2 + _metile_register_index_____________________;\n int _off__metile_v19_r22 = v2 + _metile_register_index______________________;\n int _off__metile_v19_r23 = v2 + _metile_register_index_______________________;\n int _off__metile_v19_r24 = v2 + _metile_register_index________________________;\n int _off__metile_v19_r25 = v2 + _metile_register_index_________________________;\n int _off__metile_v19_r26 = v2 + _metile_register_index__________________________;\n int _off__metile_v19_r27 = v2 + _metile_register_index___________________________;\n int _off__metile_v19_r28 = v2 + _metile_register_index____________________________;\n int _off__metile_v19_r29 = v2 + _metile_register_index_____________________________;\n int _off__metile_v19_r30 = v2 + _metile_register_index______________________________;\n int _off__metile_v19_r31 = v2 + _metile_register_index_______________________________;\n half4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = half4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n half _metile_v20_r0 = _metile_vector_load[0];\n half _metile_v20_r1 = _metile_vector_load[1];\n half _metile_v20_r2 = _metile_vector_load[2];\n half _metile_v20_r3 = _metile_vector_load[3];\n half4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = half4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n half _metile_v20_r4 = _metile_vector_load_[0];\n half _metile_v20_r5 = _metile_vector_load_[1];\n half _metile_v20_r6 = _metile_vector_load_[2];\n half _metile_v20_r7 = _metile_vector_load_[3];\n half4 _metile_vector_load__;\n if ((_metile_v18_r8) && (_metile_v18_r9) && (_metile_v18_r10) && (_metile_v18_r11) && (long(_off__metile_v19_r9) == long(_off__metile_v19_r8) + 1) && (long(_off__metile_v19_r10) == long(_off__metile_v19_r8) + 2) && (long(_off__metile_v19_r11) == long(_off__metile_v19_r8) + 3)) {\n _metile_vector_load__ = half4(*reinterpret_cast(X + _off__metile_v19_r8));\n } else {\n _metile_vector_load__[0] = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n _metile_vector_load__[1] = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n _metile_vector_load__[2] = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n _metile_vector_load__[3] = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n }\n half _metile_v20_r8 = _metile_vector_load__[0];\n half _metile_v20_r9 = _metile_vector_load__[1];\n half _metile_v20_r10 = _metile_vector_load__[2];\n half _metile_v20_r11 = _metile_vector_load__[3];\n half4 _metile_vector_load___;\n if ((_metile_v18_r12) && (_metile_v18_r13) && (_metile_v18_r14) && (_metile_v18_r15) && (long(_off__metile_v19_r13) == long(_off__metile_v19_r12) + 1) && (long(_off__metile_v19_r14) == long(_off__metile_v19_r12) + 2) && (long(_off__metile_v19_r15) == long(_off__metile_v19_r12) + 3)) {\n _metile_vector_load___ = half4(*reinterpret_cast(X + _off__metile_v19_r12));\n } else {\n _metile_vector_load___[0] = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n _metile_vector_load___[1] = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n _metile_vector_load___[2] = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n _metile_vector_load___[3] = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n }\n half _metile_v20_r12 = _metile_vector_load___[0];\n half _metile_v20_r13 = _metile_vector_load___[1];\n half _metile_v20_r14 = _metile_vector_load___[2];\n half _metile_v20_r15 = _metile_vector_load___[3];\n half4 _metile_vector_load____;\n if ((_metile_v18_r16) && (_metile_v18_r17) && (_metile_v18_r18) && (_metile_v18_r19) && (long(_off__metile_v19_r17) == long(_off__metile_v19_r16) + 1) && (long(_off__metile_v19_r18) == long(_off__metile_v19_r16) + 2) && (long(_off__metile_v19_r19) == long(_off__metile_v19_r16) + 3)) {\n _metile_vector_load____ = half4(*reinterpret_cast(X + _off__metile_v19_r16));\n } else {\n _metile_vector_load____[0] = _metile_v18_r16 ? X[_off__metile_v19_r16] : static_cast(0);\n _metile_vector_load____[1] = _metile_v18_r17 ? X[_off__metile_v19_r17] : static_cast(0);\n _metile_vector_load____[2] = _metile_v18_r18 ? X[_off__metile_v19_r18] : static_cast(0);\n _metile_vector_load____[3] = _metile_v18_r19 ? X[_off__metile_v19_r19] : static_cast(0);\n }\n half _metile_v20_r16 = _metile_vector_load____[0];\n half _metile_v20_r17 = _metile_vector_load____[1];\n half _metile_v20_r18 = _metile_vector_load____[2];\n half _metile_v20_r19 = _metile_vector_load____[3];\n half4 _metile_vector_load_____;\n if ((_metile_v18_r20) && (_metile_v18_r21) && (_metile_v18_r22) && (_metile_v18_r23) && (long(_off__metile_v19_r21) == long(_off__metile_v19_r20) + 1) && (long(_off__metile_v19_r22) == long(_off__metile_v19_r20) + 2) && (long(_off__metile_v19_r23) == long(_off__metile_v19_r20) + 3)) {\n _metile_vector_load_____ = half4(*reinterpret_cast(X + _off__metile_v19_r20));\n } else {\n _metile_vector_load_____[0] = _metile_v18_r20 ? X[_off__metile_v19_r20] : static_cast(0);\n _metile_vector_load_____[1] = _metile_v18_r21 ? X[_off__metile_v19_r21] : static_cast(0);\n _metile_vector_load_____[2] = _metile_v18_r22 ? X[_off__metile_v19_r22] : static_cast(0);\n _metile_vector_load_____[3] = _metile_v18_r23 ? X[_off__metile_v19_r23] : static_cast(0);\n }\n half _metile_v20_r20 = _metile_vector_load_____[0];\n half _metile_v20_r21 = _metile_vector_load_____[1];\n half _metile_v20_r22 = _metile_vector_load_____[2];\n half _metile_v20_r23 = _metile_vector_load_____[3];\n half4 _metile_vector_load______;\n if ((_metile_v18_r24) && (_metile_v18_r25) && (_metile_v18_r26) && (_metile_v18_r27) && (long(_off__metile_v19_r25) == long(_off__metile_v19_r24) + 1) && (long(_off__metile_v19_r26) == long(_off__metile_v19_r24) + 2) && (long(_off__metile_v19_r27) == long(_off__metile_v19_r24) + 3)) {\n _metile_vector_load______ = half4(*reinterpret_cast(X + _off__metile_v19_r24));\n } else {\n _metile_vector_load______[0] = _metile_v18_r24 ? X[_off__metile_v19_r24] : static_cast(0);\n _metile_vector_load______[1] = _metile_v18_r25 ? X[_off__metile_v19_r25] : static_cast(0);\n _metile_vector_load______[2] = _metile_v18_r26 ? X[_off__metile_v19_r26] : static_cast(0);\n _metile_vector_load______[3] = _metile_v18_r27 ? X[_off__metile_v19_r27] : static_cast(0);\n }\n half _metile_v20_r24 = _metile_vector_load______[0];\n half _metile_v20_r25 = _metile_vector_load______[1];\n half _metile_v20_r26 = _metile_vector_load______[2];\n half _metile_v20_r27 = _metile_vector_load______[3];\n half4 _metile_vector_load_______;\n if ((_metile_v18_r28) && (_metile_v18_r29) && (_metile_v18_r30) && (_metile_v18_r31) && (long(_off__metile_v19_r29) == long(_off__metile_v19_r28) + 1) && (long(_off__metile_v19_r30) == long(_off__metile_v19_r28) + 2) && (long(_off__metile_v19_r31) == long(_off__metile_v19_r28) + 3)) {\n _metile_vector_load_______ = half4(*reinterpret_cast(X + _off__metile_v19_r28));\n } else {\n _metile_vector_load_______[0] = _metile_v18_r28 ? X[_off__metile_v19_r28] : static_cast(0);\n _metile_vector_load_______[1] = _metile_v18_r29 ? X[_off__metile_v19_r29] : static_cast(0);\n _metile_vector_load_______[2] = _metile_v18_r30 ? X[_off__metile_v19_r30] : static_cast(0);\n _metile_vector_load_______[3] = _metile_v18_r31 ? X[_off__metile_v19_r31] : static_cast(0);\n }\n half _metile_v20_r28 = _metile_vector_load_______[0];\n half _metile_v20_r29 = _metile_vector_load_______[1];\n half _metile_v20_r30 = _metile_vector_load_______[2];\n half _metile_v20_r31 = _metile_vector_load_______[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v21_r16 = static_cast(_metile_v20_r16);\n float _metile_v21_r17 = static_cast(_metile_v20_r17);\n float _metile_v21_r18 = static_cast(_metile_v20_r18);\n float _metile_v21_r19 = static_cast(_metile_v20_r19);\n float _metile_v21_r20 = static_cast(_metile_v20_r20);\n float _metile_v21_r21 = static_cast(_metile_v20_r21);\n float _metile_v21_r22 = static_cast(_metile_v20_r22);\n float _metile_v21_r23 = static_cast(_metile_v20_r23);\n float _metile_v21_r24 = static_cast(_metile_v20_r24);\n float _metile_v21_r25 = static_cast(_metile_v20_r25);\n float _metile_v21_r26 = static_cast(_metile_v20_r26);\n float _metile_v21_r27 = static_cast(_metile_v20_r27);\n float _metile_v21_r28 = static_cast(_metile_v20_r28);\n float _metile_v21_r29 = static_cast(_metile_v20_r29);\n float _metile_v21_r30 = static_cast(_metile_v20_r30);\n float _metile_v21_r31 = static_cast(_metile_v20_r31);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_v22_r16 = _metile_v21_r16 * _metile_v21_r16;\n float _metile_v22_r17 = _metile_v21_r17 * _metile_v21_r17;\n float _metile_v22_r18 = _metile_v21_r18 * _metile_v21_r18;\n float _metile_v22_r19 = _metile_v21_r19 * _metile_v21_r19;\n float _metile_v22_r20 = _metile_v21_r20 * _metile_v21_r20;\n float _metile_v22_r21 = _metile_v21_r21 * _metile_v21_r21;\n float _metile_v22_r22 = _metile_v21_r22 * _metile_v21_r22;\n float _metile_v22_r23 = _metile_v21_r23 * _metile_v21_r23;\n float _metile_v22_r24 = _metile_v21_r24 * _metile_v21_r24;\n float _metile_v22_r25 = _metile_v21_r25 * _metile_v21_r25;\n float _metile_v22_r26 = _metile_v21_r26 * _metile_v21_r26;\n float _metile_v22_r27 = _metile_v21_r27 * _metile_v21_r27;\n float _metile_v22_r28 = _metile_v21_r28 * _metile_v21_r28;\n float _metile_v22_r29 = _metile_v21_r29 * _metile_v21_r29;\n float _metile_v22_r30 = _metile_v21_r30 * _metile_v21_r30;\n float _metile_v22_r31 = _metile_v21_r31 * _metile_v21_r31;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_v22_r16 + _metile_v22_r17;\n float _metile_register_sum_________ = _metile_v22_r18 + _metile_v22_r19;\n float _metile_register_sum__________ = _metile_v22_r20 + _metile_v22_r21;\n float _metile_register_sum___________ = _metile_v22_r22 + _metile_v22_r23;\n float _metile_register_sum____________ = _metile_v22_r24 + _metile_v22_r25;\n float _metile_register_sum_____________ = _metile_v22_r26 + _metile_v22_r27;\n float _metile_register_sum______________ = _metile_v22_r28 + _metile_v22_r29;\n float _metile_register_sum_______________ = _metile_v22_r30 + _metile_v22_r31;\n float _metile_register_sum________________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________________ = _metile_register_sum____________ + _metile_register_sum_____________;\n float _metile_register_sum_______________________ = _metile_register_sum______________ + _metile_register_sum_______________;\n float _metile_register_sum________________________ = _metile_register_sum________________ + _metile_register_sum_________________;\n float _metile_register_sum_________________________ = _metile_register_sum__________________ + _metile_register_sum___________________;\n float _metile_register_sum__________________________ = _metile_register_sum____________________ + _metile_register_sum_____________________;\n float _metile_register_sum___________________________ = _metile_register_sum______________________ + _metile_register_sum_______________________;\n float _metile_register_sum____________________________ = _metile_register_sum________________________ + _metile_register_sum_________________________;\n float _metile_register_sum_____________________________ = _metile_register_sum__________________________ + _metile_register_sum___________________________;\n float _metile_register_sum______________________________ = _metile_register_sum____________________________ + _metile_register_sum_____________________________;\n float v23 = simd_sum(_metile_register_sum______________________________);\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v32_r16 = _metile_register_index________________ >= 0;\n bool _metile_v32_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v32_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v32_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v32_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v32_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v32_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v32_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v32_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v32_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v32_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v32_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v32_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v32_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v32_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v32_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v33_r8 = _metile_register_index________ < 1024;\n bool _metile_v33_r9 = _metile_register_index_________ < 1024;\n bool _metile_v33_r10 = _metile_register_index__________ < 1024;\n bool _metile_v33_r11 = _metile_register_index___________ < 1024;\n bool _metile_v33_r12 = _metile_register_index____________ < 1024;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v33_r14 = _metile_register_index______________ < 1024;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v33_r16 = _metile_register_index________________ < 1024;\n bool _metile_v33_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v33_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v33_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v33_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v33_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v33_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v33_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v33_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v33_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v33_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v33_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v33_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v33_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v33_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v33_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n bool _metile_v34_r16 = _metile_v32_r16 & _metile_v33_r16;\n bool _metile_v34_r17 = _metile_v32_r17 & _metile_v33_r17;\n bool _metile_v34_r18 = _metile_v32_r18 & _metile_v33_r18;\n bool _metile_v34_r19 = _metile_v32_r19 & _metile_v33_r19;\n bool _metile_v34_r20 = _metile_v32_r20 & _metile_v33_r20;\n bool _metile_v34_r21 = _metile_v32_r21 & _metile_v33_r21;\n bool _metile_v34_r22 = _metile_v32_r22 & _metile_v33_r22;\n bool _metile_v34_r23 = _metile_v32_r23 & _metile_v33_r23;\n bool _metile_v34_r24 = _metile_v32_r24 & _metile_v33_r24;\n bool _metile_v34_r25 = _metile_v32_r25 & _metile_v33_r25;\n bool _metile_v34_r26 = _metile_v32_r26 & _metile_v33_r26;\n bool _metile_v34_r27 = _metile_v32_r27 & _metile_v33_r27;\n bool _metile_v34_r28 = _metile_v32_r28 & _metile_v33_r28;\n bool _metile_v34_r29 = _metile_v32_r29 & _metile_v33_r29;\n bool _metile_v34_r30 = _metile_v32_r30 & _metile_v33_r30;\n bool _metile_v34_r31 = _metile_v32_r31 & _metile_v33_r31;\n half4 _metile_vector_load________;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load________ = half4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load________[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load________[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load________[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load________[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n half _metile_v36_r0 = _metile_vector_load________[0];\n half _metile_v36_r1 = _metile_vector_load________[1];\n half _metile_v36_r2 = _metile_vector_load________[2];\n half _metile_v36_r3 = _metile_vector_load________[3];\n half4 _metile_vector_load_________;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load_________ = half4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load_________[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load_________[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load_________[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load_________[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n half _metile_v36_r4 = _metile_vector_load_________[0];\n half _metile_v36_r5 = _metile_vector_load_________[1];\n half _metile_v36_r6 = _metile_vector_load_________[2];\n half _metile_v36_r7 = _metile_vector_load_________[3];\n half4 _metile_vector_load__________;\n if ((_metile_v34_r8) && (_metile_v34_r9) && (_metile_v34_r10) && (_metile_v34_r11) && (long(_metile_register_index_________) == long(_metile_register_index________) + 1) && (long(_metile_register_index__________) == long(_metile_register_index________) + 2) && (long(_metile_register_index___________) == long(_metile_register_index________) + 3)) {\n _metile_vector_load__________ = half4(*reinterpret_cast(W + _metile_register_index________));\n } else {\n _metile_vector_load__________[0] = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n _metile_vector_load__________[1] = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n _metile_vector_load__________[2] = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n _metile_vector_load__________[3] = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n }\n half _metile_v36_r8 = _metile_vector_load__________[0];\n half _metile_v36_r9 = _metile_vector_load__________[1];\n half _metile_v36_r10 = _metile_vector_load__________[2];\n half _metile_v36_r11 = _metile_vector_load__________[3];\n half4 _metile_vector_load___________;\n if ((_metile_v34_r12) && (_metile_v34_r13) && (_metile_v34_r14) && (_metile_v34_r15) && (long(_metile_register_index_____________) == long(_metile_register_index____________) + 1) && (long(_metile_register_index______________) == long(_metile_register_index____________) + 2) && (long(_metile_register_index_______________) == long(_metile_register_index____________) + 3)) {\n _metile_vector_load___________ = half4(*reinterpret_cast(W + _metile_register_index____________));\n } else {\n _metile_vector_load___________[0] = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n _metile_vector_load___________[1] = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n _metile_vector_load___________[2] = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n _metile_vector_load___________[3] = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n }\n half _metile_v36_r12 = _metile_vector_load___________[0];\n half _metile_v36_r13 = _metile_vector_load___________[1];\n half _metile_v36_r14 = _metile_vector_load___________[2];\n half _metile_v36_r15 = _metile_vector_load___________[3];\n half4 _metile_vector_load____________;\n if ((_metile_v34_r16) && (_metile_v34_r17) && (_metile_v34_r18) && (_metile_v34_r19) && (long(_metile_register_index_________________) == long(_metile_register_index________________) + 1) && (long(_metile_register_index__________________) == long(_metile_register_index________________) + 2) && (long(_metile_register_index___________________) == long(_metile_register_index________________) + 3)) {\n _metile_vector_load____________ = half4(*reinterpret_cast(W + _metile_register_index________________));\n } else {\n _metile_vector_load____________[0] = _metile_v34_r16 ? W[_metile_register_index________________] : static_cast(0);\n _metile_vector_load____________[1] = _metile_v34_r17 ? W[_metile_register_index_________________] : static_cast(0);\n _metile_vector_load____________[2] = _metile_v34_r18 ? W[_metile_register_index__________________] : static_cast(0);\n _metile_vector_load____________[3] = _metile_v34_r19 ? W[_metile_register_index___________________] : static_cast(0);\n }\n half _metile_v36_r16 = _metile_vector_load____________[0];\n half _metile_v36_r17 = _metile_vector_load____________[1];\n half _metile_v36_r18 = _metile_vector_load____________[2];\n half _metile_v36_r19 = _metile_vector_load____________[3];\n half4 _metile_vector_load_____________;\n if ((_metile_v34_r20) && (_metile_v34_r21) && (_metile_v34_r22) && (_metile_v34_r23) && (long(_metile_register_index_____________________) == long(_metile_register_index____________________) + 1) && (long(_metile_register_index______________________) == long(_metile_register_index____________________) + 2) && (long(_metile_register_index_______________________) == long(_metile_register_index____________________) + 3)) {\n _metile_vector_load_____________ = half4(*reinterpret_cast(W + _metile_register_index____________________));\n } else {\n _metile_vector_load_____________[0] = _metile_v34_r20 ? W[_metile_register_index____________________] : static_cast(0);\n _metile_vector_load_____________[1] = _metile_v34_r21 ? W[_metile_register_index_____________________] : static_cast(0);\n _metile_vector_load_____________[2] = _metile_v34_r22 ? W[_metile_register_index______________________] : static_cast(0);\n _metile_vector_load_____________[3] = _metile_v34_r23 ? W[_metile_register_index_______________________] : static_cast(0);\n }\n half _metile_v36_r20 = _metile_vector_load_____________[0];\n half _metile_v36_r21 = _metile_vector_load_____________[1];\n half _metile_v36_r22 = _metile_vector_load_____________[2];\n half _metile_v36_r23 = _metile_vector_load_____________[3];\n half4 _metile_vector_load______________;\n if ((_metile_v34_r24) && (_metile_v34_r25) && (_metile_v34_r26) && (_metile_v34_r27) && (long(_metile_register_index_________________________) == long(_metile_register_index________________________) + 1) && (long(_metile_register_index__________________________) == long(_metile_register_index________________________) + 2) && (long(_metile_register_index___________________________) == long(_metile_register_index________________________) + 3)) {\n _metile_vector_load______________ = half4(*reinterpret_cast(W + _metile_register_index________________________));\n } else {\n _metile_vector_load______________[0] = _metile_v34_r24 ? W[_metile_register_index________________________] : static_cast(0);\n _metile_vector_load______________[1] = _metile_v34_r25 ? W[_metile_register_index_________________________] : static_cast(0);\n _metile_vector_load______________[2] = _metile_v34_r26 ? W[_metile_register_index__________________________] : static_cast(0);\n _metile_vector_load______________[3] = _metile_v34_r27 ? W[_metile_register_index___________________________] : static_cast(0);\n }\n half _metile_v36_r24 = _metile_vector_load______________[0];\n half _metile_v36_r25 = _metile_vector_load______________[1];\n half _metile_v36_r26 = _metile_vector_load______________[2];\n half _metile_v36_r27 = _metile_vector_load______________[3];\n half4 _metile_vector_load_______________;\n if ((_metile_v34_r28) && (_metile_v34_r29) && (_metile_v34_r30) && (_metile_v34_r31) && (long(_metile_register_index_____________________________) == long(_metile_register_index____________________________) + 1) && (long(_metile_register_index______________________________) == long(_metile_register_index____________________________) + 2) && (long(_metile_register_index_______________________________) == long(_metile_register_index____________________________) + 3)) {\n _metile_vector_load_______________ = half4(*reinterpret_cast(W + _metile_register_index____________________________));\n } else {\n _metile_vector_load_______________[0] = _metile_v34_r28 ? W[_metile_register_index____________________________] : static_cast(0);\n _metile_vector_load_______________[1] = _metile_v34_r29 ? W[_metile_register_index_____________________________] : static_cast(0);\n _metile_vector_load_______________[2] = _metile_v34_r30 ? W[_metile_register_index______________________________] : static_cast(0);\n _metile_vector_load_______________[3] = _metile_v34_r31 ? W[_metile_register_index_______________________________] : static_cast(0);\n }\n half _metile_v36_r28 = _metile_vector_load_______________[0];\n half _metile_v36_r29 = _metile_vector_load_______________[1];\n half _metile_v36_r30 = _metile_vector_load_______________[2];\n half _metile_v36_r31 = _metile_vector_load_______________[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v37_r16 = static_cast(_metile_v36_r16);\n float _metile_v37_r17 = static_cast(_metile_v36_r17);\n float _metile_v37_r18 = static_cast(_metile_v36_r18);\n float _metile_v37_r19 = static_cast(_metile_v36_r19);\n float _metile_v37_r20 = static_cast(_metile_v36_r20);\n float _metile_v37_r21 = static_cast(_metile_v36_r21);\n float _metile_v37_r22 = static_cast(_metile_v36_r22);\n float _metile_v37_r23 = static_cast(_metile_v36_r23);\n float _metile_v37_r24 = static_cast(_metile_v36_r24);\n float _metile_v37_r25 = static_cast(_metile_v36_r25);\n float _metile_v37_r26 = static_cast(_metile_v36_r26);\n float _metile_v37_r27 = static_cast(_metile_v36_r27);\n float _metile_v37_r28 = static_cast(_metile_v36_r28);\n float _metile_v37_r29 = static_cast(_metile_v36_r29);\n float _metile_v37_r30 = static_cast(_metile_v36_r30);\n float _metile_v37_r31 = static_cast(_metile_v36_r31);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v38_r16 = _metile_v21_r16 * v29;\n float _metile_v38_r17 = _metile_v21_r17 * v29;\n float _metile_v38_r18 = _metile_v21_r18 * v29;\n float _metile_v38_r19 = _metile_v21_r19 * v29;\n float _metile_v38_r20 = _metile_v21_r20 * v29;\n float _metile_v38_r21 = _metile_v21_r21 * v29;\n float _metile_v38_r22 = _metile_v21_r22 * v29;\n float _metile_v38_r23 = _metile_v21_r23 * v29;\n float _metile_v38_r24 = _metile_v21_r24 * v29;\n float _metile_v38_r25 = _metile_v21_r25 * v29;\n float _metile_v38_r26 = _metile_v21_r26 * v29;\n float _metile_v38_r27 = _metile_v21_r27 * v29;\n float _metile_v38_r28 = _metile_v21_r28 * v29;\n float _metile_v38_r29 = _metile_v21_r29 * v29;\n float _metile_v38_r30 = _metile_v21_r30 * v29;\n float _metile_v38_r31 = _metile_v21_r31 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n float _metile_v39_r16 = _metile_v38_r16 * _metile_v37_r16;\n float _metile_v39_r17 = _metile_v38_r17 * _metile_v37_r17;\n float _metile_v39_r18 = _metile_v38_r18 * _metile_v37_r18;\n float _metile_v39_r19 = _metile_v38_r19 * _metile_v37_r19;\n float _metile_v39_r20 = _metile_v38_r20 * _metile_v37_r20;\n float _metile_v39_r21 = _metile_v38_r21 * _metile_v37_r21;\n float _metile_v39_r22 = _metile_v38_r22 * _metile_v37_r22;\n float _metile_v39_r23 = _metile_v38_r23 * _metile_v37_r23;\n float _metile_v39_r24 = _metile_v38_r24 * _metile_v37_r24;\n float _metile_v39_r25 = _metile_v38_r25 * _metile_v37_r25;\n float _metile_v39_r26 = _metile_v38_r26 * _metile_v37_r26;\n float _metile_v39_r27 = _metile_v38_r27 * _metile_v37_r27;\n float _metile_v39_r28 = _metile_v38_r28 * _metile_v37_r28;\n float _metile_v39_r29 = _metile_v38_r29 * _metile_v37_r29;\n float _metile_v39_r30 = _metile_v38_r30 * _metile_v37_r30;\n float _metile_v39_r31 = _metile_v38_r31 * _metile_v37_r31;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v41_r16 = _metile_register_index________________ >= 0;\n bool _metile_v41_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v41_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v41_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v41_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v41_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v41_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v41_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v41_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v41_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v41_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v41_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v41_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v41_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v41_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v41_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v42_r8 = _metile_register_index________ < 1024;\n bool _metile_v42_r9 = _metile_register_index_________ < 1024;\n bool _metile_v42_r10 = _metile_register_index__________ < 1024;\n bool _metile_v42_r11 = _metile_register_index___________ < 1024;\n bool _metile_v42_r12 = _metile_register_index____________ < 1024;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v42_r14 = _metile_register_index______________ < 1024;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v42_r16 = _metile_register_index________________ < 1024;\n bool _metile_v42_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v42_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v42_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v42_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v42_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v42_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v42_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v42_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v42_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v42_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v42_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v42_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v42_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v42_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v42_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n bool _metile_v43_r16 = _metile_v41_r16 & _metile_v42_r16;\n bool _metile_v43_r17 = _metile_v41_r17 & _metile_v42_r17;\n bool _metile_v43_r18 = _metile_v41_r18 & _metile_v42_r18;\n bool _metile_v43_r19 = _metile_v41_r19 & _metile_v42_r19;\n bool _metile_v43_r20 = _metile_v41_r20 & _metile_v42_r20;\n bool _metile_v43_r21 = _metile_v41_r21 & _metile_v42_r21;\n bool _metile_v43_r22 = _metile_v41_r22 & _metile_v42_r22;\n bool _metile_v43_r23 = _metile_v41_r23 & _metile_v42_r23;\n bool _metile_v43_r24 = _metile_v41_r24 & _metile_v42_r24;\n bool _metile_v43_r25 = _metile_v41_r25 & _metile_v42_r25;\n bool _metile_v43_r26 = _metile_v41_r26 & _metile_v42_r26;\n bool _metile_v43_r27 = _metile_v41_r27 & _metile_v42_r27;\n bool _metile_v43_r28 = _metile_v41_r28 & _metile_v42_r28;\n bool _metile_v43_r29 = _metile_v41_r29 & _metile_v42_r29;\n bool _metile_v43_r30 = _metile_v41_r30 & _metile_v42_r30;\n bool _metile_v43_r31 = _metile_v41_r31 & _metile_v42_r31;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n int _off__metile_v44_r16 = v9 + _metile_register_index________________;\n int _off__metile_v44_r17 = v9 + _metile_register_index_________________;\n int _off__metile_v44_r18 = v9 + _metile_register_index__________________;\n int _off__metile_v44_r19 = v9 + _metile_register_index___________________;\n int _off__metile_v44_r20 = v9 + _metile_register_index____________________;\n int _off__metile_v44_r21 = v9 + _metile_register_index_____________________;\n int _off__metile_v44_r22 = v9 + _metile_register_index______________________;\n int _off__metile_v44_r23 = v9 + _metile_register_index_______________________;\n int _off__metile_v44_r24 = v9 + _metile_register_index________________________;\n int _off__metile_v44_r25 = v9 + _metile_register_index_________________________;\n int _off__metile_v44_r26 = v9 + _metile_register_index__________________________;\n int _off__metile_v44_r27 = v9 + _metile_register_index___________________________;\n int _off__metile_v44_r28 = v9 + _metile_register_index____________________________;\n int _off__metile_v44_r29 = v9 + _metile_register_index_____________________________;\n int _off__metile_v44_r30 = v9 + _metile_register_index______________________________;\n int _off__metile_v44_r31 = v9 + _metile_register_index_______________________________;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_half4(half4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_half4(half4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n if ((_metile_v43_r8) && (_metile_v43_r9) && (_metile_v43_r10) && (_metile_v43_r11) && (long(_off__metile_v44_r9) == long(_off__metile_v44_r8) + 1) && (long(_off__metile_v44_r10) == long(_off__metile_v44_r8) + 2) && (long(_off__metile_v44_r11) == long(_off__metile_v44_r8) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r8) = packed_half4(half4(static_cast(_metile_v39_r8), static_cast(_metile_v39_r9), static_cast(_metile_v39_r10), static_cast(_metile_v39_r11)));\n } else {\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = static_cast(_metile_v39_r8); }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = static_cast(_metile_v39_r9); }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = static_cast(_metile_v39_r10); }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = static_cast(_metile_v39_r11); }\n }\n if ((_metile_v43_r12) && (_metile_v43_r13) && (_metile_v43_r14) && (_metile_v43_r15) && (long(_off__metile_v44_r13) == long(_off__metile_v44_r12) + 1) && (long(_off__metile_v44_r14) == long(_off__metile_v44_r12) + 2) && (long(_off__metile_v44_r15) == long(_off__metile_v44_r12) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r12) = packed_half4(half4(static_cast(_metile_v39_r12), static_cast(_metile_v39_r13), static_cast(_metile_v39_r14), static_cast(_metile_v39_r15)));\n } else {\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = static_cast(_metile_v39_r12); }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = static_cast(_metile_v39_r13); }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = static_cast(_metile_v39_r14); }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = static_cast(_metile_v39_r15); }\n }\n if ((_metile_v43_r16) && (_metile_v43_r17) && (_metile_v43_r18) && (_metile_v43_r19) && (long(_off__metile_v44_r17) == long(_off__metile_v44_r16) + 1) && (long(_off__metile_v44_r18) == long(_off__metile_v44_r16) + 2) && (long(_off__metile_v44_r19) == long(_off__metile_v44_r16) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r16) = packed_half4(half4(static_cast(_metile_v39_r16), static_cast(_metile_v39_r17), static_cast(_metile_v39_r18), static_cast(_metile_v39_r19)));\n } else {\n if (_metile_v43_r16) { Out[_off__metile_v44_r16] = static_cast(_metile_v39_r16); }\n if (_metile_v43_r17) { Out[_off__metile_v44_r17] = static_cast(_metile_v39_r17); }\n if (_metile_v43_r18) { Out[_off__metile_v44_r18] = static_cast(_metile_v39_r18); }\n if (_metile_v43_r19) { Out[_off__metile_v44_r19] = static_cast(_metile_v39_r19); }\n }\n if ((_metile_v43_r20) && (_metile_v43_r21) && (_metile_v43_r22) && (_metile_v43_r23) && (long(_off__metile_v44_r21) == long(_off__metile_v44_r20) + 1) && (long(_off__metile_v44_r22) == long(_off__metile_v44_r20) + 2) && (long(_off__metile_v44_r23) == long(_off__metile_v44_r20) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r20) = packed_half4(half4(static_cast(_metile_v39_r20), static_cast(_metile_v39_r21), static_cast(_metile_v39_r22), static_cast(_metile_v39_r23)));\n } else {\n if (_metile_v43_r20) { Out[_off__metile_v44_r20] = static_cast(_metile_v39_r20); }\n if (_metile_v43_r21) { Out[_off__metile_v44_r21] = static_cast(_metile_v39_r21); }\n if (_metile_v43_r22) { Out[_off__metile_v44_r22] = static_cast(_metile_v39_r22); }\n if (_metile_v43_r23) { Out[_off__metile_v44_r23] = static_cast(_metile_v39_r23); }\n }\n if ((_metile_v43_r24) && (_metile_v43_r25) && (_metile_v43_r26) && (_metile_v43_r27) && (long(_off__metile_v44_r25) == long(_off__metile_v44_r24) + 1) && (long(_off__metile_v44_r26) == long(_off__metile_v44_r24) + 2) && (long(_off__metile_v44_r27) == long(_off__metile_v44_r24) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r24) = packed_half4(half4(static_cast(_metile_v39_r24), static_cast(_metile_v39_r25), static_cast(_metile_v39_r26), static_cast(_metile_v39_r27)));\n } else {\n if (_metile_v43_r24) { Out[_off__metile_v44_r24] = static_cast(_metile_v39_r24); }\n if (_metile_v43_r25) { Out[_off__metile_v44_r25] = static_cast(_metile_v39_r25); }\n if (_metile_v43_r26) { Out[_off__metile_v44_r26] = static_cast(_metile_v39_r26); }\n if (_metile_v43_r27) { Out[_off__metile_v44_r27] = static_cast(_metile_v39_r27); }\n }\n if ((_metile_v43_r28) && (_metile_v43_r29) && (_metile_v43_r30) && (_metile_v43_r31) && (long(_off__metile_v44_r29) == long(_off__metile_v44_r28) + 1) && (long(_off__metile_v44_r30) == long(_off__metile_v44_r28) + 2) && (long(_off__metile_v44_r31) == long(_off__metile_v44_r28) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r28) = packed_half4(half4(static_cast(_metile_v39_r28), static_cast(_metile_v39_r29), static_cast(_metile_v39_r30), static_cast(_metile_v39_r31)));\n } else {\n if (_metile_v43_r28) { Out[_off__metile_v44_r28] = static_cast(_metile_v39_r28); }\n if (_metile_v43_r29) { Out[_off__metile_v44_r29] = static_cast(_metile_v39_r29); }\n if (_metile_v43_r30) { Out[_off__metile_v44_r30] = static_cast(_metile_v39_r30); }\n if (_metile_v43_r31) { Out[_off__metile_v44_r31] = static_cast(_metile_v39_r31); }\n }\n}", "source_sha256": "e71f6e91f3f76564671db8d5ee10d9f8eb51e2c1e61e3c1f613552152e99fce6", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 32, 1, 1 ], "is_gemm": false, "prefer_ordered": false, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 32, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 32 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [], "double_buffered": false, "vectorized_loads": 16, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 32, "threads": 32, "scratch": null, "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 16, "grouped_stores": 8 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 589, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 210.208, "control": 204.0, "speedup": 0.9704673466281017 }, "gpu_us": { "candidate": 5.9166341088712215, "control": 4.9166264943778515, "speedup": 0.8309836984859367 } } }, { "frozen_register4": { "pairs": 589, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 208.375, "control": 203.833, "speedup": 0.9782027594481104 }, "gpu_us": { "candidate": 5.916692316532135, "control": 4.958303179591894, "speedup": 0.8380194396348182 } } }, { "frozen_register4": { "pairs": 569, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 208.208, "control": 205.458, "speedup": 0.9867920540997464 }, "gpu_us": { "candidate": 5.916692316532135, "control": 4.916684702038765, "speedup": 0.8309853612466551 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.978464675837666, "round_speedups": [ 0.9704673466281017, 0.9782027594481104, 0.9867920540997464 ], "candidate": 208.92837278379042, "control": 204.4290325491824 }, "gpu_us": { "speedup": 0.8333229134247624, "round_speedups": [ 0.8309836984859367, 0.8380194396348182, 0.8309853612466551 ], "candidate": 5.91667291391487, "control": 4.930499110404918 } } } }, { "name": "float16_256x1024", "dtype": "float16", "batches": 256, "width": 1024, "status": "measured", "variant": { "name": "register2_striped", "elements_per_thread": 2, "layout": "striped" }, "input_sha256": "fcaf7de00cd83d1d1e75063d1ab252906b9f1076e1f1c8a88d773ec19ed2a30c", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 511;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 512;\n int _metile_register_index_ = int(_metile_register_packed_);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n threadgroup float _metile_register_reduction[16];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 16u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n}", "source_sha256": "7904a94ae16a9a4d931c40f756c878c87106b2c4dc49872d49e6df50e4e1317d", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 512, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 512, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 2 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 16, "bytes": 64 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 2, "threads": 512, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 577, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 205.292, "control": 207.166, "speedup": 1.0091284609239521 }, "gpu_us": { "candidate": 4.875008016824722, "control": 4.958303179591894, "speedup": 1.0170861591364981 } } }, { "frozen_register4": { "pairs": 560, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 208.188, "control": 207.72899999999998, "speedup": 0.9977952619747535 }, "gpu_us": { "candidate": 4.875008016824722, "control": 4.958361387252808, "speedup": 1.017098099149871 } } }, { "frozen_register4": { "pairs": 521, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 203.584, "control": 207.166, "speedup": 1.017594702923609 }, "gpu_us": { "candidate": 4.875008016824722, "control": 4.958361387252808, "speedup": 1.017098099149871 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0081401471096765, "round_speedups": [ 1.0091284609239521, 0.9977952619747535, 1.017594702923609 ], "candidate": 205.67923766815412, "control": 207.35349692017905 }, "gpu_us": { "speedup": 1.017094119129839, "round_speedups": [ 1.0170861591364981, 1.017098099149871, 1.017098099149871 ], "candidate": 4.875008016824721, "control": 4.958341984623245 } } } }, { "name": "float16_256x1024", "dtype": "float16", "batches": 256, "width": 1024, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "fcaf7de00cd83d1d1e75063d1ab252906b9f1076e1f1c8a88d773ec19ed2a30c", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "a30e8c10d04f7806837b7362bac4a0f599f0d6d17735fc2e88198ca5dcb4e73d", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 585, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 206.125, "control": 206.083, "speedup": 0.9997962401455427 }, "gpu_us": { "candidate": 4.583329427987337, "control": 4.958361387252808, "speedup": 1.081825224470098 } } }, { "frozen_register4": { "pairs": 588, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.9375, "control": 205.52100000000002, "speedup": 1.0127305204804435 }, "gpu_us": { "candidate": 4.583329427987337, "control": 4.999979864805937, "speedup": 1.0909056273097877 } } }, { "frozen_register4": { "pairs": 467, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 207.625, "control": 210.75, "speedup": 1.0150511739915713 }, "gpu_us": { "candidate": 4.583329427987337, "control": 4.999979864805937, "speedup": 1.0909056273097877 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0091702638928766, "round_speedups": [ 0.9997962401455427, 1.0127305204804435, 1.0150511739915713 ], "candidate": 205.55318321611526, "control": 207.43816015022787 }, "gpu_us": { "speedup": 1.087870389220857, "round_speedups": [ 1.081825224470098, 1.0909056273097877, 1.0909056273097877 ], "candidate": 4.583329427987338, "control": 4.986068368751993 } } } }, { "name": "float16_256x1024", "dtype": "float16", "batches": 256, "width": 1024, "status": "measured", "variant": { "name": "register4_blocked4", "elements_per_thread": 4, "layout": "blocked4" }, "input_sha256": "fcaf7de00cd83d1d1e75063d1ab252906b9f1076e1f1c8a88d773ec19ed2a30c", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int((((_metile_bounded_thread >> 8) & 1u) << 0) | (((_metile_bounded_thread >> 9) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 6) & 1u) << 8) | (((_metile_bounded_thread >> 7) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 8) & 1u) << 0) | (((_metile_register_packed_ >> 9) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 6) & 1u) << 8) | (((_metile_register_packed_ >> 7) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 8) & 1u) << 0) | (((_metile_register_packed__ >> 9) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 6) & 1u) << 8) | (((_metile_register_packed__ >> 7) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 8) & 1u) << 0) | (((_metile_register_packed___ >> 9) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 6) & 1u) << 8) | (((_metile_register_packed___ >> 7) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = half4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n half _metile_v20_r0 = _metile_vector_load[0];\n half _metile_v20_r1 = _metile_vector_load[1];\n half _metile_v20_r2 = _metile_vector_load[2];\n half _metile_v20_r3 = _metile_vector_load[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half4 _metile_vector_load_;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load_ = half4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load_[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load_[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load_[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load_[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n half _metile_v36_r0 = _metile_vector_load_[0];\n half _metile_v36_r1 = _metile_vector_load_[1];\n half _metile_v36_r2 = _metile_vector_load_[2];\n half _metile_v36_r3 = _metile_vector_load_[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_half4(half4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n}", "source_sha256": "2f5456f3b5088f163701ddb7dda6355b247755e6037315115cb7598baca96276", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 2, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 2, "grouped_stores": 1 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 556, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 207.58350000000002, "control": 209.208, "speedup": 1.0078257664987824 }, "gpu_us": { "candidate": 4.999979864805937, "control": 4.958361387252808, "speedup": 0.9916762709693943 } } }, { "frozen_register4": { "pairs": 590, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 205.4795, "control": 205.437, "speedup": 0.9997931667149278 }, "gpu_us": { "candidate": 4.999979864805937, "control": 4.958303179591894, "speedup": 0.9916646293903305 } } }, { "frozen_register4": { "pairs": 593, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 203.25, "control": 204.959, "speedup": 1.0084083640836408 }, "gpu_us": { "candidate": 4.999979864805937, "control": 4.958303179591894, "speedup": 0.9916646293903305 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.005334732627653, "round_speedups": [ 1.0078257664987824, 0.9997931667149278, 1.0084083640836408 ], "candidate": 205.43004513627554, "control": 206.5259595007643 }, "gpu_us": { "speedup": 0.9916685099015001, "round_speedups": [ 0.9916762709693943, 0.9916646293903305, 0.9916646293903305 ], "candidate": 4.999979864805936, "control": 4.958322582069608 } } } }, { "name": "float16_256x1024", "dtype": "float16", "batches": 256, "width": 1024, "status": "measured", "variant": { "name": "register8_striped", "elements_per_thread": 8, "layout": "striped" }, "input_sha256": "fcaf7de00cd83d1d1e75063d1ab252906b9f1076e1f1c8a88d773ec19ed2a30c", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 127;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 128;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 256;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 384;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 512;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 640;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 768;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 896;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n half _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n half _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n half _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n half _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_____ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum______ = _metile_register_sum____ + _metile_register_sum_____;\n threadgroup float _metile_register_reduction[4];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 4u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n half _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n half _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n half _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n half _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n}", "source_sha256": "c52eee1a22cd9b99c0ecec2256f602f592be4c6e60d377eb925a553835a7a584", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 128, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 128, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 8 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 4, "bytes": 16 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 8, "threads": 128, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 591, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.708, "control": 205.625, "speedup": 1.004479551360963 }, "gpu_us": { "candidate": 4.583329427987337, "control": 4.958303179591894, "speedup": 1.0818125246059866 } } }, { "frozen_register4": { "pairs": 587, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 206.667, "control": 205.833, "speedup": 0.9959645226378667 }, "gpu_us": { "candidate": 4.583329427987337, "control": 4.958303179591894, "speedup": 1.0818125246059866 } } }, { "frozen_register4": { "pairs": 590, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 206.0625, "control": 205.10399999999998, "speedup": 0.9953484986351228 }, "gpu_us": { "candidate": 4.583329427987337, "control": 4.958303179591894, "speedup": 1.0818125246059866 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9985888475791509, "round_speedups": [ 1.004479551360963, 0.9959645226378667, 0.9953484986351228 ], "candidate": 205.81086833742197, "control": 205.52043783233046 }, "gpu_us": { "speedup": 1.0818125246059866, "round_speedups": [ 1.0818125246059866, 1.0818125246059866, 1.0818125246059866 ], "candidate": 4.583329427987338, "control": 4.958303179591894 } } } }, { "name": "float16_256x1024", "dtype": "float16", "batches": 256, "width": 1024, "status": "measured", "variant": { "name": "register8_blocked4", "elements_per_thread": 8, "layout": "blocked4" }, "input_sha256": "fcaf7de00cd83d1d1e75063d1ab252906b9f1076e1f1c8a88d773ec19ed2a30c", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 127;\n int _metile_register_index = int((((_metile_bounded_thread >> 7) & 1u) << 0) | (((_metile_bounded_thread >> 8) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 6) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 128;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 7) & 1u) << 0) | (((_metile_register_packed_ >> 8) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 6) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 256;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 7) & 1u) << 0) | (((_metile_register_packed__ >> 8) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 6) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 384;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 7) & 1u) << 0) | (((_metile_register_packed___ >> 8) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 6) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 512;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 7) & 1u) << 0) | (((_metile_register_packed____ >> 8) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 5) & 1u) << 7) | (((_metile_register_packed____ >> 6) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 640;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 7) & 1u) << 0) | (((_metile_register_packed_____ >> 8) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 5) & 1u) << 7) | (((_metile_register_packed_____ >> 6) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 768;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 7) & 1u) << 0) | (((_metile_register_packed______ >> 8) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 5) & 1u) << 7) | (((_metile_register_packed______ >> 6) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 896;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 7) & 1u) << 0) | (((_metile_register_packed_______ >> 8) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 5) & 1u) << 7) | (((_metile_register_packed_______ >> 6) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n half4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = half4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n half _metile_v20_r0 = _metile_vector_load[0];\n half _metile_v20_r1 = _metile_vector_load[1];\n half _metile_v20_r2 = _metile_vector_load[2];\n half _metile_v20_r3 = _metile_vector_load[3];\n half4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = half4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n half _metile_v20_r4 = _metile_vector_load_[0];\n half _metile_v20_r5 = _metile_vector_load_[1];\n half _metile_v20_r6 = _metile_vector_load_[2];\n half _metile_v20_r7 = _metile_vector_load_[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_____ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum______ = _metile_register_sum____ + _metile_register_sum_____;\n threadgroup float _metile_register_reduction[4];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 4u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n half4 _metile_vector_load__;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load__ = half4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load__[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load__[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load__[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load__[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n half _metile_v36_r0 = _metile_vector_load__[0];\n half _metile_v36_r1 = _metile_vector_load__[1];\n half _metile_v36_r2 = _metile_vector_load__[2];\n half _metile_v36_r3 = _metile_vector_load__[3];\n half4 _metile_vector_load___;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load___ = half4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load___[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load___[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load___[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load___[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n half _metile_v36_r4 = _metile_vector_load___[0];\n half _metile_v36_r5 = _metile_vector_load___[1];\n half _metile_v36_r6 = _metile_vector_load___[2];\n half _metile_v36_r7 = _metile_vector_load___[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_half4(half4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_half4(half4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n}", "source_sha256": "0795515dc02028985d5e8efef00cea1dcab53425817a6bcfdff5ade2f974789f", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 128, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 128, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 8 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 4, "bytes": 16 } ], "double_buffered": false, "vectorized_loads": 4, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 8, "threads": 128, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 4, "grouped_stores": 2 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 590, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 205.20850000000002, "control": 204.33350000000002, "speedup": 0.9957360440722485 }, "gpu_us": { "candidate": 5.20836329087615, "control": 4.875008016824722, "speedup": 0.9359961555225248 } } }, { "frozen_register4": { "pairs": 580, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 206.20850000000002, "control": 204.125, "speedup": 0.9898961488008495 }, "gpu_us": { "candidate": 5.249981768429279, "control": 4.916684702038765, "speedup": 0.9365146240326407 } } }, { "frozen_register4": { "pairs": 528, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 205.666, "control": 206.792, "speedup": 1.0054748961909115 }, "gpu_us": { "candidate": 5.249981768429279, "control": 4.958361387252808, "speedup": 0.944453067831563 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9970150137423429, "round_speedups": [ 0.9957360440722485, 0.9898961488008495, 1.0054748961909115 ], "candidate": 205.69392728071256, "control": 205.07993373449602 }, "gpu_us": { "speedup": 0.9389799884422328, "round_speedups": [ 0.9359961555225248, 0.9365146240326407, 0.944453067831563 ], "candidate": 5.236072121994637, "control": 4.916566940593223 } } } }, { "name": "float16_256x1024", "dtype": "float16", "batches": 256, "width": 1024, "status": "measured", "variant": { "name": "register16_striped", "elements_per_thread": 16, "layout": "striped" }, "input_sha256": "fcaf7de00cd83d1d1e75063d1ab252906b9f1076e1f1c8a88d773ec19ed2a30c", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 63;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 64;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 128;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 192;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 256;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 320;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 384;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 448;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n int _metile_register_packed________ = _metile_bounded_thread + 512;\n int _metile_register_index________ = int(_metile_register_packed________);\n int _metile_register_packed_________ = _metile_bounded_thread + 576;\n int _metile_register_index_________ = int(_metile_register_packed_________);\n int _metile_register_packed__________ = _metile_bounded_thread + 640;\n int _metile_register_index__________ = int(_metile_register_packed__________);\n int _metile_register_packed___________ = _metile_bounded_thread + 704;\n int _metile_register_index___________ = int(_metile_register_packed___________);\n int _metile_register_packed____________ = _metile_bounded_thread + 768;\n int _metile_register_index____________ = int(_metile_register_packed____________);\n int _metile_register_packed_____________ = _metile_bounded_thread + 832;\n int _metile_register_index_____________ = int(_metile_register_packed_____________);\n int _metile_register_packed______________ = _metile_bounded_thread + 896;\n int _metile_register_index______________ = int(_metile_register_packed______________);\n int _metile_register_packed_______________ = _metile_bounded_thread + 960;\n int _metile_register_index_______________ = int(_metile_register_packed_______________);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v17_r8 = _metile_register_index________ < 1024;\n bool _metile_v17_r9 = _metile_register_index_________ < 1024;\n bool _metile_v17_r10 = _metile_register_index__________ < 1024;\n bool _metile_v17_r11 = _metile_register_index___________ < 1024;\n bool _metile_v17_r12 = _metile_register_index____________ < 1024;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v17_r14 = _metile_register_index______________ < 1024;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n half _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n half _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n half _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n half _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n half _metile_v20_r8 = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n half _metile_v20_r9 = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n half _metile_v20_r10 = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n half _metile_v20_r11 = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n half _metile_v20_r12 = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n half _metile_v20_r13 = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n half _metile_v20_r14 = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n half _metile_v20_r15 = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________ = _metile_register_sum____________ + _metile_register_sum_____________;\n threadgroup float _metile_register_reduction[2];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______________);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 2u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v33_r8 = _metile_register_index________ < 1024;\n bool _metile_v33_r9 = _metile_register_index_________ < 1024;\n bool _metile_v33_r10 = _metile_register_index__________ < 1024;\n bool _metile_v33_r11 = _metile_register_index___________ < 1024;\n bool _metile_v33_r12 = _metile_register_index____________ < 1024;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v33_r14 = _metile_register_index______________ < 1024;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n half _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n half _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n half _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n half _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n half _metile_v36_r8 = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n half _metile_v36_r9 = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n half _metile_v36_r10 = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n half _metile_v36_r11 = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n half _metile_v36_r12 = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n half _metile_v36_r13 = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n half _metile_v36_r14 = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n half _metile_v36_r15 = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v42_r8 = _metile_register_index________ < 1024;\n bool _metile_v42_r9 = _metile_register_index_________ < 1024;\n bool _metile_v42_r10 = _metile_register_index__________ < 1024;\n bool _metile_v42_r11 = _metile_register_index___________ < 1024;\n bool _metile_v42_r12 = _metile_register_index____________ < 1024;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v42_r14 = _metile_register_index______________ < 1024;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = _metile_v39_r8; }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = _metile_v39_r9; }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = _metile_v39_r10; }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = _metile_v39_r11; }\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = _metile_v39_r12; }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = _metile_v39_r13; }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = _metile_v39_r14; }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = _metile_v39_r15; }\n}", "source_sha256": "80e4ab993c9dda4e9764e5d0ae2ad910cd88a101c3d4ec77af99d486d6933bdb", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 64, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 64, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 16 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 2, "bytes": 8 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 16, "threads": 64, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 514, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 216.97899999999998, "control": 214.5, "speedup": 0.9885749312145415 }, "gpu_us": { "candidate": 4.750036168843508, "control": 5.249981768429279, "speedup": 1.105250903743643 } } }, { "frozen_register4": { "pairs": 577, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 206.75, "control": 203.583, "speedup": 0.9846819830713422 }, "gpu_us": { "candidate": 4.62500611320138, "control": 4.958303179591894, "speedup": 1.072064135318474 } } }, { "frozen_register4": { "pairs": 577, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 206.125, "control": 204.042, "speedup": 0.9898944815039418 }, "gpu_us": { "candidate": 4.62500611320138, "control": 4.958303179591894, "speedup": 1.072064135318474 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9877146514095448, "round_speedups": [ 0.9885749312145415, 0.9846819830713422, 0.9898944815039418 ], "candidate": 209.8930040773685, "control": 207.31439535558005 }, "gpu_us": { "speedup": 1.0830141673617844, "round_speedups": [ 1.105250903743643, 1.072064135318474, 1.072064135318474 ], "candidate": 4.666312783641053, "control": 5.053682854024664 } } } }, { "name": "float32_1x1009", "dtype": "float32", "batches": 1, "width": 1009, "status": "measured", "variant": { "name": "register32_striped", "elements_per_thread": 32, "layout": "striped" }, "input_sha256": "72c4fd9244d1e3fe8e922e59cd98ff745af158f79bcd15c587482eb6749d4442", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 4.76837158203125e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 31;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 32;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 64;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 96;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 128;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 160;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 192;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 224;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n int _metile_register_packed________ = _metile_bounded_thread + 256;\n int _metile_register_index________ = int(_metile_register_packed________);\n int _metile_register_packed_________ = _metile_bounded_thread + 288;\n int _metile_register_index_________ = int(_metile_register_packed_________);\n int _metile_register_packed__________ = _metile_bounded_thread + 320;\n int _metile_register_index__________ = int(_metile_register_packed__________);\n int _metile_register_packed___________ = _metile_bounded_thread + 352;\n int _metile_register_index___________ = int(_metile_register_packed___________);\n int _metile_register_packed____________ = _metile_bounded_thread + 384;\n int _metile_register_index____________ = int(_metile_register_packed____________);\n int _metile_register_packed_____________ = _metile_bounded_thread + 416;\n int _metile_register_index_____________ = int(_metile_register_packed_____________);\n int _metile_register_packed______________ = _metile_bounded_thread + 448;\n int _metile_register_index______________ = int(_metile_register_packed______________);\n int _metile_register_packed_______________ = _metile_bounded_thread + 480;\n int _metile_register_index_______________ = int(_metile_register_packed_______________);\n int _metile_register_packed________________ = _metile_bounded_thread + 512;\n int _metile_register_index________________ = int(_metile_register_packed________________);\n int _metile_register_packed_________________ = _metile_bounded_thread + 544;\n int _metile_register_index_________________ = int(_metile_register_packed_________________);\n int _metile_register_packed__________________ = _metile_bounded_thread + 576;\n int _metile_register_index__________________ = int(_metile_register_packed__________________);\n int _metile_register_packed___________________ = _metile_bounded_thread + 608;\n int _metile_register_index___________________ = int(_metile_register_packed___________________);\n int _metile_register_packed____________________ = _metile_bounded_thread + 640;\n int _metile_register_index____________________ = int(_metile_register_packed____________________);\n int _metile_register_packed_____________________ = _metile_bounded_thread + 672;\n int _metile_register_index_____________________ = int(_metile_register_packed_____________________);\n int _metile_register_packed______________________ = _metile_bounded_thread + 704;\n int _metile_register_index______________________ = int(_metile_register_packed______________________);\n int _metile_register_packed_______________________ = _metile_bounded_thread + 736;\n int _metile_register_index_______________________ = int(_metile_register_packed_______________________);\n int _metile_register_packed________________________ = _metile_bounded_thread + 768;\n int _metile_register_index________________________ = int(_metile_register_packed________________________);\n int _metile_register_packed_________________________ = _metile_bounded_thread + 800;\n int _metile_register_index_________________________ = int(_metile_register_packed_________________________);\n int _metile_register_packed__________________________ = _metile_bounded_thread + 832;\n int _metile_register_index__________________________ = int(_metile_register_packed__________________________);\n int _metile_register_packed___________________________ = _metile_bounded_thread + 864;\n int _metile_register_index___________________________ = int(_metile_register_packed___________________________);\n int _metile_register_packed____________________________ = _metile_bounded_thread + 896;\n int _metile_register_index____________________________ = int(_metile_register_packed____________________________);\n int _metile_register_packed_____________________________ = _metile_bounded_thread + 928;\n int _metile_register_index_____________________________ = int(_metile_register_packed_____________________________);\n int _metile_register_packed______________________________ = _metile_bounded_thread + 960;\n int _metile_register_index______________________________ = int(_metile_register_packed______________________________);\n int _metile_register_packed_______________________________ = _metile_bounded_thread + 992;\n int _metile_register_index_______________________________ = int(_metile_register_packed_______________________________);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v16_r16 = _metile_register_index________________ >= 0;\n bool _metile_v16_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v16_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v16_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v16_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v16_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v16_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v16_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v16_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v16_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v16_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v16_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v16_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v16_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v16_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v16_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v17_r8 = _metile_register_index________ < 1009;\n bool _metile_v17_r9 = _metile_register_index_________ < 1009;\n bool _metile_v17_r10 = _metile_register_index__________ < 1009;\n bool _metile_v17_r11 = _metile_register_index___________ < 1009;\n bool _metile_v17_r12 = _metile_register_index____________ < 1009;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v17_r14 = _metile_register_index______________ < 1009;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v17_r16 = _metile_register_index________________ < 1009;\n bool _metile_v17_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v17_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v17_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v17_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v17_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v17_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v17_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v17_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v17_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v17_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v17_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v17_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v17_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v17_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v17_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n bool _metile_v18_r16 = _metile_v16_r16 & _metile_v17_r16;\n bool _metile_v18_r17 = _metile_v16_r17 & _metile_v17_r17;\n bool _metile_v18_r18 = _metile_v16_r18 & _metile_v17_r18;\n bool _metile_v18_r19 = _metile_v16_r19 & _metile_v17_r19;\n bool _metile_v18_r20 = _metile_v16_r20 & _metile_v17_r20;\n bool _metile_v18_r21 = _metile_v16_r21 & _metile_v17_r21;\n bool _metile_v18_r22 = _metile_v16_r22 & _metile_v17_r22;\n bool _metile_v18_r23 = _metile_v16_r23 & _metile_v17_r23;\n bool _metile_v18_r24 = _metile_v16_r24 & _metile_v17_r24;\n bool _metile_v18_r25 = _metile_v16_r25 & _metile_v17_r25;\n bool _metile_v18_r26 = _metile_v16_r26 & _metile_v17_r26;\n bool _metile_v18_r27 = _metile_v16_r27 & _metile_v17_r27;\n bool _metile_v18_r28 = _metile_v16_r28 & _metile_v17_r28;\n bool _metile_v18_r29 = _metile_v16_r29 & _metile_v17_r29;\n bool _metile_v18_r30 = _metile_v16_r30 & _metile_v17_r30;\n bool _metile_v18_r31 = _metile_v16_r31 & _metile_v17_r31;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n int _off__metile_v19_r16 = v2 + _metile_register_index________________;\n int _off__metile_v19_r17 = v2 + _metile_register_index_________________;\n int _off__metile_v19_r18 = v2 + _metile_register_index__________________;\n int _off__metile_v19_r19 = v2 + _metile_register_index___________________;\n int _off__metile_v19_r20 = v2 + _metile_register_index____________________;\n int _off__metile_v19_r21 = v2 + _metile_register_index_____________________;\n int _off__metile_v19_r22 = v2 + _metile_register_index______________________;\n int _off__metile_v19_r23 = v2 + _metile_register_index_______________________;\n int _off__metile_v19_r24 = v2 + _metile_register_index________________________;\n int _off__metile_v19_r25 = v2 + _metile_register_index_________________________;\n int _off__metile_v19_r26 = v2 + _metile_register_index__________________________;\n int _off__metile_v19_r27 = v2 + _metile_register_index___________________________;\n int _off__metile_v19_r28 = v2 + _metile_register_index____________________________;\n int _off__metile_v19_r29 = v2 + _metile_register_index_____________________________;\n int _off__metile_v19_r30 = v2 + _metile_register_index______________________________;\n int _off__metile_v19_r31 = v2 + _metile_register_index_______________________________;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n float _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n float _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n float _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n float _metile_v20_r8 = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n float _metile_v20_r9 = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n float _metile_v20_r10 = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n float _metile_v20_r11 = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n float _metile_v20_r12 = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n float _metile_v20_r13 = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n float _metile_v20_r14 = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n float _metile_v20_r15 = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n float _metile_v20_r16 = _metile_v18_r16 ? X[_off__metile_v19_r16] : static_cast(0);\n float _metile_v20_r17 = _metile_v18_r17 ? X[_off__metile_v19_r17] : static_cast(0);\n float _metile_v20_r18 = _metile_v18_r18 ? X[_off__metile_v19_r18] : static_cast(0);\n float _metile_v20_r19 = _metile_v18_r19 ? X[_off__metile_v19_r19] : static_cast(0);\n float _metile_v20_r20 = _metile_v18_r20 ? X[_off__metile_v19_r20] : static_cast(0);\n float _metile_v20_r21 = _metile_v18_r21 ? X[_off__metile_v19_r21] : static_cast(0);\n float _metile_v20_r22 = _metile_v18_r22 ? X[_off__metile_v19_r22] : static_cast(0);\n float _metile_v20_r23 = _metile_v18_r23 ? X[_off__metile_v19_r23] : static_cast(0);\n float _metile_v20_r24 = _metile_v18_r24 ? X[_off__metile_v19_r24] : static_cast(0);\n float _metile_v20_r25 = _metile_v18_r25 ? X[_off__metile_v19_r25] : static_cast(0);\n float _metile_v20_r26 = _metile_v18_r26 ? X[_off__metile_v19_r26] : static_cast(0);\n float _metile_v20_r27 = _metile_v18_r27 ? X[_off__metile_v19_r27] : static_cast(0);\n float _metile_v20_r28 = _metile_v18_r28 ? X[_off__metile_v19_r28] : static_cast(0);\n float _metile_v20_r29 = _metile_v18_r29 ? X[_off__metile_v19_r29] : static_cast(0);\n float _metile_v20_r30 = _metile_v18_r30 ? X[_off__metile_v19_r30] : static_cast(0);\n float _metile_v20_r31 = _metile_v18_r31 ? X[_off__metile_v19_r31] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v21_r16 = static_cast(_metile_v20_r16);\n float _metile_v21_r17 = static_cast(_metile_v20_r17);\n float _metile_v21_r18 = static_cast(_metile_v20_r18);\n float _metile_v21_r19 = static_cast(_metile_v20_r19);\n float _metile_v21_r20 = static_cast(_metile_v20_r20);\n float _metile_v21_r21 = static_cast(_metile_v20_r21);\n float _metile_v21_r22 = static_cast(_metile_v20_r22);\n float _metile_v21_r23 = static_cast(_metile_v20_r23);\n float _metile_v21_r24 = static_cast(_metile_v20_r24);\n float _metile_v21_r25 = static_cast(_metile_v20_r25);\n float _metile_v21_r26 = static_cast(_metile_v20_r26);\n float _metile_v21_r27 = static_cast(_metile_v20_r27);\n float _metile_v21_r28 = static_cast(_metile_v20_r28);\n float _metile_v21_r29 = static_cast(_metile_v20_r29);\n float _metile_v21_r30 = static_cast(_metile_v20_r30);\n float _metile_v21_r31 = static_cast(_metile_v20_r31);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_v22_r16 = _metile_v21_r16 * _metile_v21_r16;\n float _metile_v22_r17 = _metile_v21_r17 * _metile_v21_r17;\n float _metile_v22_r18 = _metile_v21_r18 * _metile_v21_r18;\n float _metile_v22_r19 = _metile_v21_r19 * _metile_v21_r19;\n float _metile_v22_r20 = _metile_v21_r20 * _metile_v21_r20;\n float _metile_v22_r21 = _metile_v21_r21 * _metile_v21_r21;\n float _metile_v22_r22 = _metile_v21_r22 * _metile_v21_r22;\n float _metile_v22_r23 = _metile_v21_r23 * _metile_v21_r23;\n float _metile_v22_r24 = _metile_v21_r24 * _metile_v21_r24;\n float _metile_v22_r25 = _metile_v21_r25 * _metile_v21_r25;\n float _metile_v22_r26 = _metile_v21_r26 * _metile_v21_r26;\n float _metile_v22_r27 = _metile_v21_r27 * _metile_v21_r27;\n float _metile_v22_r28 = _metile_v21_r28 * _metile_v21_r28;\n float _metile_v22_r29 = _metile_v21_r29 * _metile_v21_r29;\n float _metile_v22_r30 = _metile_v21_r30 * _metile_v21_r30;\n float _metile_v22_r31 = _metile_v21_r31 * _metile_v21_r31;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_v22_r16 + _metile_v22_r17;\n float _metile_register_sum_________ = _metile_v22_r18 + _metile_v22_r19;\n float _metile_register_sum__________ = _metile_v22_r20 + _metile_v22_r21;\n float _metile_register_sum___________ = _metile_v22_r22 + _metile_v22_r23;\n float _metile_register_sum____________ = _metile_v22_r24 + _metile_v22_r25;\n float _metile_register_sum_____________ = _metile_v22_r26 + _metile_v22_r27;\n float _metile_register_sum______________ = _metile_v22_r28 + _metile_v22_r29;\n float _metile_register_sum_______________ = _metile_v22_r30 + _metile_v22_r31;\n float _metile_register_sum________________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________________ = _metile_register_sum____________ + _metile_register_sum_____________;\n float _metile_register_sum_______________________ = _metile_register_sum______________ + _metile_register_sum_______________;\n float _metile_register_sum________________________ = _metile_register_sum________________ + _metile_register_sum_________________;\n float _metile_register_sum_________________________ = _metile_register_sum__________________ + _metile_register_sum___________________;\n float _metile_register_sum__________________________ = _metile_register_sum____________________ + _metile_register_sum_____________________;\n float _metile_register_sum___________________________ = _metile_register_sum______________________ + _metile_register_sum_______________________;\n float _metile_register_sum____________________________ = _metile_register_sum________________________ + _metile_register_sum_________________________;\n float _metile_register_sum_____________________________ = _metile_register_sum__________________________ + _metile_register_sum___________________________;\n float _metile_register_sum______________________________ = _metile_register_sum____________________________ + _metile_register_sum_____________________________;\n float v23 = simd_sum(_metile_register_sum______________________________);\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v32_r16 = _metile_register_index________________ >= 0;\n bool _metile_v32_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v32_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v32_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v32_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v32_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v32_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v32_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v32_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v32_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v32_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v32_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v32_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v32_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v32_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v32_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v33_r8 = _metile_register_index________ < 1009;\n bool _metile_v33_r9 = _metile_register_index_________ < 1009;\n bool _metile_v33_r10 = _metile_register_index__________ < 1009;\n bool _metile_v33_r11 = _metile_register_index___________ < 1009;\n bool _metile_v33_r12 = _metile_register_index____________ < 1009;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v33_r14 = _metile_register_index______________ < 1009;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v33_r16 = _metile_register_index________________ < 1009;\n bool _metile_v33_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v33_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v33_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v33_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v33_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v33_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v33_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v33_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v33_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v33_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v33_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v33_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v33_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v33_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v33_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n bool _metile_v34_r16 = _metile_v32_r16 & _metile_v33_r16;\n bool _metile_v34_r17 = _metile_v32_r17 & _metile_v33_r17;\n bool _metile_v34_r18 = _metile_v32_r18 & _metile_v33_r18;\n bool _metile_v34_r19 = _metile_v32_r19 & _metile_v33_r19;\n bool _metile_v34_r20 = _metile_v32_r20 & _metile_v33_r20;\n bool _metile_v34_r21 = _metile_v32_r21 & _metile_v33_r21;\n bool _metile_v34_r22 = _metile_v32_r22 & _metile_v33_r22;\n bool _metile_v34_r23 = _metile_v32_r23 & _metile_v33_r23;\n bool _metile_v34_r24 = _metile_v32_r24 & _metile_v33_r24;\n bool _metile_v34_r25 = _metile_v32_r25 & _metile_v33_r25;\n bool _metile_v34_r26 = _metile_v32_r26 & _metile_v33_r26;\n bool _metile_v34_r27 = _metile_v32_r27 & _metile_v33_r27;\n bool _metile_v34_r28 = _metile_v32_r28 & _metile_v33_r28;\n bool _metile_v34_r29 = _metile_v32_r29 & _metile_v33_r29;\n bool _metile_v34_r30 = _metile_v32_r30 & _metile_v33_r30;\n bool _metile_v34_r31 = _metile_v32_r31 & _metile_v33_r31;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n float _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n float _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n float _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n float _metile_v36_r8 = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n float _metile_v36_r9 = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n float _metile_v36_r10 = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n float _metile_v36_r11 = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n float _metile_v36_r12 = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n float _metile_v36_r13 = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n float _metile_v36_r14 = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n float _metile_v36_r15 = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n float _metile_v36_r16 = _metile_v34_r16 ? W[_metile_register_index________________] : static_cast(0);\n float _metile_v36_r17 = _metile_v34_r17 ? W[_metile_register_index_________________] : static_cast(0);\n float _metile_v36_r18 = _metile_v34_r18 ? W[_metile_register_index__________________] : static_cast(0);\n float _metile_v36_r19 = _metile_v34_r19 ? W[_metile_register_index___________________] : static_cast(0);\n float _metile_v36_r20 = _metile_v34_r20 ? W[_metile_register_index____________________] : static_cast(0);\n float _metile_v36_r21 = _metile_v34_r21 ? W[_metile_register_index_____________________] : static_cast(0);\n float _metile_v36_r22 = _metile_v34_r22 ? W[_metile_register_index______________________] : static_cast(0);\n float _metile_v36_r23 = _metile_v34_r23 ? W[_metile_register_index_______________________] : static_cast(0);\n float _metile_v36_r24 = _metile_v34_r24 ? W[_metile_register_index________________________] : static_cast(0);\n float _metile_v36_r25 = _metile_v34_r25 ? W[_metile_register_index_________________________] : static_cast(0);\n float _metile_v36_r26 = _metile_v34_r26 ? W[_metile_register_index__________________________] : static_cast(0);\n float _metile_v36_r27 = _metile_v34_r27 ? W[_metile_register_index___________________________] : static_cast(0);\n float _metile_v36_r28 = _metile_v34_r28 ? W[_metile_register_index____________________________] : static_cast(0);\n float _metile_v36_r29 = _metile_v34_r29 ? W[_metile_register_index_____________________________] : static_cast(0);\n float _metile_v36_r30 = _metile_v34_r30 ? W[_metile_register_index______________________________] : static_cast(0);\n float _metile_v36_r31 = _metile_v34_r31 ? W[_metile_register_index_______________________________] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v37_r16 = static_cast(_metile_v36_r16);\n float _metile_v37_r17 = static_cast(_metile_v36_r17);\n float _metile_v37_r18 = static_cast(_metile_v36_r18);\n float _metile_v37_r19 = static_cast(_metile_v36_r19);\n float _metile_v37_r20 = static_cast(_metile_v36_r20);\n float _metile_v37_r21 = static_cast(_metile_v36_r21);\n float _metile_v37_r22 = static_cast(_metile_v36_r22);\n float _metile_v37_r23 = static_cast(_metile_v36_r23);\n float _metile_v37_r24 = static_cast(_metile_v36_r24);\n float _metile_v37_r25 = static_cast(_metile_v36_r25);\n float _metile_v37_r26 = static_cast(_metile_v36_r26);\n float _metile_v37_r27 = static_cast(_metile_v36_r27);\n float _metile_v37_r28 = static_cast(_metile_v36_r28);\n float _metile_v37_r29 = static_cast(_metile_v36_r29);\n float _metile_v37_r30 = static_cast(_metile_v36_r30);\n float _metile_v37_r31 = static_cast(_metile_v36_r31);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v38_r16 = _metile_v21_r16 * v29;\n float _metile_v38_r17 = _metile_v21_r17 * v29;\n float _metile_v38_r18 = _metile_v21_r18 * v29;\n float _metile_v38_r19 = _metile_v21_r19 * v29;\n float _metile_v38_r20 = _metile_v21_r20 * v29;\n float _metile_v38_r21 = _metile_v21_r21 * v29;\n float _metile_v38_r22 = _metile_v21_r22 * v29;\n float _metile_v38_r23 = _metile_v21_r23 * v29;\n float _metile_v38_r24 = _metile_v21_r24 * v29;\n float _metile_v38_r25 = _metile_v21_r25 * v29;\n float _metile_v38_r26 = _metile_v21_r26 * v29;\n float _metile_v38_r27 = _metile_v21_r27 * v29;\n float _metile_v38_r28 = _metile_v21_r28 * v29;\n float _metile_v38_r29 = _metile_v21_r29 * v29;\n float _metile_v38_r30 = _metile_v21_r30 * v29;\n float _metile_v38_r31 = _metile_v21_r31 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n float _metile_v39_r16 = _metile_v38_r16 * _metile_v37_r16;\n float _metile_v39_r17 = _metile_v38_r17 * _metile_v37_r17;\n float _metile_v39_r18 = _metile_v38_r18 * _metile_v37_r18;\n float _metile_v39_r19 = _metile_v38_r19 * _metile_v37_r19;\n float _metile_v39_r20 = _metile_v38_r20 * _metile_v37_r20;\n float _metile_v39_r21 = _metile_v38_r21 * _metile_v37_r21;\n float _metile_v39_r22 = _metile_v38_r22 * _metile_v37_r22;\n float _metile_v39_r23 = _metile_v38_r23 * _metile_v37_r23;\n float _metile_v39_r24 = _metile_v38_r24 * _metile_v37_r24;\n float _metile_v39_r25 = _metile_v38_r25 * _metile_v37_r25;\n float _metile_v39_r26 = _metile_v38_r26 * _metile_v37_r26;\n float _metile_v39_r27 = _metile_v38_r27 * _metile_v37_r27;\n float _metile_v39_r28 = _metile_v38_r28 * _metile_v37_r28;\n float _metile_v39_r29 = _metile_v38_r29 * _metile_v37_r29;\n float _metile_v39_r30 = _metile_v38_r30 * _metile_v37_r30;\n float _metile_v39_r31 = _metile_v38_r31 * _metile_v37_r31;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v41_r16 = _metile_register_index________________ >= 0;\n bool _metile_v41_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v41_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v41_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v41_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v41_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v41_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v41_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v41_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v41_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v41_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v41_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v41_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v41_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v41_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v41_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v42_r8 = _metile_register_index________ < 1009;\n bool _metile_v42_r9 = _metile_register_index_________ < 1009;\n bool _metile_v42_r10 = _metile_register_index__________ < 1009;\n bool _metile_v42_r11 = _metile_register_index___________ < 1009;\n bool _metile_v42_r12 = _metile_register_index____________ < 1009;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v42_r14 = _metile_register_index______________ < 1009;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v42_r16 = _metile_register_index________________ < 1009;\n bool _metile_v42_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v42_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v42_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v42_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v42_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v42_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v42_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v42_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v42_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v42_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v42_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v42_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v42_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v42_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v42_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n bool _metile_v43_r16 = _metile_v41_r16 & _metile_v42_r16;\n bool _metile_v43_r17 = _metile_v41_r17 & _metile_v42_r17;\n bool _metile_v43_r18 = _metile_v41_r18 & _metile_v42_r18;\n bool _metile_v43_r19 = _metile_v41_r19 & _metile_v42_r19;\n bool _metile_v43_r20 = _metile_v41_r20 & _metile_v42_r20;\n bool _metile_v43_r21 = _metile_v41_r21 & _metile_v42_r21;\n bool _metile_v43_r22 = _metile_v41_r22 & _metile_v42_r22;\n bool _metile_v43_r23 = _metile_v41_r23 & _metile_v42_r23;\n bool _metile_v43_r24 = _metile_v41_r24 & _metile_v42_r24;\n bool _metile_v43_r25 = _metile_v41_r25 & _metile_v42_r25;\n bool _metile_v43_r26 = _metile_v41_r26 & _metile_v42_r26;\n bool _metile_v43_r27 = _metile_v41_r27 & _metile_v42_r27;\n bool _metile_v43_r28 = _metile_v41_r28 & _metile_v42_r28;\n bool _metile_v43_r29 = _metile_v41_r29 & _metile_v42_r29;\n bool _metile_v43_r30 = _metile_v41_r30 & _metile_v42_r30;\n bool _metile_v43_r31 = _metile_v41_r31 & _metile_v42_r31;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n int _off__metile_v44_r16 = v9 + _metile_register_index________________;\n int _off__metile_v44_r17 = v9 + _metile_register_index_________________;\n int _off__metile_v44_r18 = v9 + _metile_register_index__________________;\n int _off__metile_v44_r19 = v9 + _metile_register_index___________________;\n int _off__metile_v44_r20 = v9 + _metile_register_index____________________;\n int _off__metile_v44_r21 = v9 + _metile_register_index_____________________;\n int _off__metile_v44_r22 = v9 + _metile_register_index______________________;\n int _off__metile_v44_r23 = v9 + _metile_register_index_______________________;\n int _off__metile_v44_r24 = v9 + _metile_register_index________________________;\n int _off__metile_v44_r25 = v9 + _metile_register_index_________________________;\n int _off__metile_v44_r26 = v9 + _metile_register_index__________________________;\n int _off__metile_v44_r27 = v9 + _metile_register_index___________________________;\n int _off__metile_v44_r28 = v9 + _metile_register_index____________________________;\n int _off__metile_v44_r29 = v9 + _metile_register_index_____________________________;\n int _off__metile_v44_r30 = v9 + _metile_register_index______________________________;\n int _off__metile_v44_r31 = v9 + _metile_register_index_______________________________;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = _metile_v39_r8; }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = _metile_v39_r9; }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = _metile_v39_r10; }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = _metile_v39_r11; }\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = _metile_v39_r12; }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = _metile_v39_r13; }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = _metile_v39_r14; }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = _metile_v39_r15; }\n if (_metile_v43_r16) { Out[_off__metile_v44_r16] = _metile_v39_r16; }\n if (_metile_v43_r17) { Out[_off__metile_v44_r17] = _metile_v39_r17; }\n if (_metile_v43_r18) { Out[_off__metile_v44_r18] = _metile_v39_r18; }\n if (_metile_v43_r19) { Out[_off__metile_v44_r19] = _metile_v39_r19; }\n if (_metile_v43_r20) { Out[_off__metile_v44_r20] = _metile_v39_r20; }\n if (_metile_v43_r21) { Out[_off__metile_v44_r21] = _metile_v39_r21; }\n if (_metile_v43_r22) { Out[_off__metile_v44_r22] = _metile_v39_r22; }\n if (_metile_v43_r23) { Out[_off__metile_v44_r23] = _metile_v39_r23; }\n if (_metile_v43_r24) { Out[_off__metile_v44_r24] = _metile_v39_r24; }\n if (_metile_v43_r25) { Out[_off__metile_v44_r25] = _metile_v39_r25; }\n if (_metile_v43_r26) { Out[_off__metile_v44_r26] = _metile_v39_r26; }\n if (_metile_v43_r27) { Out[_off__metile_v44_r27] = _metile_v39_r27; }\n if (_metile_v43_r28) { Out[_off__metile_v44_r28] = _metile_v39_r28; }\n if (_metile_v43_r29) { Out[_off__metile_v44_r29] = _metile_v39_r29; }\n if (_metile_v43_r30) { Out[_off__metile_v44_r30] = _metile_v39_r30; }\n if (_metile_v43_r31) { Out[_off__metile_v44_r31] = _metile_v39_r31; }\n}", "source_sha256": "11365c357d8fbe48acbc6b54fb859a3d19b352b116d23e5955e6f3b1336584e2", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 32, 1, 1 ], "is_gemm": false, "prefer_ordered": false, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 32, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 32 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 32, "threads": 32, "scratch": null, "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 640, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 205.3545, "control": 203.10399999999998, "speedup": 0.98904090243944 }, "gpu_us": { "candidate": 2.20834044739604, "control": 1.708336640149355, "speedup": 0.7735839110150505 } } }, { "frozen_register4": { "pairs": 529, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 207.125, "control": 206.917, "speedup": 0.9989957754978878 }, "gpu_us": { "candidate": 2.1666637621819973, "control": 1.6666599549353123, "speedup": 0.7692287026838245 } } }, { "frozen_register4": { "pairs": 549, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.584, "control": 199.916, "speedup": 0.9966697244047381 }, "gpu_us": { "candidate": 2.3333122953772545, "control": 1.7916318029165268, "speedup": 0.7678491243825775 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9948930340454595, "round_speedups": [ 0.98904090243944, 0.9989957754978878, 0.9966697244047381 ], "candidate": 204.3357444495281, "control": 203.29220875932862 }, "gpu_us": { "speedup": 0.7702167061918362, "round_speedups": [ 0.7735839110150505, 0.7692287026838245, 0.7678491243825775 ], "candidate": 2.2349962841260695, "control": 1.721431476310575 } } } }, { "name": "float32_1x1009", "dtype": "float32", "batches": 1, "width": 1009, "status": "measured", "variant": { "name": "register32_blocked4", "elements_per_thread": 32, "layout": "blocked4" }, "input_sha256": "72c4fd9244d1e3fe8e922e59cd98ff745af158f79bcd15c587482eb6749d4442", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 4.76837158203125e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 31;\n int _metile_register_index = int((((_metile_bounded_thread >> 5) & 1u) << 0) | (((_metile_bounded_thread >> 6) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 7) & 1u) << 7) | (((_metile_bounded_thread >> 8) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 32;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 5) & 1u) << 0) | (((_metile_register_packed_ >> 6) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 7) & 1u) << 7) | (((_metile_register_packed_ >> 8) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 64;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 5) & 1u) << 0) | (((_metile_register_packed__ >> 6) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 7) & 1u) << 7) | (((_metile_register_packed__ >> 8) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 96;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 5) & 1u) << 0) | (((_metile_register_packed___ >> 6) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 7) & 1u) << 7) | (((_metile_register_packed___ >> 8) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 128;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 5) & 1u) << 0) | (((_metile_register_packed____ >> 6) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 7) & 1u) << 7) | (((_metile_register_packed____ >> 8) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 160;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 5) & 1u) << 0) | (((_metile_register_packed_____ >> 6) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 7) & 1u) << 7) | (((_metile_register_packed_____ >> 8) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 192;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 5) & 1u) << 0) | (((_metile_register_packed______ >> 6) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 7) & 1u) << 7) | (((_metile_register_packed______ >> 8) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 224;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 5) & 1u) << 0) | (((_metile_register_packed_______ >> 6) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 7) & 1u) << 7) | (((_metile_register_packed_______ >> 8) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n int _metile_register_packed________ = _metile_bounded_thread + 256;\n int _metile_register_index________ = int((((_metile_register_packed________ >> 5) & 1u) << 0) | (((_metile_register_packed________ >> 6) & 1u) << 1) | (((_metile_register_packed________ >> 0) & 1u) << 2) | (((_metile_register_packed________ >> 1) & 1u) << 3) | (((_metile_register_packed________ >> 2) & 1u) << 4) | (((_metile_register_packed________ >> 3) & 1u) << 5) | (((_metile_register_packed________ >> 4) & 1u) << 6) | (((_metile_register_packed________ >> 7) & 1u) << 7) | (((_metile_register_packed________ >> 8) & 1u) << 8) | (((_metile_register_packed________ >> 9) & 1u) << 9));\n int _metile_register_packed_________ = _metile_bounded_thread + 288;\n int _metile_register_index_________ = int((((_metile_register_packed_________ >> 5) & 1u) << 0) | (((_metile_register_packed_________ >> 6) & 1u) << 1) | (((_metile_register_packed_________ >> 0) & 1u) << 2) | (((_metile_register_packed_________ >> 1) & 1u) << 3) | (((_metile_register_packed_________ >> 2) & 1u) << 4) | (((_metile_register_packed_________ >> 3) & 1u) << 5) | (((_metile_register_packed_________ >> 4) & 1u) << 6) | (((_metile_register_packed_________ >> 7) & 1u) << 7) | (((_metile_register_packed_________ >> 8) & 1u) << 8) | (((_metile_register_packed_________ >> 9) & 1u) << 9));\n int _metile_register_packed__________ = _metile_bounded_thread + 320;\n int _metile_register_index__________ = int((((_metile_register_packed__________ >> 5) & 1u) << 0) | (((_metile_register_packed__________ >> 6) & 1u) << 1) | (((_metile_register_packed__________ >> 0) & 1u) << 2) | (((_metile_register_packed__________ >> 1) & 1u) << 3) | (((_metile_register_packed__________ >> 2) & 1u) << 4) | (((_metile_register_packed__________ >> 3) & 1u) << 5) | (((_metile_register_packed__________ >> 4) & 1u) << 6) | (((_metile_register_packed__________ >> 7) & 1u) << 7) | (((_metile_register_packed__________ >> 8) & 1u) << 8) | (((_metile_register_packed__________ >> 9) & 1u) << 9));\n int _metile_register_packed___________ = _metile_bounded_thread + 352;\n int _metile_register_index___________ = int((((_metile_register_packed___________ >> 5) & 1u) << 0) | (((_metile_register_packed___________ >> 6) & 1u) << 1) | (((_metile_register_packed___________ >> 0) & 1u) << 2) | (((_metile_register_packed___________ >> 1) & 1u) << 3) | (((_metile_register_packed___________ >> 2) & 1u) << 4) | (((_metile_register_packed___________ >> 3) & 1u) << 5) | (((_metile_register_packed___________ >> 4) & 1u) << 6) | (((_metile_register_packed___________ >> 7) & 1u) << 7) | (((_metile_register_packed___________ >> 8) & 1u) << 8) | (((_metile_register_packed___________ >> 9) & 1u) << 9));\n int _metile_register_packed____________ = _metile_bounded_thread + 384;\n int _metile_register_index____________ = int((((_metile_register_packed____________ >> 5) & 1u) << 0) | (((_metile_register_packed____________ >> 6) & 1u) << 1) | (((_metile_register_packed____________ >> 0) & 1u) << 2) | (((_metile_register_packed____________ >> 1) & 1u) << 3) | (((_metile_register_packed____________ >> 2) & 1u) << 4) | (((_metile_register_packed____________ >> 3) & 1u) << 5) | (((_metile_register_packed____________ >> 4) & 1u) << 6) | (((_metile_register_packed____________ >> 7) & 1u) << 7) | (((_metile_register_packed____________ >> 8) & 1u) << 8) | (((_metile_register_packed____________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________ = _metile_bounded_thread + 416;\n int _metile_register_index_____________ = int((((_metile_register_packed_____________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________ >> 9) & 1u) << 9));\n int _metile_register_packed______________ = _metile_bounded_thread + 448;\n int _metile_register_index______________ = int((((_metile_register_packed______________ >> 5) & 1u) << 0) | (((_metile_register_packed______________ >> 6) & 1u) << 1) | (((_metile_register_packed______________ >> 0) & 1u) << 2) | (((_metile_register_packed______________ >> 1) & 1u) << 3) | (((_metile_register_packed______________ >> 2) & 1u) << 4) | (((_metile_register_packed______________ >> 3) & 1u) << 5) | (((_metile_register_packed______________ >> 4) & 1u) << 6) | (((_metile_register_packed______________ >> 7) & 1u) << 7) | (((_metile_register_packed______________ >> 8) & 1u) << 8) | (((_metile_register_packed______________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________ = _metile_bounded_thread + 480;\n int _metile_register_index_______________ = int((((_metile_register_packed_______________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________ >> 9) & 1u) << 9));\n int _metile_register_packed________________ = _metile_bounded_thread + 512;\n int _metile_register_index________________ = int((((_metile_register_packed________________ >> 5) & 1u) << 0) | (((_metile_register_packed________________ >> 6) & 1u) << 1) | (((_metile_register_packed________________ >> 0) & 1u) << 2) | (((_metile_register_packed________________ >> 1) & 1u) << 3) | (((_metile_register_packed________________ >> 2) & 1u) << 4) | (((_metile_register_packed________________ >> 3) & 1u) << 5) | (((_metile_register_packed________________ >> 4) & 1u) << 6) | (((_metile_register_packed________________ >> 7) & 1u) << 7) | (((_metile_register_packed________________ >> 8) & 1u) << 8) | (((_metile_register_packed________________ >> 9) & 1u) << 9));\n int _metile_register_packed_________________ = _metile_bounded_thread + 544;\n int _metile_register_index_________________ = int((((_metile_register_packed_________________ >> 5) & 1u) << 0) | (((_metile_register_packed_________________ >> 6) & 1u) << 1) | (((_metile_register_packed_________________ >> 0) & 1u) << 2) | (((_metile_register_packed_________________ >> 1) & 1u) << 3) | (((_metile_register_packed_________________ >> 2) & 1u) << 4) | (((_metile_register_packed_________________ >> 3) & 1u) << 5) | (((_metile_register_packed_________________ >> 4) & 1u) << 6) | (((_metile_register_packed_________________ >> 7) & 1u) << 7) | (((_metile_register_packed_________________ >> 8) & 1u) << 8) | (((_metile_register_packed_________________ >> 9) & 1u) << 9));\n int _metile_register_packed__________________ = _metile_bounded_thread + 576;\n int _metile_register_index__________________ = int((((_metile_register_packed__________________ >> 5) & 1u) << 0) | (((_metile_register_packed__________________ >> 6) & 1u) << 1) | (((_metile_register_packed__________________ >> 0) & 1u) << 2) | (((_metile_register_packed__________________ >> 1) & 1u) << 3) | (((_metile_register_packed__________________ >> 2) & 1u) << 4) | (((_metile_register_packed__________________ >> 3) & 1u) << 5) | (((_metile_register_packed__________________ >> 4) & 1u) << 6) | (((_metile_register_packed__________________ >> 7) & 1u) << 7) | (((_metile_register_packed__________________ >> 8) & 1u) << 8) | (((_metile_register_packed__________________ >> 9) & 1u) << 9));\n int _metile_register_packed___________________ = _metile_bounded_thread + 608;\n int _metile_register_index___________________ = int((((_metile_register_packed___________________ >> 5) & 1u) << 0) | (((_metile_register_packed___________________ >> 6) & 1u) << 1) | (((_metile_register_packed___________________ >> 0) & 1u) << 2) | (((_metile_register_packed___________________ >> 1) & 1u) << 3) | (((_metile_register_packed___________________ >> 2) & 1u) << 4) | (((_metile_register_packed___________________ >> 3) & 1u) << 5) | (((_metile_register_packed___________________ >> 4) & 1u) << 6) | (((_metile_register_packed___________________ >> 7) & 1u) << 7) | (((_metile_register_packed___________________ >> 8) & 1u) << 8) | (((_metile_register_packed___________________ >> 9) & 1u) << 9));\n int _metile_register_packed____________________ = _metile_bounded_thread + 640;\n int _metile_register_index____________________ = int((((_metile_register_packed____________________ >> 5) & 1u) << 0) | (((_metile_register_packed____________________ >> 6) & 1u) << 1) | (((_metile_register_packed____________________ >> 0) & 1u) << 2) | (((_metile_register_packed____________________ >> 1) & 1u) << 3) | (((_metile_register_packed____________________ >> 2) & 1u) << 4) | (((_metile_register_packed____________________ >> 3) & 1u) << 5) | (((_metile_register_packed____________________ >> 4) & 1u) << 6) | (((_metile_register_packed____________________ >> 7) & 1u) << 7) | (((_metile_register_packed____________________ >> 8) & 1u) << 8) | (((_metile_register_packed____________________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________________ = _metile_bounded_thread + 672;\n int _metile_register_index_____________________ = int((((_metile_register_packed_____________________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________________ >> 9) & 1u) << 9));\n int _metile_register_packed______________________ = _metile_bounded_thread + 704;\n int _metile_register_index______________________ = int((((_metile_register_packed______________________ >> 5) & 1u) << 0) | (((_metile_register_packed______________________ >> 6) & 1u) << 1) | (((_metile_register_packed______________________ >> 0) & 1u) << 2) | (((_metile_register_packed______________________ >> 1) & 1u) << 3) | (((_metile_register_packed______________________ >> 2) & 1u) << 4) | (((_metile_register_packed______________________ >> 3) & 1u) << 5) | (((_metile_register_packed______________________ >> 4) & 1u) << 6) | (((_metile_register_packed______________________ >> 7) & 1u) << 7) | (((_metile_register_packed______________________ >> 8) & 1u) << 8) | (((_metile_register_packed______________________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________________ = _metile_bounded_thread + 736;\n int _metile_register_index_______________________ = int((((_metile_register_packed_______________________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________________ >> 9) & 1u) << 9));\n int _metile_register_packed________________________ = _metile_bounded_thread + 768;\n int _metile_register_index________________________ = int((((_metile_register_packed________________________ >> 5) & 1u) << 0) | (((_metile_register_packed________________________ >> 6) & 1u) << 1) | (((_metile_register_packed________________________ >> 0) & 1u) << 2) | (((_metile_register_packed________________________ >> 1) & 1u) << 3) | (((_metile_register_packed________________________ >> 2) & 1u) << 4) | (((_metile_register_packed________________________ >> 3) & 1u) << 5) | (((_metile_register_packed________________________ >> 4) & 1u) << 6) | (((_metile_register_packed________________________ >> 7) & 1u) << 7) | (((_metile_register_packed________________________ >> 8) & 1u) << 8) | (((_metile_register_packed________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_________________________ = _metile_bounded_thread + 800;\n int _metile_register_index_________________________ = int((((_metile_register_packed_________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_________________________ >> 9) & 1u) << 9));\n int _metile_register_packed__________________________ = _metile_bounded_thread + 832;\n int _metile_register_index__________________________ = int((((_metile_register_packed__________________________ >> 5) & 1u) << 0) | (((_metile_register_packed__________________________ >> 6) & 1u) << 1) | (((_metile_register_packed__________________________ >> 0) & 1u) << 2) | (((_metile_register_packed__________________________ >> 1) & 1u) << 3) | (((_metile_register_packed__________________________ >> 2) & 1u) << 4) | (((_metile_register_packed__________________________ >> 3) & 1u) << 5) | (((_metile_register_packed__________________________ >> 4) & 1u) << 6) | (((_metile_register_packed__________________________ >> 7) & 1u) << 7) | (((_metile_register_packed__________________________ >> 8) & 1u) << 8) | (((_metile_register_packed__________________________ >> 9) & 1u) << 9));\n int _metile_register_packed___________________________ = _metile_bounded_thread + 864;\n int _metile_register_index___________________________ = int((((_metile_register_packed___________________________ >> 5) & 1u) << 0) | (((_metile_register_packed___________________________ >> 6) & 1u) << 1) | (((_metile_register_packed___________________________ >> 0) & 1u) << 2) | (((_metile_register_packed___________________________ >> 1) & 1u) << 3) | (((_metile_register_packed___________________________ >> 2) & 1u) << 4) | (((_metile_register_packed___________________________ >> 3) & 1u) << 5) | (((_metile_register_packed___________________________ >> 4) & 1u) << 6) | (((_metile_register_packed___________________________ >> 7) & 1u) << 7) | (((_metile_register_packed___________________________ >> 8) & 1u) << 8) | (((_metile_register_packed___________________________ >> 9) & 1u) << 9));\n int _metile_register_packed____________________________ = _metile_bounded_thread + 896;\n int _metile_register_index____________________________ = int((((_metile_register_packed____________________________ >> 5) & 1u) << 0) | (((_metile_register_packed____________________________ >> 6) & 1u) << 1) | (((_metile_register_packed____________________________ >> 0) & 1u) << 2) | (((_metile_register_packed____________________________ >> 1) & 1u) << 3) | (((_metile_register_packed____________________________ >> 2) & 1u) << 4) | (((_metile_register_packed____________________________ >> 3) & 1u) << 5) | (((_metile_register_packed____________________________ >> 4) & 1u) << 6) | (((_metile_register_packed____________________________ >> 7) & 1u) << 7) | (((_metile_register_packed____________________________ >> 8) & 1u) << 8) | (((_metile_register_packed____________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________________________ = _metile_bounded_thread + 928;\n int _metile_register_index_____________________________ = int((((_metile_register_packed_____________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________________________ >> 9) & 1u) << 9));\n int _metile_register_packed______________________________ = _metile_bounded_thread + 960;\n int _metile_register_index______________________________ = int((((_metile_register_packed______________________________ >> 5) & 1u) << 0) | (((_metile_register_packed______________________________ >> 6) & 1u) << 1) | (((_metile_register_packed______________________________ >> 0) & 1u) << 2) | (((_metile_register_packed______________________________ >> 1) & 1u) << 3) | (((_metile_register_packed______________________________ >> 2) & 1u) << 4) | (((_metile_register_packed______________________________ >> 3) & 1u) << 5) | (((_metile_register_packed______________________________ >> 4) & 1u) << 6) | (((_metile_register_packed______________________________ >> 7) & 1u) << 7) | (((_metile_register_packed______________________________ >> 8) & 1u) << 8) | (((_metile_register_packed______________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________________________ = _metile_bounded_thread + 992;\n int _metile_register_index_______________________________ = int((((_metile_register_packed_______________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________________________ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v16_r16 = _metile_register_index________________ >= 0;\n bool _metile_v16_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v16_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v16_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v16_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v16_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v16_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v16_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v16_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v16_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v16_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v16_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v16_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v16_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v16_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v16_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v17_r8 = _metile_register_index________ < 1009;\n bool _metile_v17_r9 = _metile_register_index_________ < 1009;\n bool _metile_v17_r10 = _metile_register_index__________ < 1009;\n bool _metile_v17_r11 = _metile_register_index___________ < 1009;\n bool _metile_v17_r12 = _metile_register_index____________ < 1009;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v17_r14 = _metile_register_index______________ < 1009;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v17_r16 = _metile_register_index________________ < 1009;\n bool _metile_v17_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v17_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v17_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v17_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v17_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v17_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v17_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v17_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v17_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v17_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v17_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v17_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v17_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v17_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v17_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n bool _metile_v18_r16 = _metile_v16_r16 & _metile_v17_r16;\n bool _metile_v18_r17 = _metile_v16_r17 & _metile_v17_r17;\n bool _metile_v18_r18 = _metile_v16_r18 & _metile_v17_r18;\n bool _metile_v18_r19 = _metile_v16_r19 & _metile_v17_r19;\n bool _metile_v18_r20 = _metile_v16_r20 & _metile_v17_r20;\n bool _metile_v18_r21 = _metile_v16_r21 & _metile_v17_r21;\n bool _metile_v18_r22 = _metile_v16_r22 & _metile_v17_r22;\n bool _metile_v18_r23 = _metile_v16_r23 & _metile_v17_r23;\n bool _metile_v18_r24 = _metile_v16_r24 & _metile_v17_r24;\n bool _metile_v18_r25 = _metile_v16_r25 & _metile_v17_r25;\n bool _metile_v18_r26 = _metile_v16_r26 & _metile_v17_r26;\n bool _metile_v18_r27 = _metile_v16_r27 & _metile_v17_r27;\n bool _metile_v18_r28 = _metile_v16_r28 & _metile_v17_r28;\n bool _metile_v18_r29 = _metile_v16_r29 & _metile_v17_r29;\n bool _metile_v18_r30 = _metile_v16_r30 & _metile_v17_r30;\n bool _metile_v18_r31 = _metile_v16_r31 & _metile_v17_r31;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n int _off__metile_v19_r16 = v2 + _metile_register_index________________;\n int _off__metile_v19_r17 = v2 + _metile_register_index_________________;\n int _off__metile_v19_r18 = v2 + _metile_register_index__________________;\n int _off__metile_v19_r19 = v2 + _metile_register_index___________________;\n int _off__metile_v19_r20 = v2 + _metile_register_index____________________;\n int _off__metile_v19_r21 = v2 + _metile_register_index_____________________;\n int _off__metile_v19_r22 = v2 + _metile_register_index______________________;\n int _off__metile_v19_r23 = v2 + _metile_register_index_______________________;\n int _off__metile_v19_r24 = v2 + _metile_register_index________________________;\n int _off__metile_v19_r25 = v2 + _metile_register_index_________________________;\n int _off__metile_v19_r26 = v2 + _metile_register_index__________________________;\n int _off__metile_v19_r27 = v2 + _metile_register_index___________________________;\n int _off__metile_v19_r28 = v2 + _metile_register_index____________________________;\n int _off__metile_v19_r29 = v2 + _metile_register_index_____________________________;\n int _off__metile_v19_r30 = v2 + _metile_register_index______________________________;\n int _off__metile_v19_r31 = v2 + _metile_register_index_______________________________;\n float4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = float4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n float _metile_v20_r0 = _metile_vector_load[0];\n float _metile_v20_r1 = _metile_vector_load[1];\n float _metile_v20_r2 = _metile_vector_load[2];\n float _metile_v20_r3 = _metile_vector_load[3];\n float4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = float4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n float _metile_v20_r4 = _metile_vector_load_[0];\n float _metile_v20_r5 = _metile_vector_load_[1];\n float _metile_v20_r6 = _metile_vector_load_[2];\n float _metile_v20_r7 = _metile_vector_load_[3];\n float4 _metile_vector_load__;\n if ((_metile_v18_r8) && (_metile_v18_r9) && (_metile_v18_r10) && (_metile_v18_r11) && (long(_off__metile_v19_r9) == long(_off__metile_v19_r8) + 1) && (long(_off__metile_v19_r10) == long(_off__metile_v19_r8) + 2) && (long(_off__metile_v19_r11) == long(_off__metile_v19_r8) + 3)) {\n _metile_vector_load__ = float4(*reinterpret_cast(X + _off__metile_v19_r8));\n } else {\n _metile_vector_load__[0] = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n _metile_vector_load__[1] = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n _metile_vector_load__[2] = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n _metile_vector_load__[3] = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n }\n float _metile_v20_r8 = _metile_vector_load__[0];\n float _metile_v20_r9 = _metile_vector_load__[1];\n float _metile_v20_r10 = _metile_vector_load__[2];\n float _metile_v20_r11 = _metile_vector_load__[3];\n float4 _metile_vector_load___;\n if ((_metile_v18_r12) && (_metile_v18_r13) && (_metile_v18_r14) && (_metile_v18_r15) && (long(_off__metile_v19_r13) == long(_off__metile_v19_r12) + 1) && (long(_off__metile_v19_r14) == long(_off__metile_v19_r12) + 2) && (long(_off__metile_v19_r15) == long(_off__metile_v19_r12) + 3)) {\n _metile_vector_load___ = float4(*reinterpret_cast(X + _off__metile_v19_r12));\n } else {\n _metile_vector_load___[0] = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n _metile_vector_load___[1] = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n _metile_vector_load___[2] = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n _metile_vector_load___[3] = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n }\n float _metile_v20_r12 = _metile_vector_load___[0];\n float _metile_v20_r13 = _metile_vector_load___[1];\n float _metile_v20_r14 = _metile_vector_load___[2];\n float _metile_v20_r15 = _metile_vector_load___[3];\n float4 _metile_vector_load____;\n if ((_metile_v18_r16) && (_metile_v18_r17) && (_metile_v18_r18) && (_metile_v18_r19) && (long(_off__metile_v19_r17) == long(_off__metile_v19_r16) + 1) && (long(_off__metile_v19_r18) == long(_off__metile_v19_r16) + 2) && (long(_off__metile_v19_r19) == long(_off__metile_v19_r16) + 3)) {\n _metile_vector_load____ = float4(*reinterpret_cast(X + _off__metile_v19_r16));\n } else {\n _metile_vector_load____[0] = _metile_v18_r16 ? X[_off__metile_v19_r16] : static_cast(0);\n _metile_vector_load____[1] = _metile_v18_r17 ? X[_off__metile_v19_r17] : static_cast(0);\n _metile_vector_load____[2] = _metile_v18_r18 ? X[_off__metile_v19_r18] : static_cast(0);\n _metile_vector_load____[3] = _metile_v18_r19 ? X[_off__metile_v19_r19] : static_cast(0);\n }\n float _metile_v20_r16 = _metile_vector_load____[0];\n float _metile_v20_r17 = _metile_vector_load____[1];\n float _metile_v20_r18 = _metile_vector_load____[2];\n float _metile_v20_r19 = _metile_vector_load____[3];\n float4 _metile_vector_load_____;\n if ((_metile_v18_r20) && (_metile_v18_r21) && (_metile_v18_r22) && (_metile_v18_r23) && (long(_off__metile_v19_r21) == long(_off__metile_v19_r20) + 1) && (long(_off__metile_v19_r22) == long(_off__metile_v19_r20) + 2) && (long(_off__metile_v19_r23) == long(_off__metile_v19_r20) + 3)) {\n _metile_vector_load_____ = float4(*reinterpret_cast(X + _off__metile_v19_r20));\n } else {\n _metile_vector_load_____[0] = _metile_v18_r20 ? X[_off__metile_v19_r20] : static_cast(0);\n _metile_vector_load_____[1] = _metile_v18_r21 ? X[_off__metile_v19_r21] : static_cast(0);\n _metile_vector_load_____[2] = _metile_v18_r22 ? X[_off__metile_v19_r22] : static_cast(0);\n _metile_vector_load_____[3] = _metile_v18_r23 ? X[_off__metile_v19_r23] : static_cast(0);\n }\n float _metile_v20_r20 = _metile_vector_load_____[0];\n float _metile_v20_r21 = _metile_vector_load_____[1];\n float _metile_v20_r22 = _metile_vector_load_____[2];\n float _metile_v20_r23 = _metile_vector_load_____[3];\n float4 _metile_vector_load______;\n if ((_metile_v18_r24) && (_metile_v18_r25) && (_metile_v18_r26) && (_metile_v18_r27) && (long(_off__metile_v19_r25) == long(_off__metile_v19_r24) + 1) && (long(_off__metile_v19_r26) == long(_off__metile_v19_r24) + 2) && (long(_off__metile_v19_r27) == long(_off__metile_v19_r24) + 3)) {\n _metile_vector_load______ = float4(*reinterpret_cast(X + _off__metile_v19_r24));\n } else {\n _metile_vector_load______[0] = _metile_v18_r24 ? X[_off__metile_v19_r24] : static_cast(0);\n _metile_vector_load______[1] = _metile_v18_r25 ? X[_off__metile_v19_r25] : static_cast(0);\n _metile_vector_load______[2] = _metile_v18_r26 ? X[_off__metile_v19_r26] : static_cast(0);\n _metile_vector_load______[3] = _metile_v18_r27 ? X[_off__metile_v19_r27] : static_cast(0);\n }\n float _metile_v20_r24 = _metile_vector_load______[0];\n float _metile_v20_r25 = _metile_vector_load______[1];\n float _metile_v20_r26 = _metile_vector_load______[2];\n float _metile_v20_r27 = _metile_vector_load______[3];\n float4 _metile_vector_load_______;\n if ((_metile_v18_r28) && (_metile_v18_r29) && (_metile_v18_r30) && (_metile_v18_r31) && (long(_off__metile_v19_r29) == long(_off__metile_v19_r28) + 1) && (long(_off__metile_v19_r30) == long(_off__metile_v19_r28) + 2) && (long(_off__metile_v19_r31) == long(_off__metile_v19_r28) + 3)) {\n _metile_vector_load_______ = float4(*reinterpret_cast(X + _off__metile_v19_r28));\n } else {\n _metile_vector_load_______[0] = _metile_v18_r28 ? X[_off__metile_v19_r28] : static_cast(0);\n _metile_vector_load_______[1] = _metile_v18_r29 ? X[_off__metile_v19_r29] : static_cast(0);\n _metile_vector_load_______[2] = _metile_v18_r30 ? X[_off__metile_v19_r30] : static_cast(0);\n _metile_vector_load_______[3] = _metile_v18_r31 ? X[_off__metile_v19_r31] : static_cast(0);\n }\n float _metile_v20_r28 = _metile_vector_load_______[0];\n float _metile_v20_r29 = _metile_vector_load_______[1];\n float _metile_v20_r30 = _metile_vector_load_______[2];\n float _metile_v20_r31 = _metile_vector_load_______[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v21_r16 = static_cast(_metile_v20_r16);\n float _metile_v21_r17 = static_cast(_metile_v20_r17);\n float _metile_v21_r18 = static_cast(_metile_v20_r18);\n float _metile_v21_r19 = static_cast(_metile_v20_r19);\n float _metile_v21_r20 = static_cast(_metile_v20_r20);\n float _metile_v21_r21 = static_cast(_metile_v20_r21);\n float _metile_v21_r22 = static_cast(_metile_v20_r22);\n float _metile_v21_r23 = static_cast(_metile_v20_r23);\n float _metile_v21_r24 = static_cast(_metile_v20_r24);\n float _metile_v21_r25 = static_cast(_metile_v20_r25);\n float _metile_v21_r26 = static_cast(_metile_v20_r26);\n float _metile_v21_r27 = static_cast(_metile_v20_r27);\n float _metile_v21_r28 = static_cast(_metile_v20_r28);\n float _metile_v21_r29 = static_cast(_metile_v20_r29);\n float _metile_v21_r30 = static_cast(_metile_v20_r30);\n float _metile_v21_r31 = static_cast(_metile_v20_r31);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_v22_r16 = _metile_v21_r16 * _metile_v21_r16;\n float _metile_v22_r17 = _metile_v21_r17 * _metile_v21_r17;\n float _metile_v22_r18 = _metile_v21_r18 * _metile_v21_r18;\n float _metile_v22_r19 = _metile_v21_r19 * _metile_v21_r19;\n float _metile_v22_r20 = _metile_v21_r20 * _metile_v21_r20;\n float _metile_v22_r21 = _metile_v21_r21 * _metile_v21_r21;\n float _metile_v22_r22 = _metile_v21_r22 * _metile_v21_r22;\n float _metile_v22_r23 = _metile_v21_r23 * _metile_v21_r23;\n float _metile_v22_r24 = _metile_v21_r24 * _metile_v21_r24;\n float _metile_v22_r25 = _metile_v21_r25 * _metile_v21_r25;\n float _metile_v22_r26 = _metile_v21_r26 * _metile_v21_r26;\n float _metile_v22_r27 = _metile_v21_r27 * _metile_v21_r27;\n float _metile_v22_r28 = _metile_v21_r28 * _metile_v21_r28;\n float _metile_v22_r29 = _metile_v21_r29 * _metile_v21_r29;\n float _metile_v22_r30 = _metile_v21_r30 * _metile_v21_r30;\n float _metile_v22_r31 = _metile_v21_r31 * _metile_v21_r31;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_v22_r16 + _metile_v22_r17;\n float _metile_register_sum_________ = _metile_v22_r18 + _metile_v22_r19;\n float _metile_register_sum__________ = _metile_v22_r20 + _metile_v22_r21;\n float _metile_register_sum___________ = _metile_v22_r22 + _metile_v22_r23;\n float _metile_register_sum____________ = _metile_v22_r24 + _metile_v22_r25;\n float _metile_register_sum_____________ = _metile_v22_r26 + _metile_v22_r27;\n float _metile_register_sum______________ = _metile_v22_r28 + _metile_v22_r29;\n float _metile_register_sum_______________ = _metile_v22_r30 + _metile_v22_r31;\n float _metile_register_sum________________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________________ = _metile_register_sum____________ + _metile_register_sum_____________;\n float _metile_register_sum_______________________ = _metile_register_sum______________ + _metile_register_sum_______________;\n float _metile_register_sum________________________ = _metile_register_sum________________ + _metile_register_sum_________________;\n float _metile_register_sum_________________________ = _metile_register_sum__________________ + _metile_register_sum___________________;\n float _metile_register_sum__________________________ = _metile_register_sum____________________ + _metile_register_sum_____________________;\n float _metile_register_sum___________________________ = _metile_register_sum______________________ + _metile_register_sum_______________________;\n float _metile_register_sum____________________________ = _metile_register_sum________________________ + _metile_register_sum_________________________;\n float _metile_register_sum_____________________________ = _metile_register_sum__________________________ + _metile_register_sum___________________________;\n float _metile_register_sum______________________________ = _metile_register_sum____________________________ + _metile_register_sum_____________________________;\n float v23 = simd_sum(_metile_register_sum______________________________);\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v32_r16 = _metile_register_index________________ >= 0;\n bool _metile_v32_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v32_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v32_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v32_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v32_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v32_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v32_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v32_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v32_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v32_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v32_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v32_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v32_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v32_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v32_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v33_r8 = _metile_register_index________ < 1009;\n bool _metile_v33_r9 = _metile_register_index_________ < 1009;\n bool _metile_v33_r10 = _metile_register_index__________ < 1009;\n bool _metile_v33_r11 = _metile_register_index___________ < 1009;\n bool _metile_v33_r12 = _metile_register_index____________ < 1009;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v33_r14 = _metile_register_index______________ < 1009;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v33_r16 = _metile_register_index________________ < 1009;\n bool _metile_v33_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v33_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v33_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v33_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v33_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v33_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v33_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v33_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v33_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v33_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v33_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v33_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v33_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v33_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v33_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n bool _metile_v34_r16 = _metile_v32_r16 & _metile_v33_r16;\n bool _metile_v34_r17 = _metile_v32_r17 & _metile_v33_r17;\n bool _metile_v34_r18 = _metile_v32_r18 & _metile_v33_r18;\n bool _metile_v34_r19 = _metile_v32_r19 & _metile_v33_r19;\n bool _metile_v34_r20 = _metile_v32_r20 & _metile_v33_r20;\n bool _metile_v34_r21 = _metile_v32_r21 & _metile_v33_r21;\n bool _metile_v34_r22 = _metile_v32_r22 & _metile_v33_r22;\n bool _metile_v34_r23 = _metile_v32_r23 & _metile_v33_r23;\n bool _metile_v34_r24 = _metile_v32_r24 & _metile_v33_r24;\n bool _metile_v34_r25 = _metile_v32_r25 & _metile_v33_r25;\n bool _metile_v34_r26 = _metile_v32_r26 & _metile_v33_r26;\n bool _metile_v34_r27 = _metile_v32_r27 & _metile_v33_r27;\n bool _metile_v34_r28 = _metile_v32_r28 & _metile_v33_r28;\n bool _metile_v34_r29 = _metile_v32_r29 & _metile_v33_r29;\n bool _metile_v34_r30 = _metile_v32_r30 & _metile_v33_r30;\n bool _metile_v34_r31 = _metile_v32_r31 & _metile_v33_r31;\n float4 _metile_vector_load________;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load________ = float4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load________[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load________[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load________[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load________[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n float _metile_v36_r0 = _metile_vector_load________[0];\n float _metile_v36_r1 = _metile_vector_load________[1];\n float _metile_v36_r2 = _metile_vector_load________[2];\n float _metile_v36_r3 = _metile_vector_load________[3];\n float4 _metile_vector_load_________;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load_________ = float4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load_________[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load_________[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load_________[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load_________[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n float _metile_v36_r4 = _metile_vector_load_________[0];\n float _metile_v36_r5 = _metile_vector_load_________[1];\n float _metile_v36_r6 = _metile_vector_load_________[2];\n float _metile_v36_r7 = _metile_vector_load_________[3];\n float4 _metile_vector_load__________;\n if ((_metile_v34_r8) && (_metile_v34_r9) && (_metile_v34_r10) && (_metile_v34_r11) && (long(_metile_register_index_________) == long(_metile_register_index________) + 1) && (long(_metile_register_index__________) == long(_metile_register_index________) + 2) && (long(_metile_register_index___________) == long(_metile_register_index________) + 3)) {\n _metile_vector_load__________ = float4(*reinterpret_cast(W + _metile_register_index________));\n } else {\n _metile_vector_load__________[0] = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n _metile_vector_load__________[1] = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n _metile_vector_load__________[2] = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n _metile_vector_load__________[3] = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n }\n float _metile_v36_r8 = _metile_vector_load__________[0];\n float _metile_v36_r9 = _metile_vector_load__________[1];\n float _metile_v36_r10 = _metile_vector_load__________[2];\n float _metile_v36_r11 = _metile_vector_load__________[3];\n float4 _metile_vector_load___________;\n if ((_metile_v34_r12) && (_metile_v34_r13) && (_metile_v34_r14) && (_metile_v34_r15) && (long(_metile_register_index_____________) == long(_metile_register_index____________) + 1) && (long(_metile_register_index______________) == long(_metile_register_index____________) + 2) && (long(_metile_register_index_______________) == long(_metile_register_index____________) + 3)) {\n _metile_vector_load___________ = float4(*reinterpret_cast(W + _metile_register_index____________));\n } else {\n _metile_vector_load___________[0] = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n _metile_vector_load___________[1] = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n _metile_vector_load___________[2] = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n _metile_vector_load___________[3] = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n }\n float _metile_v36_r12 = _metile_vector_load___________[0];\n float _metile_v36_r13 = _metile_vector_load___________[1];\n float _metile_v36_r14 = _metile_vector_load___________[2];\n float _metile_v36_r15 = _metile_vector_load___________[3];\n float4 _metile_vector_load____________;\n if ((_metile_v34_r16) && (_metile_v34_r17) && (_metile_v34_r18) && (_metile_v34_r19) && (long(_metile_register_index_________________) == long(_metile_register_index________________) + 1) && (long(_metile_register_index__________________) == long(_metile_register_index________________) + 2) && (long(_metile_register_index___________________) == long(_metile_register_index________________) + 3)) {\n _metile_vector_load____________ = float4(*reinterpret_cast(W + _metile_register_index________________));\n } else {\n _metile_vector_load____________[0] = _metile_v34_r16 ? W[_metile_register_index________________] : static_cast(0);\n _metile_vector_load____________[1] = _metile_v34_r17 ? W[_metile_register_index_________________] : static_cast(0);\n _metile_vector_load____________[2] = _metile_v34_r18 ? W[_metile_register_index__________________] : static_cast(0);\n _metile_vector_load____________[3] = _metile_v34_r19 ? W[_metile_register_index___________________] : static_cast(0);\n }\n float _metile_v36_r16 = _metile_vector_load____________[0];\n float _metile_v36_r17 = _metile_vector_load____________[1];\n float _metile_v36_r18 = _metile_vector_load____________[2];\n float _metile_v36_r19 = _metile_vector_load____________[3];\n float4 _metile_vector_load_____________;\n if ((_metile_v34_r20) && (_metile_v34_r21) && (_metile_v34_r22) && (_metile_v34_r23) && (long(_metile_register_index_____________________) == long(_metile_register_index____________________) + 1) && (long(_metile_register_index______________________) == long(_metile_register_index____________________) + 2) && (long(_metile_register_index_______________________) == long(_metile_register_index____________________) + 3)) {\n _metile_vector_load_____________ = float4(*reinterpret_cast(W + _metile_register_index____________________));\n } else {\n _metile_vector_load_____________[0] = _metile_v34_r20 ? W[_metile_register_index____________________] : static_cast(0);\n _metile_vector_load_____________[1] = _metile_v34_r21 ? W[_metile_register_index_____________________] : static_cast(0);\n _metile_vector_load_____________[2] = _metile_v34_r22 ? W[_metile_register_index______________________] : static_cast(0);\n _metile_vector_load_____________[3] = _metile_v34_r23 ? W[_metile_register_index_______________________] : static_cast(0);\n }\n float _metile_v36_r20 = _metile_vector_load_____________[0];\n float _metile_v36_r21 = _metile_vector_load_____________[1];\n float _metile_v36_r22 = _metile_vector_load_____________[2];\n float _metile_v36_r23 = _metile_vector_load_____________[3];\n float4 _metile_vector_load______________;\n if ((_metile_v34_r24) && (_metile_v34_r25) && (_metile_v34_r26) && (_metile_v34_r27) && (long(_metile_register_index_________________________) == long(_metile_register_index________________________) + 1) && (long(_metile_register_index__________________________) == long(_metile_register_index________________________) + 2) && (long(_metile_register_index___________________________) == long(_metile_register_index________________________) + 3)) {\n _metile_vector_load______________ = float4(*reinterpret_cast(W + _metile_register_index________________________));\n } else {\n _metile_vector_load______________[0] = _metile_v34_r24 ? W[_metile_register_index________________________] : static_cast(0);\n _metile_vector_load______________[1] = _metile_v34_r25 ? W[_metile_register_index_________________________] : static_cast(0);\n _metile_vector_load______________[2] = _metile_v34_r26 ? W[_metile_register_index__________________________] : static_cast(0);\n _metile_vector_load______________[3] = _metile_v34_r27 ? W[_metile_register_index___________________________] : static_cast(0);\n }\n float _metile_v36_r24 = _metile_vector_load______________[0];\n float _metile_v36_r25 = _metile_vector_load______________[1];\n float _metile_v36_r26 = _metile_vector_load______________[2];\n float _metile_v36_r27 = _metile_vector_load______________[3];\n float4 _metile_vector_load_______________;\n if ((_metile_v34_r28) && (_metile_v34_r29) && (_metile_v34_r30) && (_metile_v34_r31) && (long(_metile_register_index_____________________________) == long(_metile_register_index____________________________) + 1) && (long(_metile_register_index______________________________) == long(_metile_register_index____________________________) + 2) && (long(_metile_register_index_______________________________) == long(_metile_register_index____________________________) + 3)) {\n _metile_vector_load_______________ = float4(*reinterpret_cast(W + _metile_register_index____________________________));\n } else {\n _metile_vector_load_______________[0] = _metile_v34_r28 ? W[_metile_register_index____________________________] : static_cast(0);\n _metile_vector_load_______________[1] = _metile_v34_r29 ? W[_metile_register_index_____________________________] : static_cast(0);\n _metile_vector_load_______________[2] = _metile_v34_r30 ? W[_metile_register_index______________________________] : static_cast(0);\n _metile_vector_load_______________[3] = _metile_v34_r31 ? W[_metile_register_index_______________________________] : static_cast(0);\n }\n float _metile_v36_r28 = _metile_vector_load_______________[0];\n float _metile_v36_r29 = _metile_vector_load_______________[1];\n float _metile_v36_r30 = _metile_vector_load_______________[2];\n float _metile_v36_r31 = _metile_vector_load_______________[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v37_r16 = static_cast(_metile_v36_r16);\n float _metile_v37_r17 = static_cast(_metile_v36_r17);\n float _metile_v37_r18 = static_cast(_metile_v36_r18);\n float _metile_v37_r19 = static_cast(_metile_v36_r19);\n float _metile_v37_r20 = static_cast(_metile_v36_r20);\n float _metile_v37_r21 = static_cast(_metile_v36_r21);\n float _metile_v37_r22 = static_cast(_metile_v36_r22);\n float _metile_v37_r23 = static_cast(_metile_v36_r23);\n float _metile_v37_r24 = static_cast(_metile_v36_r24);\n float _metile_v37_r25 = static_cast(_metile_v36_r25);\n float _metile_v37_r26 = static_cast(_metile_v36_r26);\n float _metile_v37_r27 = static_cast(_metile_v36_r27);\n float _metile_v37_r28 = static_cast(_metile_v36_r28);\n float _metile_v37_r29 = static_cast(_metile_v36_r29);\n float _metile_v37_r30 = static_cast(_metile_v36_r30);\n float _metile_v37_r31 = static_cast(_metile_v36_r31);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v38_r16 = _metile_v21_r16 * v29;\n float _metile_v38_r17 = _metile_v21_r17 * v29;\n float _metile_v38_r18 = _metile_v21_r18 * v29;\n float _metile_v38_r19 = _metile_v21_r19 * v29;\n float _metile_v38_r20 = _metile_v21_r20 * v29;\n float _metile_v38_r21 = _metile_v21_r21 * v29;\n float _metile_v38_r22 = _metile_v21_r22 * v29;\n float _metile_v38_r23 = _metile_v21_r23 * v29;\n float _metile_v38_r24 = _metile_v21_r24 * v29;\n float _metile_v38_r25 = _metile_v21_r25 * v29;\n float _metile_v38_r26 = _metile_v21_r26 * v29;\n float _metile_v38_r27 = _metile_v21_r27 * v29;\n float _metile_v38_r28 = _metile_v21_r28 * v29;\n float _metile_v38_r29 = _metile_v21_r29 * v29;\n float _metile_v38_r30 = _metile_v21_r30 * v29;\n float _metile_v38_r31 = _metile_v21_r31 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n float _metile_v39_r16 = _metile_v38_r16 * _metile_v37_r16;\n float _metile_v39_r17 = _metile_v38_r17 * _metile_v37_r17;\n float _metile_v39_r18 = _metile_v38_r18 * _metile_v37_r18;\n float _metile_v39_r19 = _metile_v38_r19 * _metile_v37_r19;\n float _metile_v39_r20 = _metile_v38_r20 * _metile_v37_r20;\n float _metile_v39_r21 = _metile_v38_r21 * _metile_v37_r21;\n float _metile_v39_r22 = _metile_v38_r22 * _metile_v37_r22;\n float _metile_v39_r23 = _metile_v38_r23 * _metile_v37_r23;\n float _metile_v39_r24 = _metile_v38_r24 * _metile_v37_r24;\n float _metile_v39_r25 = _metile_v38_r25 * _metile_v37_r25;\n float _metile_v39_r26 = _metile_v38_r26 * _metile_v37_r26;\n float _metile_v39_r27 = _metile_v38_r27 * _metile_v37_r27;\n float _metile_v39_r28 = _metile_v38_r28 * _metile_v37_r28;\n float _metile_v39_r29 = _metile_v38_r29 * _metile_v37_r29;\n float _metile_v39_r30 = _metile_v38_r30 * _metile_v37_r30;\n float _metile_v39_r31 = _metile_v38_r31 * _metile_v37_r31;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v41_r16 = _metile_register_index________________ >= 0;\n bool _metile_v41_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v41_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v41_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v41_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v41_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v41_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v41_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v41_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v41_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v41_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v41_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v41_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v41_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v41_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v41_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v42_r8 = _metile_register_index________ < 1009;\n bool _metile_v42_r9 = _metile_register_index_________ < 1009;\n bool _metile_v42_r10 = _metile_register_index__________ < 1009;\n bool _metile_v42_r11 = _metile_register_index___________ < 1009;\n bool _metile_v42_r12 = _metile_register_index____________ < 1009;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v42_r14 = _metile_register_index______________ < 1009;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v42_r16 = _metile_register_index________________ < 1009;\n bool _metile_v42_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v42_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v42_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v42_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v42_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v42_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v42_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v42_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v42_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v42_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v42_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v42_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v42_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v42_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v42_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n bool _metile_v43_r16 = _metile_v41_r16 & _metile_v42_r16;\n bool _metile_v43_r17 = _metile_v41_r17 & _metile_v42_r17;\n bool _metile_v43_r18 = _metile_v41_r18 & _metile_v42_r18;\n bool _metile_v43_r19 = _metile_v41_r19 & _metile_v42_r19;\n bool _metile_v43_r20 = _metile_v41_r20 & _metile_v42_r20;\n bool _metile_v43_r21 = _metile_v41_r21 & _metile_v42_r21;\n bool _metile_v43_r22 = _metile_v41_r22 & _metile_v42_r22;\n bool _metile_v43_r23 = _metile_v41_r23 & _metile_v42_r23;\n bool _metile_v43_r24 = _metile_v41_r24 & _metile_v42_r24;\n bool _metile_v43_r25 = _metile_v41_r25 & _metile_v42_r25;\n bool _metile_v43_r26 = _metile_v41_r26 & _metile_v42_r26;\n bool _metile_v43_r27 = _metile_v41_r27 & _metile_v42_r27;\n bool _metile_v43_r28 = _metile_v41_r28 & _metile_v42_r28;\n bool _metile_v43_r29 = _metile_v41_r29 & _metile_v42_r29;\n bool _metile_v43_r30 = _metile_v41_r30 & _metile_v42_r30;\n bool _metile_v43_r31 = _metile_v41_r31 & _metile_v42_r31;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n int _off__metile_v44_r16 = v9 + _metile_register_index________________;\n int _off__metile_v44_r17 = v9 + _metile_register_index_________________;\n int _off__metile_v44_r18 = v9 + _metile_register_index__________________;\n int _off__metile_v44_r19 = v9 + _metile_register_index___________________;\n int _off__metile_v44_r20 = v9 + _metile_register_index____________________;\n int _off__metile_v44_r21 = v9 + _metile_register_index_____________________;\n int _off__metile_v44_r22 = v9 + _metile_register_index______________________;\n int _off__metile_v44_r23 = v9 + _metile_register_index_______________________;\n int _off__metile_v44_r24 = v9 + _metile_register_index________________________;\n int _off__metile_v44_r25 = v9 + _metile_register_index_________________________;\n int _off__metile_v44_r26 = v9 + _metile_register_index__________________________;\n int _off__metile_v44_r27 = v9 + _metile_register_index___________________________;\n int _off__metile_v44_r28 = v9 + _metile_register_index____________________________;\n int _off__metile_v44_r29 = v9 + _metile_register_index_____________________________;\n int _off__metile_v44_r30 = v9 + _metile_register_index______________________________;\n int _off__metile_v44_r31 = v9 + _metile_register_index_______________________________;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_float4(float4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_float4(float4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n if ((_metile_v43_r8) && (_metile_v43_r9) && (_metile_v43_r10) && (_metile_v43_r11) && (long(_off__metile_v44_r9) == long(_off__metile_v44_r8) + 1) && (long(_off__metile_v44_r10) == long(_off__metile_v44_r8) + 2) && (long(_off__metile_v44_r11) == long(_off__metile_v44_r8) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r8) = packed_float4(float4(static_cast(_metile_v39_r8), static_cast(_metile_v39_r9), static_cast(_metile_v39_r10), static_cast(_metile_v39_r11)));\n } else {\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = static_cast(_metile_v39_r8); }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = static_cast(_metile_v39_r9); }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = static_cast(_metile_v39_r10); }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = static_cast(_metile_v39_r11); }\n }\n if ((_metile_v43_r12) && (_metile_v43_r13) && (_metile_v43_r14) && (_metile_v43_r15) && (long(_off__metile_v44_r13) == long(_off__metile_v44_r12) + 1) && (long(_off__metile_v44_r14) == long(_off__metile_v44_r12) + 2) && (long(_off__metile_v44_r15) == long(_off__metile_v44_r12) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r12) = packed_float4(float4(static_cast(_metile_v39_r12), static_cast(_metile_v39_r13), static_cast(_metile_v39_r14), static_cast(_metile_v39_r15)));\n } else {\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = static_cast(_metile_v39_r12); }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = static_cast(_metile_v39_r13); }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = static_cast(_metile_v39_r14); }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = static_cast(_metile_v39_r15); }\n }\n if ((_metile_v43_r16) && (_metile_v43_r17) && (_metile_v43_r18) && (_metile_v43_r19) && (long(_off__metile_v44_r17) == long(_off__metile_v44_r16) + 1) && (long(_off__metile_v44_r18) == long(_off__metile_v44_r16) + 2) && (long(_off__metile_v44_r19) == long(_off__metile_v44_r16) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r16) = packed_float4(float4(static_cast(_metile_v39_r16), static_cast(_metile_v39_r17), static_cast(_metile_v39_r18), static_cast(_metile_v39_r19)));\n } else {\n if (_metile_v43_r16) { Out[_off__metile_v44_r16] = static_cast(_metile_v39_r16); }\n if (_metile_v43_r17) { Out[_off__metile_v44_r17] = static_cast(_metile_v39_r17); }\n if (_metile_v43_r18) { Out[_off__metile_v44_r18] = static_cast(_metile_v39_r18); }\n if (_metile_v43_r19) { Out[_off__metile_v44_r19] = static_cast(_metile_v39_r19); }\n }\n if ((_metile_v43_r20) && (_metile_v43_r21) && (_metile_v43_r22) && (_metile_v43_r23) && (long(_off__metile_v44_r21) == long(_off__metile_v44_r20) + 1) && (long(_off__metile_v44_r22) == long(_off__metile_v44_r20) + 2) && (long(_off__metile_v44_r23) == long(_off__metile_v44_r20) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r20) = packed_float4(float4(static_cast(_metile_v39_r20), static_cast(_metile_v39_r21), static_cast(_metile_v39_r22), static_cast(_metile_v39_r23)));\n } else {\n if (_metile_v43_r20) { Out[_off__metile_v44_r20] = static_cast(_metile_v39_r20); }\n if (_metile_v43_r21) { Out[_off__metile_v44_r21] = static_cast(_metile_v39_r21); }\n if (_metile_v43_r22) { Out[_off__metile_v44_r22] = static_cast(_metile_v39_r22); }\n if (_metile_v43_r23) { Out[_off__metile_v44_r23] = static_cast(_metile_v39_r23); }\n }\n if ((_metile_v43_r24) && (_metile_v43_r25) && (_metile_v43_r26) && (_metile_v43_r27) && (long(_off__metile_v44_r25) == long(_off__metile_v44_r24) + 1) && (long(_off__metile_v44_r26) == long(_off__metile_v44_r24) + 2) && (long(_off__metile_v44_r27) == long(_off__metile_v44_r24) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r24) = packed_float4(float4(static_cast(_metile_v39_r24), static_cast(_metile_v39_r25), static_cast(_metile_v39_r26), static_cast(_metile_v39_r27)));\n } else {\n if (_metile_v43_r24) { Out[_off__metile_v44_r24] = static_cast(_metile_v39_r24); }\n if (_metile_v43_r25) { Out[_off__metile_v44_r25] = static_cast(_metile_v39_r25); }\n if (_metile_v43_r26) { Out[_off__metile_v44_r26] = static_cast(_metile_v39_r26); }\n if (_metile_v43_r27) { Out[_off__metile_v44_r27] = static_cast(_metile_v39_r27); }\n }\n if ((_metile_v43_r28) && (_metile_v43_r29) && (_metile_v43_r30) && (_metile_v43_r31) && (long(_off__metile_v44_r29) == long(_off__metile_v44_r28) + 1) && (long(_off__metile_v44_r30) == long(_off__metile_v44_r28) + 2) && (long(_off__metile_v44_r31) == long(_off__metile_v44_r28) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r28) = packed_float4(float4(static_cast(_metile_v39_r28), static_cast(_metile_v39_r29), static_cast(_metile_v39_r30), static_cast(_metile_v39_r31)));\n } else {\n if (_metile_v43_r28) { Out[_off__metile_v44_r28] = static_cast(_metile_v39_r28); }\n if (_metile_v43_r29) { Out[_off__metile_v44_r29] = static_cast(_metile_v39_r29); }\n if (_metile_v43_r30) { Out[_off__metile_v44_r30] = static_cast(_metile_v39_r30); }\n if (_metile_v43_r31) { Out[_off__metile_v44_r31] = static_cast(_metile_v39_r31); }\n }\n}", "source_sha256": "8205038bf6ba3e8bd71e472a270b8fc036d7a98adf4a40b12e66c4dc7e4b1644", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 32, 1, 1 ], "is_gemm": false, "prefer_ordered": false, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 32, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 32 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [], "double_buffered": false, "vectorized_loads": 16, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 32, "threads": 32, "scratch": null, "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 16, "grouped_stores": 8 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 487, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 226.625, "control": 222.541, "speedup": 0.9819790402647546 }, "gpu_us": { "candidate": 4.166678991168737, "control": 1.708336640149355, "speedup": 0.4099995809060811 } } }, { "frozen_register4": { "pairs": 315, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 316.709, "control": 307.708, "speedup": 0.9715795888339138 }, "gpu_us": { "candidate": 17.208338249474764, "control": 7.125025149434805, "speedup": 0.41404492671756243 } } }, { "frozen_register4": { "pairs": 319, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 319.91700000000003, "control": 305.708, "speedup": 0.9555853549514405 }, "gpu_us": { "candidate": 17.249956727027893, "control": 7.166643626987934, "speedup": 0.4154586437749703 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9696537810694865, "round_speedups": [ 0.9819790402647546, 0.9715795888339138, 0.9555853549514405 ], "candidate": 284.22908276814024, "control": 275.6038047960391 }, "gpu_us": { "speedup": 0.41316122824232365, "round_speedups": [ 0.4099995809060811, 0.41404492671756243, 0.4154586437749703 ], "candidate": 10.73426540302432, "control": 4.434982278192609 } } } }, { "name": "float32_1x1009", "dtype": "float32", "batches": 1, "width": 1009, "status": "measured", "variant": { "name": "register2_striped", "elements_per_thread": 2, "layout": "striped" }, "input_sha256": "72c4fd9244d1e3fe8e922e59cd98ff745af158f79bcd15c587482eb6749d4442", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 4.76837158203125e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 511;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 512;\n int _metile_register_index_ = int(_metile_register_packed_);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n threadgroup float _metile_register_reduction[16];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 16u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n}", "source_sha256": "9bc3eb88c124547d7881e3d6279f1602e263cfc0456cb6238d2c206b0f83ac05", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 512, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 512, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 2 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 16, "bytes": 64 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 2, "threads": 512, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 618, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.08350000000002, "control": 197.75, "speedup": 1.003381815321932 }, "gpu_us": { "candidate": 1.5416881069540977, "control": 1.6666599549353123, "speedup": 1.0810616929698709 } } }, { "frozen_register4": { "pairs": 608, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.2295, "control": 198.3955, "speedup": 0.990840510514185 }, "gpu_us": { "candidate": 1.583306584507227, "control": 1.6666599549353123, "speedup": 1.0526451233410536 } } }, { "frozen_register4": { "pairs": 501, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.208, "control": 200.709, "speedup": 0.9828655096764084 }, "gpu_us": { "candidate": 1.5833647921681404, "control": 1.6666599549353123, "speedup": 1.0526064259980883 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9923267342797951, "round_speedups": [ 1.003381815321932, 0.990840510514185, 0.9828655096764084 ], "candidate": 200.48583500678563, "control": 198.94745392164143 }, "gpu_us": { "speedup": 1.0620203194849167, "round_speedups": [ 1.0810616929698709, 1.0526451233410536, 1.0526064259980883 ], "candidate": 1.569329629911081, "control": 1.6666599549353123 } } } }, { "name": "float32_1x1009", "dtype": "float32", "batches": 1, "width": 1009, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "72c4fd9244d1e3fe8e922e59cd98ff745af158f79bcd15c587482eb6749d4442", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 2.384185791015625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "c1d33e27fc56debd55c6a508dc39b24b01c51c4f01d8ebe463b73c7d94ad343d", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 618, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.5005, "control": 196.5625, "speedup": 0.9902368004110822 }, "gpu_us": { "candidate": 1.6249832697212696, "control": 1.6666599549353123, "speedup": 1.0256474549557617 } } }, { "frozen_register4": { "pairs": 618, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.83350000000002, "control": 197.8125, "speedup": 0.99989385013155 }, "gpu_us": { "candidate": 1.6249832697212696, "control": 1.6666599549353123, "speedup": 1.0256474549557617 } } }, { "frozen_register4": { "pairs": 504, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 206.8125, "control": 204.47899999999998, "speedup": 0.9887168328800241 }, "gpu_us": { "candidate": 1.6666599549353123, "control": 1.708336640149355, "speedup": 1.0250061118290086 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9929368512557202, "round_speedups": [ 0.9902368004110822, 0.99989385013155, 0.9887168328800241 ], "candidate": 201.00772178854723, "control": 199.5879743508058 }, "gpu_us": { "speedup": 1.0254336293385282, "round_speedups": [ 1.0256474549557617, 1.0256474549557617, 1.0250061118290086 ], "candidate": 1.6387583952158695, "control": 1.6804379688151914 } } } }, { "name": "float32_1x1009", "dtype": "float32", "batches": 1, "width": 1009, "status": "measured", "variant": { "name": "register4_blocked4", "elements_per_thread": 4, "layout": "blocked4" }, "input_sha256": "72c4fd9244d1e3fe8e922e59cd98ff745af158f79bcd15c587482eb6749d4442", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int((((_metile_bounded_thread >> 8) & 1u) << 0) | (((_metile_bounded_thread >> 9) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 6) & 1u) << 8) | (((_metile_bounded_thread >> 7) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 8) & 1u) << 0) | (((_metile_register_packed_ >> 9) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 6) & 1u) << 8) | (((_metile_register_packed_ >> 7) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 8) & 1u) << 0) | (((_metile_register_packed__ >> 9) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 6) & 1u) << 8) | (((_metile_register_packed__ >> 7) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 8) & 1u) << 0) | (((_metile_register_packed___ >> 9) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 6) & 1u) << 8) | (((_metile_register_packed___ >> 7) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = float4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n float _metile_v20_r0 = _metile_vector_load[0];\n float _metile_v20_r1 = _metile_vector_load[1];\n float _metile_v20_r2 = _metile_vector_load[2];\n float _metile_v20_r3 = _metile_vector_load[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float4 _metile_vector_load_;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load_ = float4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load_[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load_[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load_[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load_[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n float _metile_v36_r0 = _metile_vector_load_[0];\n float _metile_v36_r1 = _metile_vector_load_[1];\n float _metile_v36_r2 = _metile_vector_load_[2];\n float _metile_v36_r3 = _metile_vector_load_[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_float4(float4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n}", "source_sha256": "9c1852dfc63c9d26d086e577f959fcc52d4398d11ea3c1c13748f723d2747516", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 2, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 2, "grouped_stores": 1 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 616, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.9375, "control": 198.625, "speedup": 0.9984291548853284 }, "gpu_us": { "candidate": 1.8749851733446121, "control": 1.6666599549353123, "speedup": 0.8888923382590339 } } }, { "frozen_register4": { "pairs": 525, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 205.166, "control": 201.75, "speedup": 0.9833500677500171 }, "gpu_us": { "candidate": 1.8749851733446121, "control": 1.6666599549353123, "speedup": 0.8888923382590339 } } }, { "frozen_register4": { "pairs": 616, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.6255, "control": 198.85399999999998, "speedup": 0.9961352632804927 }, "gpu_us": { "candidate": 1.833366695791483, "control": 1.625041477382183, "speedup": 0.886370130488618 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9926159289685388, "round_speedups": [ 0.9984291548853284, 0.9833500677500171, 0.9961352632804927 ], "candidate": 201.2238039819616, "control": 199.7379531201378 }, "gpu_us": { "speedup": 0.8880508058912527, "round_speedups": [ 0.8888923382590339, 0.8888923382590339, 0.886370130488618 ], "candidate": 1.8610084190664096, "control": 1.6526700263223313 } } } }, { "name": "float32_1x1009", "dtype": "float32", "batches": 1, "width": 1009, "status": "measured", "variant": { "name": "register8_striped", "elements_per_thread": 8, "layout": "striped" }, "input_sha256": "72c4fd9244d1e3fe8e922e59cd98ff745af158f79bcd15c587482eb6749d4442", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 2.384185791015625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 127;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 128;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 256;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 384;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 512;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 640;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 768;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 896;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n float _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n float _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n float _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_____ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum______ = _metile_register_sum____ + _metile_register_sum_____;\n threadgroup float _metile_register_reduction[4];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 4u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n float _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n float _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n float _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n}", "source_sha256": "81a1ee1fc79ce28ef50cf43c835b1d4e5d87eb35125d922f384a1baeea3fdb7d", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 128, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 128, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 8 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 4, "bytes": 16 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 8, "threads": 128, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 546, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.52100000000002, "control": 200.1245, "speedup": 0.9930702011204787 }, "gpu_us": { "candidate": 1.7916318029165268, "control": 1.6666599549353123, "speedup": 0.9302469135802469 } } }, { "frozen_register4": { "pairs": 506, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.02100000000002, "control": 197.5205, "speedup": 0.9874988126246743 }, "gpu_us": { "candidate": 1.7916318029165268, "control": 1.6666599549353123, "speedup": 0.9302469135802469 } } }, { "frozen_register4": { "pairs": 625, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 195.875, "control": 197.875, "speedup": 1.0102105934907466 }, "gpu_us": { "candidate": 1.7500133253633976, "control": 1.6666599549353123, "speedup": 0.9523698652918676 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.996879848311829, "round_speedups": [ 0.9930702011204787, 0.9874988126246743, 1.0102105934907466 ], "candidate": 199.12462507055443, "control": 198.50332603548406 }, "gpu_us": { "speedup": 0.937563532943953, "round_speedups": [ 0.9302469135802469, 0.9302469135802469, 0.9523698652918676 ], "candidate": 1.7776501499604982, "control": 1.6666599549353123 } } } }, { "name": "float32_1x1009", "dtype": "float32", "batches": 1, "width": 1009, "status": "measured", "variant": { "name": "register8_blocked4", "elements_per_thread": 8, "layout": "blocked4" }, "input_sha256": "72c4fd9244d1e3fe8e922e59cd98ff745af158f79bcd15c587482eb6749d4442", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 127;\n int _metile_register_index = int((((_metile_bounded_thread >> 7) & 1u) << 0) | (((_metile_bounded_thread >> 8) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 6) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 128;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 7) & 1u) << 0) | (((_metile_register_packed_ >> 8) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 6) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 256;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 7) & 1u) << 0) | (((_metile_register_packed__ >> 8) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 6) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 384;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 7) & 1u) << 0) | (((_metile_register_packed___ >> 8) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 6) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 512;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 7) & 1u) << 0) | (((_metile_register_packed____ >> 8) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 5) & 1u) << 7) | (((_metile_register_packed____ >> 6) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 640;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 7) & 1u) << 0) | (((_metile_register_packed_____ >> 8) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 5) & 1u) << 7) | (((_metile_register_packed_____ >> 6) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 768;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 7) & 1u) << 0) | (((_metile_register_packed______ >> 8) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 5) & 1u) << 7) | (((_metile_register_packed______ >> 6) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 896;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 7) & 1u) << 0) | (((_metile_register_packed_______ >> 8) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 5) & 1u) << 7) | (((_metile_register_packed_______ >> 6) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n float4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = float4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n float _metile_v20_r0 = _metile_vector_load[0];\n float _metile_v20_r1 = _metile_vector_load[1];\n float _metile_v20_r2 = _metile_vector_load[2];\n float _metile_v20_r3 = _metile_vector_load[3];\n float4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = float4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n float _metile_v20_r4 = _metile_vector_load_[0];\n float _metile_v20_r5 = _metile_vector_load_[1];\n float _metile_v20_r6 = _metile_vector_load_[2];\n float _metile_v20_r7 = _metile_vector_load_[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_____ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum______ = _metile_register_sum____ + _metile_register_sum_____;\n threadgroup float _metile_register_reduction[4];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 4u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n float4 _metile_vector_load__;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load__ = float4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load__[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load__[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load__[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load__[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n float _metile_v36_r0 = _metile_vector_load__[0];\n float _metile_v36_r1 = _metile_vector_load__[1];\n float _metile_v36_r2 = _metile_vector_load__[2];\n float _metile_v36_r3 = _metile_vector_load__[3];\n float4 _metile_vector_load___;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load___ = float4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load___[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load___[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load___[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load___[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n float _metile_v36_r4 = _metile_vector_load___[0];\n float _metile_v36_r5 = _metile_vector_load___[1];\n float _metile_v36_r6 = _metile_vector_load___[2];\n float _metile_v36_r7 = _metile_vector_load___[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_float4(float4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_float4(float4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n}", "source_sha256": "9f08087b05ab0b6f116b5c1e98de9acc212cb296d3daf05cb3d563f20cdce2ce", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 128, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 128, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 8 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 4, "bytes": 16 } ], "double_buffered": false, "vectorized_loads": 4, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 8, "threads": 128, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 4, "grouped_stores": 2 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 605, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.917, "control": 197.583, "speedup": 0.998312423894865 }, "gpu_us": { "candidate": 2.2500171326100826, "control": 1.6666599549353123, "speedup": 0.7407321174492304 } } }, { "frozen_register4": { "pairs": 545, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.083, "control": 200.541, "speedup": 1.0022890500442316 }, "gpu_us": { "candidate": 2.2500171326100826, "control": 1.6666599549353123, "speedup": 0.7407321174492304 } } }, { "frozen_register4": { "pairs": 616, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.3545, "control": 201.0205, "speedup": 1.003324108018537 }, "gpu_us": { "candidate": 2.2500171326100826, "control": 1.708336640149355, "speedup": 0.7592549476135041 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0013061949568716, "round_speedups": [ 0.998312423894865, 1.0022890500442316, 1.003324108018537 ], "candidate": 199.44851036793983, "control": 199.70902900633806 }, "gpu_us": { "speedup": 0.7468556325461561, "round_speedups": [ 0.7407321174492304, 0.7407321174492304, 0.7592549476135041 ], "candidate": 2.2500171326100826, "control": 1.6804379688151914 } } } }, { "name": "float32_1x1009", "dtype": "float32", "batches": 1, "width": 1009, "status": "measured", "variant": { "name": "register16_striped", "elements_per_thread": 16, "layout": "striped" }, "input_sha256": "72c4fd9244d1e3fe8e922e59cd98ff745af158f79bcd15c587482eb6749d4442", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 2.384185791015625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 63;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 64;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 128;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 192;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 256;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 320;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 384;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 448;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n int _metile_register_packed________ = _metile_bounded_thread + 512;\n int _metile_register_index________ = int(_metile_register_packed________);\n int _metile_register_packed_________ = _metile_bounded_thread + 576;\n int _metile_register_index_________ = int(_metile_register_packed_________);\n int _metile_register_packed__________ = _metile_bounded_thread + 640;\n int _metile_register_index__________ = int(_metile_register_packed__________);\n int _metile_register_packed___________ = _metile_bounded_thread + 704;\n int _metile_register_index___________ = int(_metile_register_packed___________);\n int _metile_register_packed____________ = _metile_bounded_thread + 768;\n int _metile_register_index____________ = int(_metile_register_packed____________);\n int _metile_register_packed_____________ = _metile_bounded_thread + 832;\n int _metile_register_index_____________ = int(_metile_register_packed_____________);\n int _metile_register_packed______________ = _metile_bounded_thread + 896;\n int _metile_register_index______________ = int(_metile_register_packed______________);\n int _metile_register_packed_______________ = _metile_bounded_thread + 960;\n int _metile_register_index_______________ = int(_metile_register_packed_______________);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v17_r8 = _metile_register_index________ < 1009;\n bool _metile_v17_r9 = _metile_register_index_________ < 1009;\n bool _metile_v17_r10 = _metile_register_index__________ < 1009;\n bool _metile_v17_r11 = _metile_register_index___________ < 1009;\n bool _metile_v17_r12 = _metile_register_index____________ < 1009;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v17_r14 = _metile_register_index______________ < 1009;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n float _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n float _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n float _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n float _metile_v20_r8 = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n float _metile_v20_r9 = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n float _metile_v20_r10 = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n float _metile_v20_r11 = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n float _metile_v20_r12 = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n float _metile_v20_r13 = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n float _metile_v20_r14 = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n float _metile_v20_r15 = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________ = _metile_register_sum____________ + _metile_register_sum_____________;\n threadgroup float _metile_register_reduction[2];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______________);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 2u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v33_r8 = _metile_register_index________ < 1009;\n bool _metile_v33_r9 = _metile_register_index_________ < 1009;\n bool _metile_v33_r10 = _metile_register_index__________ < 1009;\n bool _metile_v33_r11 = _metile_register_index___________ < 1009;\n bool _metile_v33_r12 = _metile_register_index____________ < 1009;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v33_r14 = _metile_register_index______________ < 1009;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n float _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n float _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n float _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n float _metile_v36_r8 = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n float _metile_v36_r9 = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n float _metile_v36_r10 = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n float _metile_v36_r11 = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n float _metile_v36_r12 = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n float _metile_v36_r13 = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n float _metile_v36_r14 = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n float _metile_v36_r15 = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v42_r8 = _metile_register_index________ < 1009;\n bool _metile_v42_r9 = _metile_register_index_________ < 1009;\n bool _metile_v42_r10 = _metile_register_index__________ < 1009;\n bool _metile_v42_r11 = _metile_register_index___________ < 1009;\n bool _metile_v42_r12 = _metile_register_index____________ < 1009;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v42_r14 = _metile_register_index______________ < 1009;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = _metile_v39_r8; }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = _metile_v39_r9; }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = _metile_v39_r10; }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = _metile_v39_r11; }\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = _metile_v39_r12; }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = _metile_v39_r13; }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = _metile_v39_r14; }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = _metile_v39_r15; }\n}", "source_sha256": "33426fa20c0c7f16979a8494e3077f7df7a4e0321c1045d73ed33afeb179b8e5", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 64, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 64, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 16 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 2, "bytes": 8 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 16, "threads": 64, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 622, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.27100000000002, "control": 197.35399999999998, "speedup": 1.0004207410110963 }, "gpu_us": { "candidate": 1.7916900105774403, "control": 1.625041477382183, "speedup": 0.9069880770605243 } } }, { "frozen_register4": { "pairs": 432, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.709, "control": 201.5, "speedup": 0.998963853868692 }, "gpu_us": { "candidate": 1.7916900105774403, "control": 1.6666599549353123, "speedup": 0.9302166921152659 } } }, { "frozen_register4": { "pairs": 620, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.64600000000002, "control": 199.25, "speedup": 1.003040584758817 }, "gpu_us": { "candidate": 1.7916900105774403, "control": 1.625041477382183, "speedup": 0.9069880770605243 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.000806972344622, "round_speedups": [ 1.0004207410110963, 0.998963853868692, 1.003040584758817 ], "candidate": 199.2000526761171, "control": 199.36080160967418 }, "gpu_us": { "speedup": 0.9146657733028515, "round_speedups": [ 0.9069880770605243, 0.9302166921152659, 0.9069880770605243 ], "candidate": 1.7916900105774403, "control": 1.6387975290438086 } } } }, { "name": "float32_1x1009", "dtype": "float32", "batches": 1, "width": 1009, "status": "measured", "variant": { "name": "register16_blocked4", "elements_per_thread": 16, "layout": "blocked4" }, "input_sha256": "72c4fd9244d1e3fe8e922e59cd98ff745af158f79bcd15c587482eb6749d4442", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 63;\n int _metile_register_index = int((((_metile_bounded_thread >> 6) & 1u) << 0) | (((_metile_bounded_thread >> 7) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 8) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 64;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 6) & 1u) << 0) | (((_metile_register_packed_ >> 7) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 8) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 128;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 6) & 1u) << 0) | (((_metile_register_packed__ >> 7) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 8) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 192;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 6) & 1u) << 0) | (((_metile_register_packed___ >> 7) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 8) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 256;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 6) & 1u) << 0) | (((_metile_register_packed____ >> 7) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 5) & 1u) << 7) | (((_metile_register_packed____ >> 8) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 320;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 6) & 1u) << 0) | (((_metile_register_packed_____ >> 7) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 5) & 1u) << 7) | (((_metile_register_packed_____ >> 8) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 384;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 6) & 1u) << 0) | (((_metile_register_packed______ >> 7) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 5) & 1u) << 7) | (((_metile_register_packed______ >> 8) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 448;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 6) & 1u) << 0) | (((_metile_register_packed_______ >> 7) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 5) & 1u) << 7) | (((_metile_register_packed_______ >> 8) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n int _metile_register_packed________ = _metile_bounded_thread + 512;\n int _metile_register_index________ = int((((_metile_register_packed________ >> 6) & 1u) << 0) | (((_metile_register_packed________ >> 7) & 1u) << 1) | (((_metile_register_packed________ >> 0) & 1u) << 2) | (((_metile_register_packed________ >> 1) & 1u) << 3) | (((_metile_register_packed________ >> 2) & 1u) << 4) | (((_metile_register_packed________ >> 3) & 1u) << 5) | (((_metile_register_packed________ >> 4) & 1u) << 6) | (((_metile_register_packed________ >> 5) & 1u) << 7) | (((_metile_register_packed________ >> 8) & 1u) << 8) | (((_metile_register_packed________ >> 9) & 1u) << 9));\n int _metile_register_packed_________ = _metile_bounded_thread + 576;\n int _metile_register_index_________ = int((((_metile_register_packed_________ >> 6) & 1u) << 0) | (((_metile_register_packed_________ >> 7) & 1u) << 1) | (((_metile_register_packed_________ >> 0) & 1u) << 2) | (((_metile_register_packed_________ >> 1) & 1u) << 3) | (((_metile_register_packed_________ >> 2) & 1u) << 4) | (((_metile_register_packed_________ >> 3) & 1u) << 5) | (((_metile_register_packed_________ >> 4) & 1u) << 6) | (((_metile_register_packed_________ >> 5) & 1u) << 7) | (((_metile_register_packed_________ >> 8) & 1u) << 8) | (((_metile_register_packed_________ >> 9) & 1u) << 9));\n int _metile_register_packed__________ = _metile_bounded_thread + 640;\n int _metile_register_index__________ = int((((_metile_register_packed__________ >> 6) & 1u) << 0) | (((_metile_register_packed__________ >> 7) & 1u) << 1) | (((_metile_register_packed__________ >> 0) & 1u) << 2) | (((_metile_register_packed__________ >> 1) & 1u) << 3) | (((_metile_register_packed__________ >> 2) & 1u) << 4) | (((_metile_register_packed__________ >> 3) & 1u) << 5) | (((_metile_register_packed__________ >> 4) & 1u) << 6) | (((_metile_register_packed__________ >> 5) & 1u) << 7) | (((_metile_register_packed__________ >> 8) & 1u) << 8) | (((_metile_register_packed__________ >> 9) & 1u) << 9));\n int _metile_register_packed___________ = _metile_bounded_thread + 704;\n int _metile_register_index___________ = int((((_metile_register_packed___________ >> 6) & 1u) << 0) | (((_metile_register_packed___________ >> 7) & 1u) << 1) | (((_metile_register_packed___________ >> 0) & 1u) << 2) | (((_metile_register_packed___________ >> 1) & 1u) << 3) | (((_metile_register_packed___________ >> 2) & 1u) << 4) | (((_metile_register_packed___________ >> 3) & 1u) << 5) | (((_metile_register_packed___________ >> 4) & 1u) << 6) | (((_metile_register_packed___________ >> 5) & 1u) << 7) | (((_metile_register_packed___________ >> 8) & 1u) << 8) | (((_metile_register_packed___________ >> 9) & 1u) << 9));\n int _metile_register_packed____________ = _metile_bounded_thread + 768;\n int _metile_register_index____________ = int((((_metile_register_packed____________ >> 6) & 1u) << 0) | (((_metile_register_packed____________ >> 7) & 1u) << 1) | (((_metile_register_packed____________ >> 0) & 1u) << 2) | (((_metile_register_packed____________ >> 1) & 1u) << 3) | (((_metile_register_packed____________ >> 2) & 1u) << 4) | (((_metile_register_packed____________ >> 3) & 1u) << 5) | (((_metile_register_packed____________ >> 4) & 1u) << 6) | (((_metile_register_packed____________ >> 5) & 1u) << 7) | (((_metile_register_packed____________ >> 8) & 1u) << 8) | (((_metile_register_packed____________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________ = _metile_bounded_thread + 832;\n int _metile_register_index_____________ = int((((_metile_register_packed_____________ >> 6) & 1u) << 0) | (((_metile_register_packed_____________ >> 7) & 1u) << 1) | (((_metile_register_packed_____________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________ >> 5) & 1u) << 7) | (((_metile_register_packed_____________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________ >> 9) & 1u) << 9));\n int _metile_register_packed______________ = _metile_bounded_thread + 896;\n int _metile_register_index______________ = int((((_metile_register_packed______________ >> 6) & 1u) << 0) | (((_metile_register_packed______________ >> 7) & 1u) << 1) | (((_metile_register_packed______________ >> 0) & 1u) << 2) | (((_metile_register_packed______________ >> 1) & 1u) << 3) | (((_metile_register_packed______________ >> 2) & 1u) << 4) | (((_metile_register_packed______________ >> 3) & 1u) << 5) | (((_metile_register_packed______________ >> 4) & 1u) << 6) | (((_metile_register_packed______________ >> 5) & 1u) << 7) | (((_metile_register_packed______________ >> 8) & 1u) << 8) | (((_metile_register_packed______________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________ = _metile_bounded_thread + 960;\n int _metile_register_index_______________ = int((((_metile_register_packed_______________ >> 6) & 1u) << 0) | (((_metile_register_packed_______________ >> 7) & 1u) << 1) | (((_metile_register_packed_______________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________ >> 5) & 1u) << 7) | (((_metile_register_packed_______________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v17_r8 = _metile_register_index________ < 1009;\n bool _metile_v17_r9 = _metile_register_index_________ < 1009;\n bool _metile_v17_r10 = _metile_register_index__________ < 1009;\n bool _metile_v17_r11 = _metile_register_index___________ < 1009;\n bool _metile_v17_r12 = _metile_register_index____________ < 1009;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v17_r14 = _metile_register_index______________ < 1009;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n float4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = float4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n float _metile_v20_r0 = _metile_vector_load[0];\n float _metile_v20_r1 = _metile_vector_load[1];\n float _metile_v20_r2 = _metile_vector_load[2];\n float _metile_v20_r3 = _metile_vector_load[3];\n float4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = float4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n float _metile_v20_r4 = _metile_vector_load_[0];\n float _metile_v20_r5 = _metile_vector_load_[1];\n float _metile_v20_r6 = _metile_vector_load_[2];\n float _metile_v20_r7 = _metile_vector_load_[3];\n float4 _metile_vector_load__;\n if ((_metile_v18_r8) && (_metile_v18_r9) && (_metile_v18_r10) && (_metile_v18_r11) && (long(_off__metile_v19_r9) == long(_off__metile_v19_r8) + 1) && (long(_off__metile_v19_r10) == long(_off__metile_v19_r8) + 2) && (long(_off__metile_v19_r11) == long(_off__metile_v19_r8) + 3)) {\n _metile_vector_load__ = float4(*reinterpret_cast(X + _off__metile_v19_r8));\n } else {\n _metile_vector_load__[0] = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n _metile_vector_load__[1] = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n _metile_vector_load__[2] = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n _metile_vector_load__[3] = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n }\n float _metile_v20_r8 = _metile_vector_load__[0];\n float _metile_v20_r9 = _metile_vector_load__[1];\n float _metile_v20_r10 = _metile_vector_load__[2];\n float _metile_v20_r11 = _metile_vector_load__[3];\n float4 _metile_vector_load___;\n if ((_metile_v18_r12) && (_metile_v18_r13) && (_metile_v18_r14) && (_metile_v18_r15) && (long(_off__metile_v19_r13) == long(_off__metile_v19_r12) + 1) && (long(_off__metile_v19_r14) == long(_off__metile_v19_r12) + 2) && (long(_off__metile_v19_r15) == long(_off__metile_v19_r12) + 3)) {\n _metile_vector_load___ = float4(*reinterpret_cast(X + _off__metile_v19_r12));\n } else {\n _metile_vector_load___[0] = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n _metile_vector_load___[1] = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n _metile_vector_load___[2] = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n _metile_vector_load___[3] = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n }\n float _metile_v20_r12 = _metile_vector_load___[0];\n float _metile_v20_r13 = _metile_vector_load___[1];\n float _metile_v20_r14 = _metile_vector_load___[2];\n float _metile_v20_r15 = _metile_vector_load___[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________ = _metile_register_sum____________ + _metile_register_sum_____________;\n threadgroup float _metile_register_reduction[2];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______________);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 2u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v33_r8 = _metile_register_index________ < 1009;\n bool _metile_v33_r9 = _metile_register_index_________ < 1009;\n bool _metile_v33_r10 = _metile_register_index__________ < 1009;\n bool _metile_v33_r11 = _metile_register_index___________ < 1009;\n bool _metile_v33_r12 = _metile_register_index____________ < 1009;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v33_r14 = _metile_register_index______________ < 1009;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n float4 _metile_vector_load____;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load____ = float4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load____[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load____[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load____[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load____[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n float _metile_v36_r0 = _metile_vector_load____[0];\n float _metile_v36_r1 = _metile_vector_load____[1];\n float _metile_v36_r2 = _metile_vector_load____[2];\n float _metile_v36_r3 = _metile_vector_load____[3];\n float4 _metile_vector_load_____;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load_____ = float4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load_____[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load_____[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load_____[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load_____[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n float _metile_v36_r4 = _metile_vector_load_____[0];\n float _metile_v36_r5 = _metile_vector_load_____[1];\n float _metile_v36_r6 = _metile_vector_load_____[2];\n float _metile_v36_r7 = _metile_vector_load_____[3];\n float4 _metile_vector_load______;\n if ((_metile_v34_r8) && (_metile_v34_r9) && (_metile_v34_r10) && (_metile_v34_r11) && (long(_metile_register_index_________) == long(_metile_register_index________) + 1) && (long(_metile_register_index__________) == long(_metile_register_index________) + 2) && (long(_metile_register_index___________) == long(_metile_register_index________) + 3)) {\n _metile_vector_load______ = float4(*reinterpret_cast(W + _metile_register_index________));\n } else {\n _metile_vector_load______[0] = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n _metile_vector_load______[1] = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n _metile_vector_load______[2] = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n _metile_vector_load______[3] = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n }\n float _metile_v36_r8 = _metile_vector_load______[0];\n float _metile_v36_r9 = _metile_vector_load______[1];\n float _metile_v36_r10 = _metile_vector_load______[2];\n float _metile_v36_r11 = _metile_vector_load______[3];\n float4 _metile_vector_load_______;\n if ((_metile_v34_r12) && (_metile_v34_r13) && (_metile_v34_r14) && (_metile_v34_r15) && (long(_metile_register_index_____________) == long(_metile_register_index____________) + 1) && (long(_metile_register_index______________) == long(_metile_register_index____________) + 2) && (long(_metile_register_index_______________) == long(_metile_register_index____________) + 3)) {\n _metile_vector_load_______ = float4(*reinterpret_cast(W + _metile_register_index____________));\n } else {\n _metile_vector_load_______[0] = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n _metile_vector_load_______[1] = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n _metile_vector_load_______[2] = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n _metile_vector_load_______[3] = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n }\n float _metile_v36_r12 = _metile_vector_load_______[0];\n float _metile_v36_r13 = _metile_vector_load_______[1];\n float _metile_v36_r14 = _metile_vector_load_______[2];\n float _metile_v36_r15 = _metile_vector_load_______[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v42_r8 = _metile_register_index________ < 1009;\n bool _metile_v42_r9 = _metile_register_index_________ < 1009;\n bool _metile_v42_r10 = _metile_register_index__________ < 1009;\n bool _metile_v42_r11 = _metile_register_index___________ < 1009;\n bool _metile_v42_r12 = _metile_register_index____________ < 1009;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v42_r14 = _metile_register_index______________ < 1009;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_float4(float4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_float4(float4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n if ((_metile_v43_r8) && (_metile_v43_r9) && (_metile_v43_r10) && (_metile_v43_r11) && (long(_off__metile_v44_r9) == long(_off__metile_v44_r8) + 1) && (long(_off__metile_v44_r10) == long(_off__metile_v44_r8) + 2) && (long(_off__metile_v44_r11) == long(_off__metile_v44_r8) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r8) = packed_float4(float4(static_cast(_metile_v39_r8), static_cast(_metile_v39_r9), static_cast(_metile_v39_r10), static_cast(_metile_v39_r11)));\n } else {\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = static_cast(_metile_v39_r8); }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = static_cast(_metile_v39_r9); }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = static_cast(_metile_v39_r10); }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = static_cast(_metile_v39_r11); }\n }\n if ((_metile_v43_r12) && (_metile_v43_r13) && (_metile_v43_r14) && (_metile_v43_r15) && (long(_off__metile_v44_r13) == long(_off__metile_v44_r12) + 1) && (long(_off__metile_v44_r14) == long(_off__metile_v44_r12) + 2) && (long(_off__metile_v44_r15) == long(_off__metile_v44_r12) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r12) = packed_float4(float4(static_cast(_metile_v39_r12), static_cast(_metile_v39_r13), static_cast(_metile_v39_r14), static_cast(_metile_v39_r15)));\n } else {\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = static_cast(_metile_v39_r12); }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = static_cast(_metile_v39_r13); }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = static_cast(_metile_v39_r14); }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = static_cast(_metile_v39_r15); }\n }\n}", "source_sha256": "2617a2e2182b7192b8def8bf914a9cd9d48eed7adf610815901d9692d304fd01", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 64, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 64, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 16 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 2, "bytes": 8 } ], "double_buffered": false, "vectorized_loads": 8, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 16, "threads": 64, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 8, "grouped_stores": 4 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 624, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.542, "control": 197.27100000000002, "speedup": 0.9986281398386166 }, "gpu_us": { "candidate": 2.8333161026239395, "control": 1.6666599549353123, "speedup": 0.5882365025885447 } } }, { "frozen_register4": { "pairs": 340, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.958, "control": 200.08350000000002, "speedup": 1.0056569728284361 }, "gpu_us": { "candidate": 2.833374310284853, "control": 1.6666599549353123, "speedup": 0.5882244181030055 } } }, { "frozen_register4": { "pairs": 618, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 196.41649999999998, "control": 197.083, "speedup": 1.003393299442766 }, "gpu_us": { "candidate": 2.833374310284853, "control": 1.6666599549353123, "speedup": 0.5882244181030055 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.002555187413235, "round_speedups": [ 0.9986281398386166, 1.0056569728284361, 1.003393299442766 ], "candidate": 197.63609927131694, "control": 198.14109654457584 }, "gpu_us": { "speedup": 0.5882284462372673, "round_speedups": [ 0.5882365025885447, 0.5882244181030055, 0.5882244181030055 ], "candidate": 2.8333549075983475, "control": 1.6666599549353123 } } } }, { "name": "float32_32x1009", "dtype": "float32", "batches": 32, "width": 1009, "status": "measured", "variant": { "name": "register32_blocked4", "elements_per_thread": 32, "layout": "blocked4" }, "input_sha256": "41fd264c427e4e182eaad0b6751f90d1477b7e8f193b298a4dc8ccbfebb45ec3", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 31;\n int _metile_register_index = int((((_metile_bounded_thread >> 5) & 1u) << 0) | (((_metile_bounded_thread >> 6) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 7) & 1u) << 7) | (((_metile_bounded_thread >> 8) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 32;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 5) & 1u) << 0) | (((_metile_register_packed_ >> 6) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 7) & 1u) << 7) | (((_metile_register_packed_ >> 8) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 64;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 5) & 1u) << 0) | (((_metile_register_packed__ >> 6) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 7) & 1u) << 7) | (((_metile_register_packed__ >> 8) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 96;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 5) & 1u) << 0) | (((_metile_register_packed___ >> 6) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 7) & 1u) << 7) | (((_metile_register_packed___ >> 8) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 128;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 5) & 1u) << 0) | (((_metile_register_packed____ >> 6) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 7) & 1u) << 7) | (((_metile_register_packed____ >> 8) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 160;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 5) & 1u) << 0) | (((_metile_register_packed_____ >> 6) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 7) & 1u) << 7) | (((_metile_register_packed_____ >> 8) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 192;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 5) & 1u) << 0) | (((_metile_register_packed______ >> 6) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 7) & 1u) << 7) | (((_metile_register_packed______ >> 8) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 224;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 5) & 1u) << 0) | (((_metile_register_packed_______ >> 6) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 7) & 1u) << 7) | (((_metile_register_packed_______ >> 8) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n int _metile_register_packed________ = _metile_bounded_thread + 256;\n int _metile_register_index________ = int((((_metile_register_packed________ >> 5) & 1u) << 0) | (((_metile_register_packed________ >> 6) & 1u) << 1) | (((_metile_register_packed________ >> 0) & 1u) << 2) | (((_metile_register_packed________ >> 1) & 1u) << 3) | (((_metile_register_packed________ >> 2) & 1u) << 4) | (((_metile_register_packed________ >> 3) & 1u) << 5) | (((_metile_register_packed________ >> 4) & 1u) << 6) | (((_metile_register_packed________ >> 7) & 1u) << 7) | (((_metile_register_packed________ >> 8) & 1u) << 8) | (((_metile_register_packed________ >> 9) & 1u) << 9));\n int _metile_register_packed_________ = _metile_bounded_thread + 288;\n int _metile_register_index_________ = int((((_metile_register_packed_________ >> 5) & 1u) << 0) | (((_metile_register_packed_________ >> 6) & 1u) << 1) | (((_metile_register_packed_________ >> 0) & 1u) << 2) | (((_metile_register_packed_________ >> 1) & 1u) << 3) | (((_metile_register_packed_________ >> 2) & 1u) << 4) | (((_metile_register_packed_________ >> 3) & 1u) << 5) | (((_metile_register_packed_________ >> 4) & 1u) << 6) | (((_metile_register_packed_________ >> 7) & 1u) << 7) | (((_metile_register_packed_________ >> 8) & 1u) << 8) | (((_metile_register_packed_________ >> 9) & 1u) << 9));\n int _metile_register_packed__________ = _metile_bounded_thread + 320;\n int _metile_register_index__________ = int((((_metile_register_packed__________ >> 5) & 1u) << 0) | (((_metile_register_packed__________ >> 6) & 1u) << 1) | (((_metile_register_packed__________ >> 0) & 1u) << 2) | (((_metile_register_packed__________ >> 1) & 1u) << 3) | (((_metile_register_packed__________ >> 2) & 1u) << 4) | (((_metile_register_packed__________ >> 3) & 1u) << 5) | (((_metile_register_packed__________ >> 4) & 1u) << 6) | (((_metile_register_packed__________ >> 7) & 1u) << 7) | (((_metile_register_packed__________ >> 8) & 1u) << 8) | (((_metile_register_packed__________ >> 9) & 1u) << 9));\n int _metile_register_packed___________ = _metile_bounded_thread + 352;\n int _metile_register_index___________ = int((((_metile_register_packed___________ >> 5) & 1u) << 0) | (((_metile_register_packed___________ >> 6) & 1u) << 1) | (((_metile_register_packed___________ >> 0) & 1u) << 2) | (((_metile_register_packed___________ >> 1) & 1u) << 3) | (((_metile_register_packed___________ >> 2) & 1u) << 4) | (((_metile_register_packed___________ >> 3) & 1u) << 5) | (((_metile_register_packed___________ >> 4) & 1u) << 6) | (((_metile_register_packed___________ >> 7) & 1u) << 7) | (((_metile_register_packed___________ >> 8) & 1u) << 8) | (((_metile_register_packed___________ >> 9) & 1u) << 9));\n int _metile_register_packed____________ = _metile_bounded_thread + 384;\n int _metile_register_index____________ = int((((_metile_register_packed____________ >> 5) & 1u) << 0) | (((_metile_register_packed____________ >> 6) & 1u) << 1) | (((_metile_register_packed____________ >> 0) & 1u) << 2) | (((_metile_register_packed____________ >> 1) & 1u) << 3) | (((_metile_register_packed____________ >> 2) & 1u) << 4) | (((_metile_register_packed____________ >> 3) & 1u) << 5) | (((_metile_register_packed____________ >> 4) & 1u) << 6) | (((_metile_register_packed____________ >> 7) & 1u) << 7) | (((_metile_register_packed____________ >> 8) & 1u) << 8) | (((_metile_register_packed____________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________ = _metile_bounded_thread + 416;\n int _metile_register_index_____________ = int((((_metile_register_packed_____________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________ >> 9) & 1u) << 9));\n int _metile_register_packed______________ = _metile_bounded_thread + 448;\n int _metile_register_index______________ = int((((_metile_register_packed______________ >> 5) & 1u) << 0) | (((_metile_register_packed______________ >> 6) & 1u) << 1) | (((_metile_register_packed______________ >> 0) & 1u) << 2) | (((_metile_register_packed______________ >> 1) & 1u) << 3) | (((_metile_register_packed______________ >> 2) & 1u) << 4) | (((_metile_register_packed______________ >> 3) & 1u) << 5) | (((_metile_register_packed______________ >> 4) & 1u) << 6) | (((_metile_register_packed______________ >> 7) & 1u) << 7) | (((_metile_register_packed______________ >> 8) & 1u) << 8) | (((_metile_register_packed______________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________ = _metile_bounded_thread + 480;\n int _metile_register_index_______________ = int((((_metile_register_packed_______________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________ >> 9) & 1u) << 9));\n int _metile_register_packed________________ = _metile_bounded_thread + 512;\n int _metile_register_index________________ = int((((_metile_register_packed________________ >> 5) & 1u) << 0) | (((_metile_register_packed________________ >> 6) & 1u) << 1) | (((_metile_register_packed________________ >> 0) & 1u) << 2) | (((_metile_register_packed________________ >> 1) & 1u) << 3) | (((_metile_register_packed________________ >> 2) & 1u) << 4) | (((_metile_register_packed________________ >> 3) & 1u) << 5) | (((_metile_register_packed________________ >> 4) & 1u) << 6) | (((_metile_register_packed________________ >> 7) & 1u) << 7) | (((_metile_register_packed________________ >> 8) & 1u) << 8) | (((_metile_register_packed________________ >> 9) & 1u) << 9));\n int _metile_register_packed_________________ = _metile_bounded_thread + 544;\n int _metile_register_index_________________ = int((((_metile_register_packed_________________ >> 5) & 1u) << 0) | (((_metile_register_packed_________________ >> 6) & 1u) << 1) | (((_metile_register_packed_________________ >> 0) & 1u) << 2) | (((_metile_register_packed_________________ >> 1) & 1u) << 3) | (((_metile_register_packed_________________ >> 2) & 1u) << 4) | (((_metile_register_packed_________________ >> 3) & 1u) << 5) | (((_metile_register_packed_________________ >> 4) & 1u) << 6) | (((_metile_register_packed_________________ >> 7) & 1u) << 7) | (((_metile_register_packed_________________ >> 8) & 1u) << 8) | (((_metile_register_packed_________________ >> 9) & 1u) << 9));\n int _metile_register_packed__________________ = _metile_bounded_thread + 576;\n int _metile_register_index__________________ = int((((_metile_register_packed__________________ >> 5) & 1u) << 0) | (((_metile_register_packed__________________ >> 6) & 1u) << 1) | (((_metile_register_packed__________________ >> 0) & 1u) << 2) | (((_metile_register_packed__________________ >> 1) & 1u) << 3) | (((_metile_register_packed__________________ >> 2) & 1u) << 4) | (((_metile_register_packed__________________ >> 3) & 1u) << 5) | (((_metile_register_packed__________________ >> 4) & 1u) << 6) | (((_metile_register_packed__________________ >> 7) & 1u) << 7) | (((_metile_register_packed__________________ >> 8) & 1u) << 8) | (((_metile_register_packed__________________ >> 9) & 1u) << 9));\n int _metile_register_packed___________________ = _metile_bounded_thread + 608;\n int _metile_register_index___________________ = int((((_metile_register_packed___________________ >> 5) & 1u) << 0) | (((_metile_register_packed___________________ >> 6) & 1u) << 1) | (((_metile_register_packed___________________ >> 0) & 1u) << 2) | (((_metile_register_packed___________________ >> 1) & 1u) << 3) | (((_metile_register_packed___________________ >> 2) & 1u) << 4) | (((_metile_register_packed___________________ >> 3) & 1u) << 5) | (((_metile_register_packed___________________ >> 4) & 1u) << 6) | (((_metile_register_packed___________________ >> 7) & 1u) << 7) | (((_metile_register_packed___________________ >> 8) & 1u) << 8) | (((_metile_register_packed___________________ >> 9) & 1u) << 9));\n int _metile_register_packed____________________ = _metile_bounded_thread + 640;\n int _metile_register_index____________________ = int((((_metile_register_packed____________________ >> 5) & 1u) << 0) | (((_metile_register_packed____________________ >> 6) & 1u) << 1) | (((_metile_register_packed____________________ >> 0) & 1u) << 2) | (((_metile_register_packed____________________ >> 1) & 1u) << 3) | (((_metile_register_packed____________________ >> 2) & 1u) << 4) | (((_metile_register_packed____________________ >> 3) & 1u) << 5) | (((_metile_register_packed____________________ >> 4) & 1u) << 6) | (((_metile_register_packed____________________ >> 7) & 1u) << 7) | (((_metile_register_packed____________________ >> 8) & 1u) << 8) | (((_metile_register_packed____________________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________________ = _metile_bounded_thread + 672;\n int _metile_register_index_____________________ = int((((_metile_register_packed_____________________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________________ >> 9) & 1u) << 9));\n int _metile_register_packed______________________ = _metile_bounded_thread + 704;\n int _metile_register_index______________________ = int((((_metile_register_packed______________________ >> 5) & 1u) << 0) | (((_metile_register_packed______________________ >> 6) & 1u) << 1) | (((_metile_register_packed______________________ >> 0) & 1u) << 2) | (((_metile_register_packed______________________ >> 1) & 1u) << 3) | (((_metile_register_packed______________________ >> 2) & 1u) << 4) | (((_metile_register_packed______________________ >> 3) & 1u) << 5) | (((_metile_register_packed______________________ >> 4) & 1u) << 6) | (((_metile_register_packed______________________ >> 7) & 1u) << 7) | (((_metile_register_packed______________________ >> 8) & 1u) << 8) | (((_metile_register_packed______________________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________________ = _metile_bounded_thread + 736;\n int _metile_register_index_______________________ = int((((_metile_register_packed_______________________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________________ >> 9) & 1u) << 9));\n int _metile_register_packed________________________ = _metile_bounded_thread + 768;\n int _metile_register_index________________________ = int((((_metile_register_packed________________________ >> 5) & 1u) << 0) | (((_metile_register_packed________________________ >> 6) & 1u) << 1) | (((_metile_register_packed________________________ >> 0) & 1u) << 2) | (((_metile_register_packed________________________ >> 1) & 1u) << 3) | (((_metile_register_packed________________________ >> 2) & 1u) << 4) | (((_metile_register_packed________________________ >> 3) & 1u) << 5) | (((_metile_register_packed________________________ >> 4) & 1u) << 6) | (((_metile_register_packed________________________ >> 7) & 1u) << 7) | (((_metile_register_packed________________________ >> 8) & 1u) << 8) | (((_metile_register_packed________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_________________________ = _metile_bounded_thread + 800;\n int _metile_register_index_________________________ = int((((_metile_register_packed_________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_________________________ >> 9) & 1u) << 9));\n int _metile_register_packed__________________________ = _metile_bounded_thread + 832;\n int _metile_register_index__________________________ = int((((_metile_register_packed__________________________ >> 5) & 1u) << 0) | (((_metile_register_packed__________________________ >> 6) & 1u) << 1) | (((_metile_register_packed__________________________ >> 0) & 1u) << 2) | (((_metile_register_packed__________________________ >> 1) & 1u) << 3) | (((_metile_register_packed__________________________ >> 2) & 1u) << 4) | (((_metile_register_packed__________________________ >> 3) & 1u) << 5) | (((_metile_register_packed__________________________ >> 4) & 1u) << 6) | (((_metile_register_packed__________________________ >> 7) & 1u) << 7) | (((_metile_register_packed__________________________ >> 8) & 1u) << 8) | (((_metile_register_packed__________________________ >> 9) & 1u) << 9));\n int _metile_register_packed___________________________ = _metile_bounded_thread + 864;\n int _metile_register_index___________________________ = int((((_metile_register_packed___________________________ >> 5) & 1u) << 0) | (((_metile_register_packed___________________________ >> 6) & 1u) << 1) | (((_metile_register_packed___________________________ >> 0) & 1u) << 2) | (((_metile_register_packed___________________________ >> 1) & 1u) << 3) | (((_metile_register_packed___________________________ >> 2) & 1u) << 4) | (((_metile_register_packed___________________________ >> 3) & 1u) << 5) | (((_metile_register_packed___________________________ >> 4) & 1u) << 6) | (((_metile_register_packed___________________________ >> 7) & 1u) << 7) | (((_metile_register_packed___________________________ >> 8) & 1u) << 8) | (((_metile_register_packed___________________________ >> 9) & 1u) << 9));\n int _metile_register_packed____________________________ = _metile_bounded_thread + 896;\n int _metile_register_index____________________________ = int((((_metile_register_packed____________________________ >> 5) & 1u) << 0) | (((_metile_register_packed____________________________ >> 6) & 1u) << 1) | (((_metile_register_packed____________________________ >> 0) & 1u) << 2) | (((_metile_register_packed____________________________ >> 1) & 1u) << 3) | (((_metile_register_packed____________________________ >> 2) & 1u) << 4) | (((_metile_register_packed____________________________ >> 3) & 1u) << 5) | (((_metile_register_packed____________________________ >> 4) & 1u) << 6) | (((_metile_register_packed____________________________ >> 7) & 1u) << 7) | (((_metile_register_packed____________________________ >> 8) & 1u) << 8) | (((_metile_register_packed____________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________________________ = _metile_bounded_thread + 928;\n int _metile_register_index_____________________________ = int((((_metile_register_packed_____________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________________________ >> 9) & 1u) << 9));\n int _metile_register_packed______________________________ = _metile_bounded_thread + 960;\n int _metile_register_index______________________________ = int((((_metile_register_packed______________________________ >> 5) & 1u) << 0) | (((_metile_register_packed______________________________ >> 6) & 1u) << 1) | (((_metile_register_packed______________________________ >> 0) & 1u) << 2) | (((_metile_register_packed______________________________ >> 1) & 1u) << 3) | (((_metile_register_packed______________________________ >> 2) & 1u) << 4) | (((_metile_register_packed______________________________ >> 3) & 1u) << 5) | (((_metile_register_packed______________________________ >> 4) & 1u) << 6) | (((_metile_register_packed______________________________ >> 7) & 1u) << 7) | (((_metile_register_packed______________________________ >> 8) & 1u) << 8) | (((_metile_register_packed______________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________________________ = _metile_bounded_thread + 992;\n int _metile_register_index_______________________________ = int((((_metile_register_packed_______________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________________________ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v16_r16 = _metile_register_index________________ >= 0;\n bool _metile_v16_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v16_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v16_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v16_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v16_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v16_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v16_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v16_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v16_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v16_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v16_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v16_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v16_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v16_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v16_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v17_r8 = _metile_register_index________ < 1009;\n bool _metile_v17_r9 = _metile_register_index_________ < 1009;\n bool _metile_v17_r10 = _metile_register_index__________ < 1009;\n bool _metile_v17_r11 = _metile_register_index___________ < 1009;\n bool _metile_v17_r12 = _metile_register_index____________ < 1009;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v17_r14 = _metile_register_index______________ < 1009;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v17_r16 = _metile_register_index________________ < 1009;\n bool _metile_v17_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v17_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v17_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v17_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v17_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v17_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v17_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v17_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v17_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v17_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v17_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v17_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v17_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v17_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v17_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n bool _metile_v18_r16 = _metile_v16_r16 & _metile_v17_r16;\n bool _metile_v18_r17 = _metile_v16_r17 & _metile_v17_r17;\n bool _metile_v18_r18 = _metile_v16_r18 & _metile_v17_r18;\n bool _metile_v18_r19 = _metile_v16_r19 & _metile_v17_r19;\n bool _metile_v18_r20 = _metile_v16_r20 & _metile_v17_r20;\n bool _metile_v18_r21 = _metile_v16_r21 & _metile_v17_r21;\n bool _metile_v18_r22 = _metile_v16_r22 & _metile_v17_r22;\n bool _metile_v18_r23 = _metile_v16_r23 & _metile_v17_r23;\n bool _metile_v18_r24 = _metile_v16_r24 & _metile_v17_r24;\n bool _metile_v18_r25 = _metile_v16_r25 & _metile_v17_r25;\n bool _metile_v18_r26 = _metile_v16_r26 & _metile_v17_r26;\n bool _metile_v18_r27 = _metile_v16_r27 & _metile_v17_r27;\n bool _metile_v18_r28 = _metile_v16_r28 & _metile_v17_r28;\n bool _metile_v18_r29 = _metile_v16_r29 & _metile_v17_r29;\n bool _metile_v18_r30 = _metile_v16_r30 & _metile_v17_r30;\n bool _metile_v18_r31 = _metile_v16_r31 & _metile_v17_r31;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n int _off__metile_v19_r16 = v2 + _metile_register_index________________;\n int _off__metile_v19_r17 = v2 + _metile_register_index_________________;\n int _off__metile_v19_r18 = v2 + _metile_register_index__________________;\n int _off__metile_v19_r19 = v2 + _metile_register_index___________________;\n int _off__metile_v19_r20 = v2 + _metile_register_index____________________;\n int _off__metile_v19_r21 = v2 + _metile_register_index_____________________;\n int _off__metile_v19_r22 = v2 + _metile_register_index______________________;\n int _off__metile_v19_r23 = v2 + _metile_register_index_______________________;\n int _off__metile_v19_r24 = v2 + _metile_register_index________________________;\n int _off__metile_v19_r25 = v2 + _metile_register_index_________________________;\n int _off__metile_v19_r26 = v2 + _metile_register_index__________________________;\n int _off__metile_v19_r27 = v2 + _metile_register_index___________________________;\n int _off__metile_v19_r28 = v2 + _metile_register_index____________________________;\n int _off__metile_v19_r29 = v2 + _metile_register_index_____________________________;\n int _off__metile_v19_r30 = v2 + _metile_register_index______________________________;\n int _off__metile_v19_r31 = v2 + _metile_register_index_______________________________;\n float4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = float4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n float _metile_v20_r0 = _metile_vector_load[0];\n float _metile_v20_r1 = _metile_vector_load[1];\n float _metile_v20_r2 = _metile_vector_load[2];\n float _metile_v20_r3 = _metile_vector_load[3];\n float4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = float4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n float _metile_v20_r4 = _metile_vector_load_[0];\n float _metile_v20_r5 = _metile_vector_load_[1];\n float _metile_v20_r6 = _metile_vector_load_[2];\n float _metile_v20_r7 = _metile_vector_load_[3];\n float4 _metile_vector_load__;\n if ((_metile_v18_r8) && (_metile_v18_r9) && (_metile_v18_r10) && (_metile_v18_r11) && (long(_off__metile_v19_r9) == long(_off__metile_v19_r8) + 1) && (long(_off__metile_v19_r10) == long(_off__metile_v19_r8) + 2) && (long(_off__metile_v19_r11) == long(_off__metile_v19_r8) + 3)) {\n _metile_vector_load__ = float4(*reinterpret_cast(X + _off__metile_v19_r8));\n } else {\n _metile_vector_load__[0] = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n _metile_vector_load__[1] = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n _metile_vector_load__[2] = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n _metile_vector_load__[3] = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n }\n float _metile_v20_r8 = _metile_vector_load__[0];\n float _metile_v20_r9 = _metile_vector_load__[1];\n float _metile_v20_r10 = _metile_vector_load__[2];\n float _metile_v20_r11 = _metile_vector_load__[3];\n float4 _metile_vector_load___;\n if ((_metile_v18_r12) && (_metile_v18_r13) && (_metile_v18_r14) && (_metile_v18_r15) && (long(_off__metile_v19_r13) == long(_off__metile_v19_r12) + 1) && (long(_off__metile_v19_r14) == long(_off__metile_v19_r12) + 2) && (long(_off__metile_v19_r15) == long(_off__metile_v19_r12) + 3)) {\n _metile_vector_load___ = float4(*reinterpret_cast(X + _off__metile_v19_r12));\n } else {\n _metile_vector_load___[0] = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n _metile_vector_load___[1] = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n _metile_vector_load___[2] = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n _metile_vector_load___[3] = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n }\n float _metile_v20_r12 = _metile_vector_load___[0];\n float _metile_v20_r13 = _metile_vector_load___[1];\n float _metile_v20_r14 = _metile_vector_load___[2];\n float _metile_v20_r15 = _metile_vector_load___[3];\n float4 _metile_vector_load____;\n if ((_metile_v18_r16) && (_metile_v18_r17) && (_metile_v18_r18) && (_metile_v18_r19) && (long(_off__metile_v19_r17) == long(_off__metile_v19_r16) + 1) && (long(_off__metile_v19_r18) == long(_off__metile_v19_r16) + 2) && (long(_off__metile_v19_r19) == long(_off__metile_v19_r16) + 3)) {\n _metile_vector_load____ = float4(*reinterpret_cast(X + _off__metile_v19_r16));\n } else {\n _metile_vector_load____[0] = _metile_v18_r16 ? X[_off__metile_v19_r16] : static_cast(0);\n _metile_vector_load____[1] = _metile_v18_r17 ? X[_off__metile_v19_r17] : static_cast(0);\n _metile_vector_load____[2] = _metile_v18_r18 ? X[_off__metile_v19_r18] : static_cast(0);\n _metile_vector_load____[3] = _metile_v18_r19 ? X[_off__metile_v19_r19] : static_cast(0);\n }\n float _metile_v20_r16 = _metile_vector_load____[0];\n float _metile_v20_r17 = _metile_vector_load____[1];\n float _metile_v20_r18 = _metile_vector_load____[2];\n float _metile_v20_r19 = _metile_vector_load____[3];\n float4 _metile_vector_load_____;\n if ((_metile_v18_r20) && (_metile_v18_r21) && (_metile_v18_r22) && (_metile_v18_r23) && (long(_off__metile_v19_r21) == long(_off__metile_v19_r20) + 1) && (long(_off__metile_v19_r22) == long(_off__metile_v19_r20) + 2) && (long(_off__metile_v19_r23) == long(_off__metile_v19_r20) + 3)) {\n _metile_vector_load_____ = float4(*reinterpret_cast(X + _off__metile_v19_r20));\n } else {\n _metile_vector_load_____[0] = _metile_v18_r20 ? X[_off__metile_v19_r20] : static_cast(0);\n _metile_vector_load_____[1] = _metile_v18_r21 ? X[_off__metile_v19_r21] : static_cast(0);\n _metile_vector_load_____[2] = _metile_v18_r22 ? X[_off__metile_v19_r22] : static_cast(0);\n _metile_vector_load_____[3] = _metile_v18_r23 ? X[_off__metile_v19_r23] : static_cast(0);\n }\n float _metile_v20_r20 = _metile_vector_load_____[0];\n float _metile_v20_r21 = _metile_vector_load_____[1];\n float _metile_v20_r22 = _metile_vector_load_____[2];\n float _metile_v20_r23 = _metile_vector_load_____[3];\n float4 _metile_vector_load______;\n if ((_metile_v18_r24) && (_metile_v18_r25) && (_metile_v18_r26) && (_metile_v18_r27) && (long(_off__metile_v19_r25) == long(_off__metile_v19_r24) + 1) && (long(_off__metile_v19_r26) == long(_off__metile_v19_r24) + 2) && (long(_off__metile_v19_r27) == long(_off__metile_v19_r24) + 3)) {\n _metile_vector_load______ = float4(*reinterpret_cast(X + _off__metile_v19_r24));\n } else {\n _metile_vector_load______[0] = _metile_v18_r24 ? X[_off__metile_v19_r24] : static_cast(0);\n _metile_vector_load______[1] = _metile_v18_r25 ? X[_off__metile_v19_r25] : static_cast(0);\n _metile_vector_load______[2] = _metile_v18_r26 ? X[_off__metile_v19_r26] : static_cast(0);\n _metile_vector_load______[3] = _metile_v18_r27 ? X[_off__metile_v19_r27] : static_cast(0);\n }\n float _metile_v20_r24 = _metile_vector_load______[0];\n float _metile_v20_r25 = _metile_vector_load______[1];\n float _metile_v20_r26 = _metile_vector_load______[2];\n float _metile_v20_r27 = _metile_vector_load______[3];\n float4 _metile_vector_load_______;\n if ((_metile_v18_r28) && (_metile_v18_r29) && (_metile_v18_r30) && (_metile_v18_r31) && (long(_off__metile_v19_r29) == long(_off__metile_v19_r28) + 1) && (long(_off__metile_v19_r30) == long(_off__metile_v19_r28) + 2) && (long(_off__metile_v19_r31) == long(_off__metile_v19_r28) + 3)) {\n _metile_vector_load_______ = float4(*reinterpret_cast(X + _off__metile_v19_r28));\n } else {\n _metile_vector_load_______[0] = _metile_v18_r28 ? X[_off__metile_v19_r28] : static_cast(0);\n _metile_vector_load_______[1] = _metile_v18_r29 ? X[_off__metile_v19_r29] : static_cast(0);\n _metile_vector_load_______[2] = _metile_v18_r30 ? X[_off__metile_v19_r30] : static_cast(0);\n _metile_vector_load_______[3] = _metile_v18_r31 ? X[_off__metile_v19_r31] : static_cast(0);\n }\n float _metile_v20_r28 = _metile_vector_load_______[0];\n float _metile_v20_r29 = _metile_vector_load_______[1];\n float _metile_v20_r30 = _metile_vector_load_______[2];\n float _metile_v20_r31 = _metile_vector_load_______[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v21_r16 = static_cast(_metile_v20_r16);\n float _metile_v21_r17 = static_cast(_metile_v20_r17);\n float _metile_v21_r18 = static_cast(_metile_v20_r18);\n float _metile_v21_r19 = static_cast(_metile_v20_r19);\n float _metile_v21_r20 = static_cast(_metile_v20_r20);\n float _metile_v21_r21 = static_cast(_metile_v20_r21);\n float _metile_v21_r22 = static_cast(_metile_v20_r22);\n float _metile_v21_r23 = static_cast(_metile_v20_r23);\n float _metile_v21_r24 = static_cast(_metile_v20_r24);\n float _metile_v21_r25 = static_cast(_metile_v20_r25);\n float _metile_v21_r26 = static_cast(_metile_v20_r26);\n float _metile_v21_r27 = static_cast(_metile_v20_r27);\n float _metile_v21_r28 = static_cast(_metile_v20_r28);\n float _metile_v21_r29 = static_cast(_metile_v20_r29);\n float _metile_v21_r30 = static_cast(_metile_v20_r30);\n float _metile_v21_r31 = static_cast(_metile_v20_r31);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_v22_r16 = _metile_v21_r16 * _metile_v21_r16;\n float _metile_v22_r17 = _metile_v21_r17 * _metile_v21_r17;\n float _metile_v22_r18 = _metile_v21_r18 * _metile_v21_r18;\n float _metile_v22_r19 = _metile_v21_r19 * _metile_v21_r19;\n float _metile_v22_r20 = _metile_v21_r20 * _metile_v21_r20;\n float _metile_v22_r21 = _metile_v21_r21 * _metile_v21_r21;\n float _metile_v22_r22 = _metile_v21_r22 * _metile_v21_r22;\n float _metile_v22_r23 = _metile_v21_r23 * _metile_v21_r23;\n float _metile_v22_r24 = _metile_v21_r24 * _metile_v21_r24;\n float _metile_v22_r25 = _metile_v21_r25 * _metile_v21_r25;\n float _metile_v22_r26 = _metile_v21_r26 * _metile_v21_r26;\n float _metile_v22_r27 = _metile_v21_r27 * _metile_v21_r27;\n float _metile_v22_r28 = _metile_v21_r28 * _metile_v21_r28;\n float _metile_v22_r29 = _metile_v21_r29 * _metile_v21_r29;\n float _metile_v22_r30 = _metile_v21_r30 * _metile_v21_r30;\n float _metile_v22_r31 = _metile_v21_r31 * _metile_v21_r31;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_v22_r16 + _metile_v22_r17;\n float _metile_register_sum_________ = _metile_v22_r18 + _metile_v22_r19;\n float _metile_register_sum__________ = _metile_v22_r20 + _metile_v22_r21;\n float _metile_register_sum___________ = _metile_v22_r22 + _metile_v22_r23;\n float _metile_register_sum____________ = _metile_v22_r24 + _metile_v22_r25;\n float _metile_register_sum_____________ = _metile_v22_r26 + _metile_v22_r27;\n float _metile_register_sum______________ = _metile_v22_r28 + _metile_v22_r29;\n float _metile_register_sum_______________ = _metile_v22_r30 + _metile_v22_r31;\n float _metile_register_sum________________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________________ = _metile_register_sum____________ + _metile_register_sum_____________;\n float _metile_register_sum_______________________ = _metile_register_sum______________ + _metile_register_sum_______________;\n float _metile_register_sum________________________ = _metile_register_sum________________ + _metile_register_sum_________________;\n float _metile_register_sum_________________________ = _metile_register_sum__________________ + _metile_register_sum___________________;\n float _metile_register_sum__________________________ = _metile_register_sum____________________ + _metile_register_sum_____________________;\n float _metile_register_sum___________________________ = _metile_register_sum______________________ + _metile_register_sum_______________________;\n float _metile_register_sum____________________________ = _metile_register_sum________________________ + _metile_register_sum_________________________;\n float _metile_register_sum_____________________________ = _metile_register_sum__________________________ + _metile_register_sum___________________________;\n float _metile_register_sum______________________________ = _metile_register_sum____________________________ + _metile_register_sum_____________________________;\n float v23 = simd_sum(_metile_register_sum______________________________);\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v32_r16 = _metile_register_index________________ >= 0;\n bool _metile_v32_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v32_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v32_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v32_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v32_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v32_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v32_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v32_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v32_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v32_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v32_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v32_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v32_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v32_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v32_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v33_r8 = _metile_register_index________ < 1009;\n bool _metile_v33_r9 = _metile_register_index_________ < 1009;\n bool _metile_v33_r10 = _metile_register_index__________ < 1009;\n bool _metile_v33_r11 = _metile_register_index___________ < 1009;\n bool _metile_v33_r12 = _metile_register_index____________ < 1009;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v33_r14 = _metile_register_index______________ < 1009;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v33_r16 = _metile_register_index________________ < 1009;\n bool _metile_v33_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v33_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v33_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v33_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v33_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v33_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v33_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v33_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v33_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v33_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v33_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v33_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v33_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v33_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v33_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n bool _metile_v34_r16 = _metile_v32_r16 & _metile_v33_r16;\n bool _metile_v34_r17 = _metile_v32_r17 & _metile_v33_r17;\n bool _metile_v34_r18 = _metile_v32_r18 & _metile_v33_r18;\n bool _metile_v34_r19 = _metile_v32_r19 & _metile_v33_r19;\n bool _metile_v34_r20 = _metile_v32_r20 & _metile_v33_r20;\n bool _metile_v34_r21 = _metile_v32_r21 & _metile_v33_r21;\n bool _metile_v34_r22 = _metile_v32_r22 & _metile_v33_r22;\n bool _metile_v34_r23 = _metile_v32_r23 & _metile_v33_r23;\n bool _metile_v34_r24 = _metile_v32_r24 & _metile_v33_r24;\n bool _metile_v34_r25 = _metile_v32_r25 & _metile_v33_r25;\n bool _metile_v34_r26 = _metile_v32_r26 & _metile_v33_r26;\n bool _metile_v34_r27 = _metile_v32_r27 & _metile_v33_r27;\n bool _metile_v34_r28 = _metile_v32_r28 & _metile_v33_r28;\n bool _metile_v34_r29 = _metile_v32_r29 & _metile_v33_r29;\n bool _metile_v34_r30 = _metile_v32_r30 & _metile_v33_r30;\n bool _metile_v34_r31 = _metile_v32_r31 & _metile_v33_r31;\n float4 _metile_vector_load________;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load________ = float4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load________[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load________[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load________[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load________[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n float _metile_v36_r0 = _metile_vector_load________[0];\n float _metile_v36_r1 = _metile_vector_load________[1];\n float _metile_v36_r2 = _metile_vector_load________[2];\n float _metile_v36_r3 = _metile_vector_load________[3];\n float4 _metile_vector_load_________;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load_________ = float4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load_________[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load_________[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load_________[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load_________[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n float _metile_v36_r4 = _metile_vector_load_________[0];\n float _metile_v36_r5 = _metile_vector_load_________[1];\n float _metile_v36_r6 = _metile_vector_load_________[2];\n float _metile_v36_r7 = _metile_vector_load_________[3];\n float4 _metile_vector_load__________;\n if ((_metile_v34_r8) && (_metile_v34_r9) && (_metile_v34_r10) && (_metile_v34_r11) && (long(_metile_register_index_________) == long(_metile_register_index________) + 1) && (long(_metile_register_index__________) == long(_metile_register_index________) + 2) && (long(_metile_register_index___________) == long(_metile_register_index________) + 3)) {\n _metile_vector_load__________ = float4(*reinterpret_cast(W + _metile_register_index________));\n } else {\n _metile_vector_load__________[0] = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n _metile_vector_load__________[1] = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n _metile_vector_load__________[2] = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n _metile_vector_load__________[3] = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n }\n float _metile_v36_r8 = _metile_vector_load__________[0];\n float _metile_v36_r9 = _metile_vector_load__________[1];\n float _metile_v36_r10 = _metile_vector_load__________[2];\n float _metile_v36_r11 = _metile_vector_load__________[3];\n float4 _metile_vector_load___________;\n if ((_metile_v34_r12) && (_metile_v34_r13) && (_metile_v34_r14) && (_metile_v34_r15) && (long(_metile_register_index_____________) == long(_metile_register_index____________) + 1) && (long(_metile_register_index______________) == long(_metile_register_index____________) + 2) && (long(_metile_register_index_______________) == long(_metile_register_index____________) + 3)) {\n _metile_vector_load___________ = float4(*reinterpret_cast(W + _metile_register_index____________));\n } else {\n _metile_vector_load___________[0] = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n _metile_vector_load___________[1] = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n _metile_vector_load___________[2] = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n _metile_vector_load___________[3] = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n }\n float _metile_v36_r12 = _metile_vector_load___________[0];\n float _metile_v36_r13 = _metile_vector_load___________[1];\n float _metile_v36_r14 = _metile_vector_load___________[2];\n float _metile_v36_r15 = _metile_vector_load___________[3];\n float4 _metile_vector_load____________;\n if ((_metile_v34_r16) && (_metile_v34_r17) && (_metile_v34_r18) && (_metile_v34_r19) && (long(_metile_register_index_________________) == long(_metile_register_index________________) + 1) && (long(_metile_register_index__________________) == long(_metile_register_index________________) + 2) && (long(_metile_register_index___________________) == long(_metile_register_index________________) + 3)) {\n _metile_vector_load____________ = float4(*reinterpret_cast(W + _metile_register_index________________));\n } else {\n _metile_vector_load____________[0] = _metile_v34_r16 ? W[_metile_register_index________________] : static_cast(0);\n _metile_vector_load____________[1] = _metile_v34_r17 ? W[_metile_register_index_________________] : static_cast(0);\n _metile_vector_load____________[2] = _metile_v34_r18 ? W[_metile_register_index__________________] : static_cast(0);\n _metile_vector_load____________[3] = _metile_v34_r19 ? W[_metile_register_index___________________] : static_cast(0);\n }\n float _metile_v36_r16 = _metile_vector_load____________[0];\n float _metile_v36_r17 = _metile_vector_load____________[1];\n float _metile_v36_r18 = _metile_vector_load____________[2];\n float _metile_v36_r19 = _metile_vector_load____________[3];\n float4 _metile_vector_load_____________;\n if ((_metile_v34_r20) && (_metile_v34_r21) && (_metile_v34_r22) && (_metile_v34_r23) && (long(_metile_register_index_____________________) == long(_metile_register_index____________________) + 1) && (long(_metile_register_index______________________) == long(_metile_register_index____________________) + 2) && (long(_metile_register_index_______________________) == long(_metile_register_index____________________) + 3)) {\n _metile_vector_load_____________ = float4(*reinterpret_cast(W + _metile_register_index____________________));\n } else {\n _metile_vector_load_____________[0] = _metile_v34_r20 ? W[_metile_register_index____________________] : static_cast(0);\n _metile_vector_load_____________[1] = _metile_v34_r21 ? W[_metile_register_index_____________________] : static_cast(0);\n _metile_vector_load_____________[2] = _metile_v34_r22 ? W[_metile_register_index______________________] : static_cast(0);\n _metile_vector_load_____________[3] = _metile_v34_r23 ? W[_metile_register_index_______________________] : static_cast(0);\n }\n float _metile_v36_r20 = _metile_vector_load_____________[0];\n float _metile_v36_r21 = _metile_vector_load_____________[1];\n float _metile_v36_r22 = _metile_vector_load_____________[2];\n float _metile_v36_r23 = _metile_vector_load_____________[3];\n float4 _metile_vector_load______________;\n if ((_metile_v34_r24) && (_metile_v34_r25) && (_metile_v34_r26) && (_metile_v34_r27) && (long(_metile_register_index_________________________) == long(_metile_register_index________________________) + 1) && (long(_metile_register_index__________________________) == long(_metile_register_index________________________) + 2) && (long(_metile_register_index___________________________) == long(_metile_register_index________________________) + 3)) {\n _metile_vector_load______________ = float4(*reinterpret_cast(W + _metile_register_index________________________));\n } else {\n _metile_vector_load______________[0] = _metile_v34_r24 ? W[_metile_register_index________________________] : static_cast(0);\n _metile_vector_load______________[1] = _metile_v34_r25 ? W[_metile_register_index_________________________] : static_cast(0);\n _metile_vector_load______________[2] = _metile_v34_r26 ? W[_metile_register_index__________________________] : static_cast(0);\n _metile_vector_load______________[3] = _metile_v34_r27 ? W[_metile_register_index___________________________] : static_cast(0);\n }\n float _metile_v36_r24 = _metile_vector_load______________[0];\n float _metile_v36_r25 = _metile_vector_load______________[1];\n float _metile_v36_r26 = _metile_vector_load______________[2];\n float _metile_v36_r27 = _metile_vector_load______________[3];\n float4 _metile_vector_load_______________;\n if ((_metile_v34_r28) && (_metile_v34_r29) && (_metile_v34_r30) && (_metile_v34_r31) && (long(_metile_register_index_____________________________) == long(_metile_register_index____________________________) + 1) && (long(_metile_register_index______________________________) == long(_metile_register_index____________________________) + 2) && (long(_metile_register_index_______________________________) == long(_metile_register_index____________________________) + 3)) {\n _metile_vector_load_______________ = float4(*reinterpret_cast(W + _metile_register_index____________________________));\n } else {\n _metile_vector_load_______________[0] = _metile_v34_r28 ? W[_metile_register_index____________________________] : static_cast(0);\n _metile_vector_load_______________[1] = _metile_v34_r29 ? W[_metile_register_index_____________________________] : static_cast(0);\n _metile_vector_load_______________[2] = _metile_v34_r30 ? W[_metile_register_index______________________________] : static_cast(0);\n _metile_vector_load_______________[3] = _metile_v34_r31 ? W[_metile_register_index_______________________________] : static_cast(0);\n }\n float _metile_v36_r28 = _metile_vector_load_______________[0];\n float _metile_v36_r29 = _metile_vector_load_______________[1];\n float _metile_v36_r30 = _metile_vector_load_______________[2];\n float _metile_v36_r31 = _metile_vector_load_______________[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v37_r16 = static_cast(_metile_v36_r16);\n float _metile_v37_r17 = static_cast(_metile_v36_r17);\n float _metile_v37_r18 = static_cast(_metile_v36_r18);\n float _metile_v37_r19 = static_cast(_metile_v36_r19);\n float _metile_v37_r20 = static_cast(_metile_v36_r20);\n float _metile_v37_r21 = static_cast(_metile_v36_r21);\n float _metile_v37_r22 = static_cast(_metile_v36_r22);\n float _metile_v37_r23 = static_cast(_metile_v36_r23);\n float _metile_v37_r24 = static_cast(_metile_v36_r24);\n float _metile_v37_r25 = static_cast(_metile_v36_r25);\n float _metile_v37_r26 = static_cast(_metile_v36_r26);\n float _metile_v37_r27 = static_cast(_metile_v36_r27);\n float _metile_v37_r28 = static_cast(_metile_v36_r28);\n float _metile_v37_r29 = static_cast(_metile_v36_r29);\n float _metile_v37_r30 = static_cast(_metile_v36_r30);\n float _metile_v37_r31 = static_cast(_metile_v36_r31);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v38_r16 = _metile_v21_r16 * v29;\n float _metile_v38_r17 = _metile_v21_r17 * v29;\n float _metile_v38_r18 = _metile_v21_r18 * v29;\n float _metile_v38_r19 = _metile_v21_r19 * v29;\n float _metile_v38_r20 = _metile_v21_r20 * v29;\n float _metile_v38_r21 = _metile_v21_r21 * v29;\n float _metile_v38_r22 = _metile_v21_r22 * v29;\n float _metile_v38_r23 = _metile_v21_r23 * v29;\n float _metile_v38_r24 = _metile_v21_r24 * v29;\n float _metile_v38_r25 = _metile_v21_r25 * v29;\n float _metile_v38_r26 = _metile_v21_r26 * v29;\n float _metile_v38_r27 = _metile_v21_r27 * v29;\n float _metile_v38_r28 = _metile_v21_r28 * v29;\n float _metile_v38_r29 = _metile_v21_r29 * v29;\n float _metile_v38_r30 = _metile_v21_r30 * v29;\n float _metile_v38_r31 = _metile_v21_r31 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n float _metile_v39_r16 = _metile_v38_r16 * _metile_v37_r16;\n float _metile_v39_r17 = _metile_v38_r17 * _metile_v37_r17;\n float _metile_v39_r18 = _metile_v38_r18 * _metile_v37_r18;\n float _metile_v39_r19 = _metile_v38_r19 * _metile_v37_r19;\n float _metile_v39_r20 = _metile_v38_r20 * _metile_v37_r20;\n float _metile_v39_r21 = _metile_v38_r21 * _metile_v37_r21;\n float _metile_v39_r22 = _metile_v38_r22 * _metile_v37_r22;\n float _metile_v39_r23 = _metile_v38_r23 * _metile_v37_r23;\n float _metile_v39_r24 = _metile_v38_r24 * _metile_v37_r24;\n float _metile_v39_r25 = _metile_v38_r25 * _metile_v37_r25;\n float _metile_v39_r26 = _metile_v38_r26 * _metile_v37_r26;\n float _metile_v39_r27 = _metile_v38_r27 * _metile_v37_r27;\n float _metile_v39_r28 = _metile_v38_r28 * _metile_v37_r28;\n float _metile_v39_r29 = _metile_v38_r29 * _metile_v37_r29;\n float _metile_v39_r30 = _metile_v38_r30 * _metile_v37_r30;\n float _metile_v39_r31 = _metile_v38_r31 * _metile_v37_r31;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v41_r16 = _metile_register_index________________ >= 0;\n bool _metile_v41_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v41_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v41_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v41_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v41_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v41_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v41_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v41_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v41_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v41_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v41_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v41_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v41_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v41_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v41_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v42_r8 = _metile_register_index________ < 1009;\n bool _metile_v42_r9 = _metile_register_index_________ < 1009;\n bool _metile_v42_r10 = _metile_register_index__________ < 1009;\n bool _metile_v42_r11 = _metile_register_index___________ < 1009;\n bool _metile_v42_r12 = _metile_register_index____________ < 1009;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v42_r14 = _metile_register_index______________ < 1009;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v42_r16 = _metile_register_index________________ < 1009;\n bool _metile_v42_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v42_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v42_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v42_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v42_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v42_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v42_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v42_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v42_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v42_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v42_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v42_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v42_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v42_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v42_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n bool _metile_v43_r16 = _metile_v41_r16 & _metile_v42_r16;\n bool _metile_v43_r17 = _metile_v41_r17 & _metile_v42_r17;\n bool _metile_v43_r18 = _metile_v41_r18 & _metile_v42_r18;\n bool _metile_v43_r19 = _metile_v41_r19 & _metile_v42_r19;\n bool _metile_v43_r20 = _metile_v41_r20 & _metile_v42_r20;\n bool _metile_v43_r21 = _metile_v41_r21 & _metile_v42_r21;\n bool _metile_v43_r22 = _metile_v41_r22 & _metile_v42_r22;\n bool _metile_v43_r23 = _metile_v41_r23 & _metile_v42_r23;\n bool _metile_v43_r24 = _metile_v41_r24 & _metile_v42_r24;\n bool _metile_v43_r25 = _metile_v41_r25 & _metile_v42_r25;\n bool _metile_v43_r26 = _metile_v41_r26 & _metile_v42_r26;\n bool _metile_v43_r27 = _metile_v41_r27 & _metile_v42_r27;\n bool _metile_v43_r28 = _metile_v41_r28 & _metile_v42_r28;\n bool _metile_v43_r29 = _metile_v41_r29 & _metile_v42_r29;\n bool _metile_v43_r30 = _metile_v41_r30 & _metile_v42_r30;\n bool _metile_v43_r31 = _metile_v41_r31 & _metile_v42_r31;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n int _off__metile_v44_r16 = v9 + _metile_register_index________________;\n int _off__metile_v44_r17 = v9 + _metile_register_index_________________;\n int _off__metile_v44_r18 = v9 + _metile_register_index__________________;\n int _off__metile_v44_r19 = v9 + _metile_register_index___________________;\n int _off__metile_v44_r20 = v9 + _metile_register_index____________________;\n int _off__metile_v44_r21 = v9 + _metile_register_index_____________________;\n int _off__metile_v44_r22 = v9 + _metile_register_index______________________;\n int _off__metile_v44_r23 = v9 + _metile_register_index_______________________;\n int _off__metile_v44_r24 = v9 + _metile_register_index________________________;\n int _off__metile_v44_r25 = v9 + _metile_register_index_________________________;\n int _off__metile_v44_r26 = v9 + _metile_register_index__________________________;\n int _off__metile_v44_r27 = v9 + _metile_register_index___________________________;\n int _off__metile_v44_r28 = v9 + _metile_register_index____________________________;\n int _off__metile_v44_r29 = v9 + _metile_register_index_____________________________;\n int _off__metile_v44_r30 = v9 + _metile_register_index______________________________;\n int _off__metile_v44_r31 = v9 + _metile_register_index_______________________________;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_float4(float4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_float4(float4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n if ((_metile_v43_r8) && (_metile_v43_r9) && (_metile_v43_r10) && (_metile_v43_r11) && (long(_off__metile_v44_r9) == long(_off__metile_v44_r8) + 1) && (long(_off__metile_v44_r10) == long(_off__metile_v44_r8) + 2) && (long(_off__metile_v44_r11) == long(_off__metile_v44_r8) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r8) = packed_float4(float4(static_cast(_metile_v39_r8), static_cast(_metile_v39_r9), static_cast(_metile_v39_r10), static_cast(_metile_v39_r11)));\n } else {\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = static_cast(_metile_v39_r8); }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = static_cast(_metile_v39_r9); }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = static_cast(_metile_v39_r10); }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = static_cast(_metile_v39_r11); }\n }\n if ((_metile_v43_r12) && (_metile_v43_r13) && (_metile_v43_r14) && (_metile_v43_r15) && (long(_off__metile_v44_r13) == long(_off__metile_v44_r12) + 1) && (long(_off__metile_v44_r14) == long(_off__metile_v44_r12) + 2) && (long(_off__metile_v44_r15) == long(_off__metile_v44_r12) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r12) = packed_float4(float4(static_cast(_metile_v39_r12), static_cast(_metile_v39_r13), static_cast(_metile_v39_r14), static_cast(_metile_v39_r15)));\n } else {\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = static_cast(_metile_v39_r12); }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = static_cast(_metile_v39_r13); }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = static_cast(_metile_v39_r14); }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = static_cast(_metile_v39_r15); }\n }\n if ((_metile_v43_r16) && (_metile_v43_r17) && (_metile_v43_r18) && (_metile_v43_r19) && (long(_off__metile_v44_r17) == long(_off__metile_v44_r16) + 1) && (long(_off__metile_v44_r18) == long(_off__metile_v44_r16) + 2) && (long(_off__metile_v44_r19) == long(_off__metile_v44_r16) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r16) = packed_float4(float4(static_cast(_metile_v39_r16), static_cast(_metile_v39_r17), static_cast(_metile_v39_r18), static_cast(_metile_v39_r19)));\n } else {\n if (_metile_v43_r16) { Out[_off__metile_v44_r16] = static_cast(_metile_v39_r16); }\n if (_metile_v43_r17) { Out[_off__metile_v44_r17] = static_cast(_metile_v39_r17); }\n if (_metile_v43_r18) { Out[_off__metile_v44_r18] = static_cast(_metile_v39_r18); }\n if (_metile_v43_r19) { Out[_off__metile_v44_r19] = static_cast(_metile_v39_r19); }\n }\n if ((_metile_v43_r20) && (_metile_v43_r21) && (_metile_v43_r22) && (_metile_v43_r23) && (long(_off__metile_v44_r21) == long(_off__metile_v44_r20) + 1) && (long(_off__metile_v44_r22) == long(_off__metile_v44_r20) + 2) && (long(_off__metile_v44_r23) == long(_off__metile_v44_r20) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r20) = packed_float4(float4(static_cast(_metile_v39_r20), static_cast(_metile_v39_r21), static_cast(_metile_v39_r22), static_cast(_metile_v39_r23)));\n } else {\n if (_metile_v43_r20) { Out[_off__metile_v44_r20] = static_cast(_metile_v39_r20); }\n if (_metile_v43_r21) { Out[_off__metile_v44_r21] = static_cast(_metile_v39_r21); }\n if (_metile_v43_r22) { Out[_off__metile_v44_r22] = static_cast(_metile_v39_r22); }\n if (_metile_v43_r23) { Out[_off__metile_v44_r23] = static_cast(_metile_v39_r23); }\n }\n if ((_metile_v43_r24) && (_metile_v43_r25) && (_metile_v43_r26) && (_metile_v43_r27) && (long(_off__metile_v44_r25) == long(_off__metile_v44_r24) + 1) && (long(_off__metile_v44_r26) == long(_off__metile_v44_r24) + 2) && (long(_off__metile_v44_r27) == long(_off__metile_v44_r24) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r24) = packed_float4(float4(static_cast(_metile_v39_r24), static_cast(_metile_v39_r25), static_cast(_metile_v39_r26), static_cast(_metile_v39_r27)));\n } else {\n if (_metile_v43_r24) { Out[_off__metile_v44_r24] = static_cast(_metile_v39_r24); }\n if (_metile_v43_r25) { Out[_off__metile_v44_r25] = static_cast(_metile_v39_r25); }\n if (_metile_v43_r26) { Out[_off__metile_v44_r26] = static_cast(_metile_v39_r26); }\n if (_metile_v43_r27) { Out[_off__metile_v44_r27] = static_cast(_metile_v39_r27); }\n }\n if ((_metile_v43_r28) && (_metile_v43_r29) && (_metile_v43_r30) && (_metile_v43_r31) && (long(_off__metile_v44_r29) == long(_off__metile_v44_r28) + 1) && (long(_off__metile_v44_r30) == long(_off__metile_v44_r28) + 2) && (long(_off__metile_v44_r31) == long(_off__metile_v44_r28) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r28) = packed_float4(float4(static_cast(_metile_v39_r28), static_cast(_metile_v39_r29), static_cast(_metile_v39_r30), static_cast(_metile_v39_r31)));\n } else {\n if (_metile_v43_r28) { Out[_off__metile_v44_r28] = static_cast(_metile_v39_r28); }\n if (_metile_v43_r29) { Out[_off__metile_v44_r29] = static_cast(_metile_v39_r29); }\n if (_metile_v43_r30) { Out[_off__metile_v44_r30] = static_cast(_metile_v39_r30); }\n if (_metile_v43_r31) { Out[_off__metile_v44_r31] = static_cast(_metile_v39_r31); }\n }\n}", "source_sha256": "8205038bf6ba3e8bd71e472a270b8fc036d7a98adf4a40b12e66c4dc7e4b1644", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 32, 1, 1 ], "is_gemm": false, "prefer_ordered": false, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 32, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 32 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [], "double_buffered": false, "vectorized_loads": 16, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 32, "threads": 32, "scratch": null, "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 16, "grouped_stores": 8 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 609, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.333, "control": 199.167, "speedup": 0.9892417040425564 }, "gpu_us": { "candidate": 4.20835567638278, "control": 2.41666566580534, "speedup": 0.5742541390613978 } } }, { "frozen_register4": { "pairs": 592, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.75, "control": 197.89600000000002, "speedup": 0.9857833125778332 }, "gpu_us": { "candidate": 4.249974153935909, "control": 2.41666566580534, "speedup": 0.5686306735694524 } } }, { "frozen_register4": { "pairs": 550, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.91649999999998, "control": 202.187, "speedup": 1.0013396626823465 }, "gpu_us": { "candidate": 4.249974153935909, "control": 2.41666566580534, "speedup": 0.5686306735694524 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9920991995749917, "round_speedups": [ 0.9892417040425564, 0.9857833125778332, 1.0013396626823465 ], "candidate": 201.33260345220495, "control": 199.74191473328162 }, "gpu_us": { "speedup": 0.570499016551263, "round_speedups": [ 0.5742541390613978, 0.5686306735694524, 0.5686306735694524 ], "candidate": 4.236055796229733, "control": 2.41666566580534 } } } }, { "name": "float32_32x1009", "dtype": "float32", "batches": 32, "width": 1009, "status": "measured", "variant": { "name": "register2_striped", "elements_per_thread": 2, "layout": "striped" }, "input_sha256": "41fd264c427e4e182eaad0b6751f90d1477b7e8f193b298a4dc8ccbfebb45ec3", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 511;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 512;\n int _metile_register_index_ = int(_metile_register_packed_);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n threadgroup float _metile_register_reduction[16];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 16u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n}", "source_sha256": "9bc3eb88c124547d7881e3d6279f1602e263cfc0456cb6238d2c206b0f83ac05", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 512, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 512, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 2 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 16, "bytes": 64 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 2, "threads": 512, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 610, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.042, "control": 200.39600000000002, "speedup": 1.0017696283780406 }, "gpu_us": { "candidate": 2.374988980591297, "control": 2.41666566580534, "speedup": 1.0175481594039508 } } }, { "frozen_register4": { "pairs": 539, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.667, "control": 201.042, "speedup": 0.9969008315688734 }, "gpu_us": { "candidate": 2.374988980591297, "control": 2.41666566580534, "speedup": 1.0175481594039508 } } }, { "frozen_register4": { "pairs": 618, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.083, "control": 197.10399999999998, "speedup": 1.0001065540914233 }, "gpu_us": { "candidate": 2.374988980591297, "control": 2.41666566580534, "speedup": 1.0175481594039508 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9995902946343103, "round_speedups": [ 1.0017696283780406, 0.9969008315688734, 1.0001065540914233 ], "candidate": 199.58829280053197, "control": 199.50652040604265 }, "gpu_us": { "speedup": 1.0175481594039508, "round_speedups": [ 1.0175481594039508, 1.0175481594039508, 1.0175481594039508 ], "candidate": 2.374988980591297, "control": 2.41666566580534 } } } }, { "name": "float32_32x1009", "dtype": "float32", "batches": 32, "width": 1009, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "41fd264c427e4e182eaad0b6751f90d1477b7e8f193b298a4dc8ccbfebb45ec3", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "c1d33e27fc56debd55c6a508dc39b24b01c51c4f01d8ebe463b73c7d94ad343d", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 592, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.54149999999998, "control": 200.958, "speedup": 1.0020768768559127 }, "gpu_us": { "candidate": 2.374988980591297, "control": 2.41666566580534, "speedup": 1.0175481594039508 } } }, { "frozen_register4": { "pairs": 623, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.5, "control": 196.542, "speedup": 0.9951493670886076 }, "gpu_us": { "candidate": 2.333370503038168, "control": 2.41666566580534, "speedup": 1.0356973582458153 } } }, { "frozen_register4": { "pairs": 621, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.042, "control": 197.375, "speedup": 0.9966320275497117 }, "gpu_us": { "candidate": 2.333370503038168, "control": 2.3750471882522106, "speedup": 1.017861151994412 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9979483178760784, "round_speedups": [ 1.0020768768559127, 0.9951493670886076, 0.9966320275497117 ], "candidate": 198.69009657201633, "control": 198.28244765267928 }, "gpu_us": { "speedup": 1.0236672132231097, "round_speedups": [ 1.0175481594039508, 1.0356973582458153, 1.017861151994412 ], "candidate": 2.3471616570585554, "control": 2.4027124324652678 } } } }, { "name": "float32_32x1009", "dtype": "float32", "batches": 32, "width": 1009, "status": "measured", "variant": { "name": "register4_blocked4", "elements_per_thread": 4, "layout": "blocked4" }, "input_sha256": "41fd264c427e4e182eaad0b6751f90d1477b7e8f193b298a4dc8ccbfebb45ec3", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int((((_metile_bounded_thread >> 8) & 1u) << 0) | (((_metile_bounded_thread >> 9) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 6) & 1u) << 8) | (((_metile_bounded_thread >> 7) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 8) & 1u) << 0) | (((_metile_register_packed_ >> 9) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 6) & 1u) << 8) | (((_metile_register_packed_ >> 7) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 8) & 1u) << 0) | (((_metile_register_packed__ >> 9) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 6) & 1u) << 8) | (((_metile_register_packed__ >> 7) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 8) & 1u) << 0) | (((_metile_register_packed___ >> 9) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 6) & 1u) << 8) | (((_metile_register_packed___ >> 7) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = float4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n float _metile_v20_r0 = _metile_vector_load[0];\n float _metile_v20_r1 = _metile_vector_load[1];\n float _metile_v20_r2 = _metile_vector_load[2];\n float _metile_v20_r3 = _metile_vector_load[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float4 _metile_vector_load_;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load_ = float4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load_[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load_[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load_[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load_[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n float _metile_v36_r0 = _metile_vector_load_[0];\n float _metile_v36_r1 = _metile_vector_load_[1];\n float _metile_v36_r2 = _metile_vector_load_[2];\n float _metile_v36_r3 = _metile_vector_load_[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_float4(float4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n}", "source_sha256": "9c1852dfc63c9d26d086e577f959fcc52d4398d11ea3c1c13748f723d2747516", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 2, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 2, "grouped_stores": 1 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 301, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 268.375, "control": 274.54200000000003, "speedup": 1.0229790405216583 }, "gpu_us": { "candidate": 10.374991688877344, "control": 8.66665504872799, "speedup": 0.8353409148287992 } } }, { "frozen_register4": { "pairs": 521, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 205.625, "control": 207.042, "speedup": 1.0068911854103344 }, "gpu_us": { "candidate": 2.874992787837982, "control": 2.500019036233425, "speedup": 0.8695740200842241 } } }, { "frozen_register4": { "pairs": 539, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 206.459, "control": 206.875, "speedup": 1.002014927903361 }, "gpu_us": { "candidate": 2.7500209398567677, "control": 2.4583423510193825, "speedup": 0.8939358662292306 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0105888185335494, "round_speedups": [ 1.0229790405216583, 1.0068911854103344, 1.002014927903361 ], "candidate": 225.01800196345403, "control": 227.4006767530268 }, "gpu_us": { "speedup": 0.8659488184085343, "round_speedups": [ 0.8353409148287992, 0.8695740200842241, 0.8939358662292306 ], "candidate": 4.344970570984865, "control": 3.7625221319641975 } } } }, { "name": "float32_32x1009", "dtype": "float32", "batches": 32, "width": 1009, "status": "measured", "variant": { "name": "register8_striped", "elements_per_thread": 8, "layout": "striped" }, "input_sha256": "41fd264c427e4e182eaad0b6751f90d1477b7e8f193b298a4dc8ccbfebb45ec3", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 4.76837158203125e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 127;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 128;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 256;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 384;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 512;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 640;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 768;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 896;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n float _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n float _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n float _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_____ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum______ = _metile_register_sum____ + _metile_register_sum_____;\n threadgroup float _metile_register_reduction[4];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 4u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n float _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n float _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n float _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n}", "source_sha256": "81a1ee1fc79ce28ef50cf43c835b1d4e5d87eb35125d922f384a1baeea3fdb7d", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 128, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 128, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 8 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 4, "bytes": 16 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 8, "threads": 128, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 483, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 210.417, "control": 209.958, "speedup": 0.9978186173170419 }, "gpu_us": { "candidate": 2.4583423510193825, "control": 2.41666566580534, "speedup": 0.9830468343041152 } } }, { "frozen_register4": { "pairs": 576, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 209.584, "control": 205.313, "speedup": 0.979621535995114 }, "gpu_us": { "candidate": 2.4583423510193825, "control": 2.41666566580534, "speedup": 0.9830468343041152 } } }, { "frozen_register4": { "pairs": 598, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.35399999999998, "control": 205.66649999999998, "speedup": 1.0064226782935495 }, "gpu_us": { "candidate": 2.4583423510193825, "control": 2.41666566580534, "speedup": 0.9830468343041152 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9945579968929953, "round_speedups": [ 0.9978186173170419, 0.979621535995114, 1.0064226782935495 ], "candidate": 208.10093462176968, "control": 206.96844868898734 }, "gpu_us": { "speedup": 0.9830468343041152, "round_speedups": [ 0.9830468343041152, 0.9830468343041152, 0.9830468343041152 ], "candidate": 2.4583423510193825, "control": 2.41666566580534 } } } }, { "name": "float32_32x1009", "dtype": "float32", "batches": 32, "width": 1009, "status": "measured", "variant": { "name": "register8_blocked4", "elements_per_thread": 8, "layout": "blocked4" }, "input_sha256": "41fd264c427e4e182eaad0b6751f90d1477b7e8f193b298a4dc8ccbfebb45ec3", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 127;\n int _metile_register_index = int((((_metile_bounded_thread >> 7) & 1u) << 0) | (((_metile_bounded_thread >> 8) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 6) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 128;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 7) & 1u) << 0) | (((_metile_register_packed_ >> 8) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 6) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 256;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 7) & 1u) << 0) | (((_metile_register_packed__ >> 8) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 6) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 384;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 7) & 1u) << 0) | (((_metile_register_packed___ >> 8) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 6) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 512;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 7) & 1u) << 0) | (((_metile_register_packed____ >> 8) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 5) & 1u) << 7) | (((_metile_register_packed____ >> 6) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 640;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 7) & 1u) << 0) | (((_metile_register_packed_____ >> 8) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 5) & 1u) << 7) | (((_metile_register_packed_____ >> 6) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 768;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 7) & 1u) << 0) | (((_metile_register_packed______ >> 8) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 5) & 1u) << 7) | (((_metile_register_packed______ >> 6) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 896;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 7) & 1u) << 0) | (((_metile_register_packed_______ >> 8) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 5) & 1u) << 7) | (((_metile_register_packed_______ >> 6) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n float4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = float4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n float _metile_v20_r0 = _metile_vector_load[0];\n float _metile_v20_r1 = _metile_vector_load[1];\n float _metile_v20_r2 = _metile_vector_load[2];\n float _metile_v20_r3 = _metile_vector_load[3];\n float4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = float4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n float _metile_v20_r4 = _metile_vector_load_[0];\n float _metile_v20_r5 = _metile_vector_load_[1];\n float _metile_v20_r6 = _metile_vector_load_[2];\n float _metile_v20_r7 = _metile_vector_load_[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_____ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum______ = _metile_register_sum____ + _metile_register_sum_____;\n threadgroup float _metile_register_reduction[4];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 4u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n float4 _metile_vector_load__;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load__ = float4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load__[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load__[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load__[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load__[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n float _metile_v36_r0 = _metile_vector_load__[0];\n float _metile_v36_r1 = _metile_vector_load__[1];\n float _metile_v36_r2 = _metile_vector_load__[2];\n float _metile_v36_r3 = _metile_vector_load__[3];\n float4 _metile_vector_load___;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load___ = float4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load___[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load___[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load___[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load___[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n float _metile_v36_r4 = _metile_vector_load___[0];\n float _metile_v36_r5 = _metile_vector_load___[1];\n float _metile_v36_r6 = _metile_vector_load___[2];\n float _metile_v36_r7 = _metile_vector_load___[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_float4(float4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_float4(float4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n}", "source_sha256": "9f08087b05ab0b6f116b5c1e98de9acc212cb296d3daf05cb3d563f20cdce2ce", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 128, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 128, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 8 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 4, "bytes": 16 } ], "double_buffered": false, "vectorized_loads": 4, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 8, "threads": 128, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 4, "grouped_stores": 2 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 608, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.917, "control": 197.95850000000002, "speedup": 1.0002096838573746 }, "gpu_us": { "candidate": 2.7916976250708103, "control": 2.41666566580534, "speedup": 0.8656616834511374 } } }, { "frozen_register4": { "pairs": 582, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.22899999999998, "control": 199.41649999999998, "speedup": 0.9909928489432438 }, "gpu_us": { "candidate": 2.7916976250708103, "control": 2.41666566580534, "speedup": 0.8656616834511374 } } }, { "frozen_register4": { "pairs": 605, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.042, "control": 199.708, "speedup": 0.9983303506263684 }, "gpu_us": { "candidate": 2.791639417409897, "control": 2.41666566580534, "speedup": 0.8656797331109257 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9965030142157989, "round_speedups": [ 1.0002096838573746, 0.9909928489432438, 0.9983303506263684 ], "candidate": 199.72462700156976, "control": 199.02619282019026 }, "gpu_us": { "speedup": 0.8656676999625842, "round_speedups": [ 0.8656616834511374, 0.8656616834511374, 0.8656797331109257 ], "candidate": 2.791678222382321, "control": 2.41666566580534 } } } }, { "name": "float32_32x1009", "dtype": "float32", "batches": 32, "width": 1009, "status": "measured", "variant": { "name": "register16_striped", "elements_per_thread": 16, "layout": "striped" }, "input_sha256": "41fd264c427e4e182eaad0b6751f90d1477b7e8f193b298a4dc8ccbfebb45ec3", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 63;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 64;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 128;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 192;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 256;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 320;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 384;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 448;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n int _metile_register_packed________ = _metile_bounded_thread + 512;\n int _metile_register_index________ = int(_metile_register_packed________);\n int _metile_register_packed_________ = _metile_bounded_thread + 576;\n int _metile_register_index_________ = int(_metile_register_packed_________);\n int _metile_register_packed__________ = _metile_bounded_thread + 640;\n int _metile_register_index__________ = int(_metile_register_packed__________);\n int _metile_register_packed___________ = _metile_bounded_thread + 704;\n int _metile_register_index___________ = int(_metile_register_packed___________);\n int _metile_register_packed____________ = _metile_bounded_thread + 768;\n int _metile_register_index____________ = int(_metile_register_packed____________);\n int _metile_register_packed_____________ = _metile_bounded_thread + 832;\n int _metile_register_index_____________ = int(_metile_register_packed_____________);\n int _metile_register_packed______________ = _metile_bounded_thread + 896;\n int _metile_register_index______________ = int(_metile_register_packed______________);\n int _metile_register_packed_______________ = _metile_bounded_thread + 960;\n int _metile_register_index_______________ = int(_metile_register_packed_______________);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v17_r8 = _metile_register_index________ < 1009;\n bool _metile_v17_r9 = _metile_register_index_________ < 1009;\n bool _metile_v17_r10 = _metile_register_index__________ < 1009;\n bool _metile_v17_r11 = _metile_register_index___________ < 1009;\n bool _metile_v17_r12 = _metile_register_index____________ < 1009;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v17_r14 = _metile_register_index______________ < 1009;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n float _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n float _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n float _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n float _metile_v20_r8 = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n float _metile_v20_r9 = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n float _metile_v20_r10 = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n float _metile_v20_r11 = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n float _metile_v20_r12 = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n float _metile_v20_r13 = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n float _metile_v20_r14 = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n float _metile_v20_r15 = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________ = _metile_register_sum____________ + _metile_register_sum_____________;\n threadgroup float _metile_register_reduction[2];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______________);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 2u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v33_r8 = _metile_register_index________ < 1009;\n bool _metile_v33_r9 = _metile_register_index_________ < 1009;\n bool _metile_v33_r10 = _metile_register_index__________ < 1009;\n bool _metile_v33_r11 = _metile_register_index___________ < 1009;\n bool _metile_v33_r12 = _metile_register_index____________ < 1009;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v33_r14 = _metile_register_index______________ < 1009;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n float _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n float _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n float _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n float _metile_v36_r8 = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n float _metile_v36_r9 = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n float _metile_v36_r10 = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n float _metile_v36_r11 = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n float _metile_v36_r12 = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n float _metile_v36_r13 = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n float _metile_v36_r14 = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n float _metile_v36_r15 = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v42_r8 = _metile_register_index________ < 1009;\n bool _metile_v42_r9 = _metile_register_index_________ < 1009;\n bool _metile_v42_r10 = _metile_register_index__________ < 1009;\n bool _metile_v42_r11 = _metile_register_index___________ < 1009;\n bool _metile_v42_r12 = _metile_register_index____________ < 1009;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v42_r14 = _metile_register_index______________ < 1009;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = _metile_v39_r8; }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = _metile_v39_r9; }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = _metile_v39_r10; }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = _metile_v39_r11; }\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = _metile_v39_r12; }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = _metile_v39_r13; }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = _metile_v39_r14; }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = _metile_v39_r15; }\n}", "source_sha256": "33426fa20c0c7f16979a8494e3077f7df7a4e0321c1045d73ed33afeb179b8e5", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 64, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 64, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 16 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 2, "bytes": 8 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 16, "threads": 64, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 488, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 216.458, "control": 212.58350000000002, "speedup": 0.9821004536676862 }, "gpu_us": { "candidate": 2.874992787837982, "control": 2.708344254642725, "speedup": 0.9420351473922902 } } }, { "frozen_register4": { "pairs": 541, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 205.5, "control": 202.208, "speedup": 0.9839805352798053 }, "gpu_us": { "candidate": 2.583314199000597, "control": 2.41666566580534, "speedup": 0.9354904125639351 } } }, { "frozen_register4": { "pairs": 577, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.833, "control": 203.875, "speedup": 1.0051372311211686 }, "gpu_us": { "candidate": 2.5833724066615105, "control": 2.458284143358469, "speedup": 0.9515794691541616 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9903512627886983, "round_speedups": [ 0.9821004536676862, 0.9839805352798053, 1.0051372311211686 ], "candidate": 208.18112953840682, "control": 206.1724445271386 }, "gpu_us": { "speedup": 0.9430118937419859, "round_speedups": [ 0.9420351473922902, 0.9354904125639351, 0.9515794691541616 ], "candidate": 2.67711484543032, "control": 2.52455114015403 } } } }, { "name": "float32_32x1009", "dtype": "float32", "batches": 32, "width": 1009, "status": "measured", "variant": { "name": "register16_blocked4", "elements_per_thread": 16, "layout": "blocked4" }, "input_sha256": "41fd264c427e4e182eaad0b6751f90d1477b7e8f193b298a4dc8ccbfebb45ec3", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 63;\n int _metile_register_index = int((((_metile_bounded_thread >> 6) & 1u) << 0) | (((_metile_bounded_thread >> 7) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 8) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 64;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 6) & 1u) << 0) | (((_metile_register_packed_ >> 7) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 8) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 128;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 6) & 1u) << 0) | (((_metile_register_packed__ >> 7) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 8) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 192;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 6) & 1u) << 0) | (((_metile_register_packed___ >> 7) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 8) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 256;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 6) & 1u) << 0) | (((_metile_register_packed____ >> 7) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 5) & 1u) << 7) | (((_metile_register_packed____ >> 8) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 320;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 6) & 1u) << 0) | (((_metile_register_packed_____ >> 7) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 5) & 1u) << 7) | (((_metile_register_packed_____ >> 8) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 384;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 6) & 1u) << 0) | (((_metile_register_packed______ >> 7) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 5) & 1u) << 7) | (((_metile_register_packed______ >> 8) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 448;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 6) & 1u) << 0) | (((_metile_register_packed_______ >> 7) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 5) & 1u) << 7) | (((_metile_register_packed_______ >> 8) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n int _metile_register_packed________ = _metile_bounded_thread + 512;\n int _metile_register_index________ = int((((_metile_register_packed________ >> 6) & 1u) << 0) | (((_metile_register_packed________ >> 7) & 1u) << 1) | (((_metile_register_packed________ >> 0) & 1u) << 2) | (((_metile_register_packed________ >> 1) & 1u) << 3) | (((_metile_register_packed________ >> 2) & 1u) << 4) | (((_metile_register_packed________ >> 3) & 1u) << 5) | (((_metile_register_packed________ >> 4) & 1u) << 6) | (((_metile_register_packed________ >> 5) & 1u) << 7) | (((_metile_register_packed________ >> 8) & 1u) << 8) | (((_metile_register_packed________ >> 9) & 1u) << 9));\n int _metile_register_packed_________ = _metile_bounded_thread + 576;\n int _metile_register_index_________ = int((((_metile_register_packed_________ >> 6) & 1u) << 0) | (((_metile_register_packed_________ >> 7) & 1u) << 1) | (((_metile_register_packed_________ >> 0) & 1u) << 2) | (((_metile_register_packed_________ >> 1) & 1u) << 3) | (((_metile_register_packed_________ >> 2) & 1u) << 4) | (((_metile_register_packed_________ >> 3) & 1u) << 5) | (((_metile_register_packed_________ >> 4) & 1u) << 6) | (((_metile_register_packed_________ >> 5) & 1u) << 7) | (((_metile_register_packed_________ >> 8) & 1u) << 8) | (((_metile_register_packed_________ >> 9) & 1u) << 9));\n int _metile_register_packed__________ = _metile_bounded_thread + 640;\n int _metile_register_index__________ = int((((_metile_register_packed__________ >> 6) & 1u) << 0) | (((_metile_register_packed__________ >> 7) & 1u) << 1) | (((_metile_register_packed__________ >> 0) & 1u) << 2) | (((_metile_register_packed__________ >> 1) & 1u) << 3) | (((_metile_register_packed__________ >> 2) & 1u) << 4) | (((_metile_register_packed__________ >> 3) & 1u) << 5) | (((_metile_register_packed__________ >> 4) & 1u) << 6) | (((_metile_register_packed__________ >> 5) & 1u) << 7) | (((_metile_register_packed__________ >> 8) & 1u) << 8) | (((_metile_register_packed__________ >> 9) & 1u) << 9));\n int _metile_register_packed___________ = _metile_bounded_thread + 704;\n int _metile_register_index___________ = int((((_metile_register_packed___________ >> 6) & 1u) << 0) | (((_metile_register_packed___________ >> 7) & 1u) << 1) | (((_metile_register_packed___________ >> 0) & 1u) << 2) | (((_metile_register_packed___________ >> 1) & 1u) << 3) | (((_metile_register_packed___________ >> 2) & 1u) << 4) | (((_metile_register_packed___________ >> 3) & 1u) << 5) | (((_metile_register_packed___________ >> 4) & 1u) << 6) | (((_metile_register_packed___________ >> 5) & 1u) << 7) | (((_metile_register_packed___________ >> 8) & 1u) << 8) | (((_metile_register_packed___________ >> 9) & 1u) << 9));\n int _metile_register_packed____________ = _metile_bounded_thread + 768;\n int _metile_register_index____________ = int((((_metile_register_packed____________ >> 6) & 1u) << 0) | (((_metile_register_packed____________ >> 7) & 1u) << 1) | (((_metile_register_packed____________ >> 0) & 1u) << 2) | (((_metile_register_packed____________ >> 1) & 1u) << 3) | (((_metile_register_packed____________ >> 2) & 1u) << 4) | (((_metile_register_packed____________ >> 3) & 1u) << 5) | (((_metile_register_packed____________ >> 4) & 1u) << 6) | (((_metile_register_packed____________ >> 5) & 1u) << 7) | (((_metile_register_packed____________ >> 8) & 1u) << 8) | (((_metile_register_packed____________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________ = _metile_bounded_thread + 832;\n int _metile_register_index_____________ = int((((_metile_register_packed_____________ >> 6) & 1u) << 0) | (((_metile_register_packed_____________ >> 7) & 1u) << 1) | (((_metile_register_packed_____________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________ >> 5) & 1u) << 7) | (((_metile_register_packed_____________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________ >> 9) & 1u) << 9));\n int _metile_register_packed______________ = _metile_bounded_thread + 896;\n int _metile_register_index______________ = int((((_metile_register_packed______________ >> 6) & 1u) << 0) | (((_metile_register_packed______________ >> 7) & 1u) << 1) | (((_metile_register_packed______________ >> 0) & 1u) << 2) | (((_metile_register_packed______________ >> 1) & 1u) << 3) | (((_metile_register_packed______________ >> 2) & 1u) << 4) | (((_metile_register_packed______________ >> 3) & 1u) << 5) | (((_metile_register_packed______________ >> 4) & 1u) << 6) | (((_metile_register_packed______________ >> 5) & 1u) << 7) | (((_metile_register_packed______________ >> 8) & 1u) << 8) | (((_metile_register_packed______________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________ = _metile_bounded_thread + 960;\n int _metile_register_index_______________ = int((((_metile_register_packed_______________ >> 6) & 1u) << 0) | (((_metile_register_packed_______________ >> 7) & 1u) << 1) | (((_metile_register_packed_______________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________ >> 5) & 1u) << 7) | (((_metile_register_packed_______________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v17_r8 = _metile_register_index________ < 1009;\n bool _metile_v17_r9 = _metile_register_index_________ < 1009;\n bool _metile_v17_r10 = _metile_register_index__________ < 1009;\n bool _metile_v17_r11 = _metile_register_index___________ < 1009;\n bool _metile_v17_r12 = _metile_register_index____________ < 1009;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v17_r14 = _metile_register_index______________ < 1009;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n float4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = float4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n float _metile_v20_r0 = _metile_vector_load[0];\n float _metile_v20_r1 = _metile_vector_load[1];\n float _metile_v20_r2 = _metile_vector_load[2];\n float _metile_v20_r3 = _metile_vector_load[3];\n float4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = float4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n float _metile_v20_r4 = _metile_vector_load_[0];\n float _metile_v20_r5 = _metile_vector_load_[1];\n float _metile_v20_r6 = _metile_vector_load_[2];\n float _metile_v20_r7 = _metile_vector_load_[3];\n float4 _metile_vector_load__;\n if ((_metile_v18_r8) && (_metile_v18_r9) && (_metile_v18_r10) && (_metile_v18_r11) && (long(_off__metile_v19_r9) == long(_off__metile_v19_r8) + 1) && (long(_off__metile_v19_r10) == long(_off__metile_v19_r8) + 2) && (long(_off__metile_v19_r11) == long(_off__metile_v19_r8) + 3)) {\n _metile_vector_load__ = float4(*reinterpret_cast(X + _off__metile_v19_r8));\n } else {\n _metile_vector_load__[0] = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n _metile_vector_load__[1] = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n _metile_vector_load__[2] = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n _metile_vector_load__[3] = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n }\n float _metile_v20_r8 = _metile_vector_load__[0];\n float _metile_v20_r9 = _metile_vector_load__[1];\n float _metile_v20_r10 = _metile_vector_load__[2];\n float _metile_v20_r11 = _metile_vector_load__[3];\n float4 _metile_vector_load___;\n if ((_metile_v18_r12) && (_metile_v18_r13) && (_metile_v18_r14) && (_metile_v18_r15) && (long(_off__metile_v19_r13) == long(_off__metile_v19_r12) + 1) && (long(_off__metile_v19_r14) == long(_off__metile_v19_r12) + 2) && (long(_off__metile_v19_r15) == long(_off__metile_v19_r12) + 3)) {\n _metile_vector_load___ = float4(*reinterpret_cast(X + _off__metile_v19_r12));\n } else {\n _metile_vector_load___[0] = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n _metile_vector_load___[1] = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n _metile_vector_load___[2] = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n _metile_vector_load___[3] = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n }\n float _metile_v20_r12 = _metile_vector_load___[0];\n float _metile_v20_r13 = _metile_vector_load___[1];\n float _metile_v20_r14 = _metile_vector_load___[2];\n float _metile_v20_r15 = _metile_vector_load___[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________ = _metile_register_sum____________ + _metile_register_sum_____________;\n threadgroup float _metile_register_reduction[2];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______________);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 2u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v33_r8 = _metile_register_index________ < 1009;\n bool _metile_v33_r9 = _metile_register_index_________ < 1009;\n bool _metile_v33_r10 = _metile_register_index__________ < 1009;\n bool _metile_v33_r11 = _metile_register_index___________ < 1009;\n bool _metile_v33_r12 = _metile_register_index____________ < 1009;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v33_r14 = _metile_register_index______________ < 1009;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n float4 _metile_vector_load____;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load____ = float4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load____[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load____[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load____[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load____[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n float _metile_v36_r0 = _metile_vector_load____[0];\n float _metile_v36_r1 = _metile_vector_load____[1];\n float _metile_v36_r2 = _metile_vector_load____[2];\n float _metile_v36_r3 = _metile_vector_load____[3];\n float4 _metile_vector_load_____;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load_____ = float4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load_____[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load_____[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load_____[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load_____[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n float _metile_v36_r4 = _metile_vector_load_____[0];\n float _metile_v36_r5 = _metile_vector_load_____[1];\n float _metile_v36_r6 = _metile_vector_load_____[2];\n float _metile_v36_r7 = _metile_vector_load_____[3];\n float4 _metile_vector_load______;\n if ((_metile_v34_r8) && (_metile_v34_r9) && (_metile_v34_r10) && (_metile_v34_r11) && (long(_metile_register_index_________) == long(_metile_register_index________) + 1) && (long(_metile_register_index__________) == long(_metile_register_index________) + 2) && (long(_metile_register_index___________) == long(_metile_register_index________) + 3)) {\n _metile_vector_load______ = float4(*reinterpret_cast(W + _metile_register_index________));\n } else {\n _metile_vector_load______[0] = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n _metile_vector_load______[1] = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n _metile_vector_load______[2] = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n _metile_vector_load______[3] = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n }\n float _metile_v36_r8 = _metile_vector_load______[0];\n float _metile_v36_r9 = _metile_vector_load______[1];\n float _metile_v36_r10 = _metile_vector_load______[2];\n float _metile_v36_r11 = _metile_vector_load______[3];\n float4 _metile_vector_load_______;\n if ((_metile_v34_r12) && (_metile_v34_r13) && (_metile_v34_r14) && (_metile_v34_r15) && (long(_metile_register_index_____________) == long(_metile_register_index____________) + 1) && (long(_metile_register_index______________) == long(_metile_register_index____________) + 2) && (long(_metile_register_index_______________) == long(_metile_register_index____________) + 3)) {\n _metile_vector_load_______ = float4(*reinterpret_cast(W + _metile_register_index____________));\n } else {\n _metile_vector_load_______[0] = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n _metile_vector_load_______[1] = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n _metile_vector_load_______[2] = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n _metile_vector_load_______[3] = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n }\n float _metile_v36_r12 = _metile_vector_load_______[0];\n float _metile_v36_r13 = _metile_vector_load_______[1];\n float _metile_v36_r14 = _metile_vector_load_______[2];\n float _metile_v36_r15 = _metile_vector_load_______[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v42_r8 = _metile_register_index________ < 1009;\n bool _metile_v42_r9 = _metile_register_index_________ < 1009;\n bool _metile_v42_r10 = _metile_register_index__________ < 1009;\n bool _metile_v42_r11 = _metile_register_index___________ < 1009;\n bool _metile_v42_r12 = _metile_register_index____________ < 1009;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v42_r14 = _metile_register_index______________ < 1009;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_float4(float4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_float4(float4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n if ((_metile_v43_r8) && (_metile_v43_r9) && (_metile_v43_r10) && (_metile_v43_r11) && (long(_off__metile_v44_r9) == long(_off__metile_v44_r8) + 1) && (long(_off__metile_v44_r10) == long(_off__metile_v44_r8) + 2) && (long(_off__metile_v44_r11) == long(_off__metile_v44_r8) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r8) = packed_float4(float4(static_cast(_metile_v39_r8), static_cast(_metile_v39_r9), static_cast(_metile_v39_r10), static_cast(_metile_v39_r11)));\n } else {\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = static_cast(_metile_v39_r8); }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = static_cast(_metile_v39_r9); }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = static_cast(_metile_v39_r10); }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = static_cast(_metile_v39_r11); }\n }\n if ((_metile_v43_r12) && (_metile_v43_r13) && (_metile_v43_r14) && (_metile_v43_r15) && (long(_off__metile_v44_r13) == long(_off__metile_v44_r12) + 1) && (long(_off__metile_v44_r14) == long(_off__metile_v44_r12) + 2) && (long(_off__metile_v44_r15) == long(_off__metile_v44_r12) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r12) = packed_float4(float4(static_cast(_metile_v39_r12), static_cast(_metile_v39_r13), static_cast(_metile_v39_r14), static_cast(_metile_v39_r15)));\n } else {\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = static_cast(_metile_v39_r12); }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = static_cast(_metile_v39_r13); }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = static_cast(_metile_v39_r14); }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = static_cast(_metile_v39_r15); }\n }\n}", "source_sha256": "2617a2e2182b7192b8def8bf914a9cd9d48eed7adf610815901d9692d304fd01", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 64, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 64, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 16 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 2, "bytes": 8 } ], "double_buffered": false, "vectorized_loads": 8, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 16, "threads": 64, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 8, "grouped_stores": 4 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 540, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.292, "control": 202.042, "speedup": 1.003725930489041 }, "gpu_us": { "candidate": 3.374996595084667, "control": 2.4999608285725117, "speedup": 0.7407298816874203 } } }, { "frozen_register4": { "pairs": 609, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.708, "control": 197.625, "speedup": 0.9846393766068119 }, "gpu_us": { "candidate": 3.374996595084667, "control": 2.41666566580534, "speedup": 0.7160498085612776 } } }, { "frozen_register4": { "pairs": 607, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.208, "control": 199.625, "speedup": 0.9970880284504116 }, "gpu_us": { "candidate": 3.374996595084667, "control": 2.4999608285725117, "speedup": 0.7407298816874203 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9951196036408093, "round_speedups": [ 1.003725930489041, 0.9846393766068119, 0.9970880284504116 ], "candidate": 200.73551127888098, "control": 199.7558424204751 }, "gpu_us": { "speedup": 0.7324100936583371, "round_speedups": [ 0.7407298816874203, 0.7160498085612776, 0.7407298816874203 ], "candidate": 3.374996595084667, "control": 2.4718815723025296 } } } }, { "name": "float32_32x1009", "dtype": "float32", "batches": 32, "width": 1009, "status": "measured", "variant": { "name": "register32_striped", "elements_per_thread": 32, "layout": "striped" }, "input_sha256": "41fd264c427e4e182eaad0b6751f90d1477b7e8f193b298a4dc8ccbfebb45ec3", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 31;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 32;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 64;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 96;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 128;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 160;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 192;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 224;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n int _metile_register_packed________ = _metile_bounded_thread + 256;\n int _metile_register_index________ = int(_metile_register_packed________);\n int _metile_register_packed_________ = _metile_bounded_thread + 288;\n int _metile_register_index_________ = int(_metile_register_packed_________);\n int _metile_register_packed__________ = _metile_bounded_thread + 320;\n int _metile_register_index__________ = int(_metile_register_packed__________);\n int _metile_register_packed___________ = _metile_bounded_thread + 352;\n int _metile_register_index___________ = int(_metile_register_packed___________);\n int _metile_register_packed____________ = _metile_bounded_thread + 384;\n int _metile_register_index____________ = int(_metile_register_packed____________);\n int _metile_register_packed_____________ = _metile_bounded_thread + 416;\n int _metile_register_index_____________ = int(_metile_register_packed_____________);\n int _metile_register_packed______________ = _metile_bounded_thread + 448;\n int _metile_register_index______________ = int(_metile_register_packed______________);\n int _metile_register_packed_______________ = _metile_bounded_thread + 480;\n int _metile_register_index_______________ = int(_metile_register_packed_______________);\n int _metile_register_packed________________ = _metile_bounded_thread + 512;\n int _metile_register_index________________ = int(_metile_register_packed________________);\n int _metile_register_packed_________________ = _metile_bounded_thread + 544;\n int _metile_register_index_________________ = int(_metile_register_packed_________________);\n int _metile_register_packed__________________ = _metile_bounded_thread + 576;\n int _metile_register_index__________________ = int(_metile_register_packed__________________);\n int _metile_register_packed___________________ = _metile_bounded_thread + 608;\n int _metile_register_index___________________ = int(_metile_register_packed___________________);\n int _metile_register_packed____________________ = _metile_bounded_thread + 640;\n int _metile_register_index____________________ = int(_metile_register_packed____________________);\n int _metile_register_packed_____________________ = _metile_bounded_thread + 672;\n int _metile_register_index_____________________ = int(_metile_register_packed_____________________);\n int _metile_register_packed______________________ = _metile_bounded_thread + 704;\n int _metile_register_index______________________ = int(_metile_register_packed______________________);\n int _metile_register_packed_______________________ = _metile_bounded_thread + 736;\n int _metile_register_index_______________________ = int(_metile_register_packed_______________________);\n int _metile_register_packed________________________ = _metile_bounded_thread + 768;\n int _metile_register_index________________________ = int(_metile_register_packed________________________);\n int _metile_register_packed_________________________ = _metile_bounded_thread + 800;\n int _metile_register_index_________________________ = int(_metile_register_packed_________________________);\n int _metile_register_packed__________________________ = _metile_bounded_thread + 832;\n int _metile_register_index__________________________ = int(_metile_register_packed__________________________);\n int _metile_register_packed___________________________ = _metile_bounded_thread + 864;\n int _metile_register_index___________________________ = int(_metile_register_packed___________________________);\n int _metile_register_packed____________________________ = _metile_bounded_thread + 896;\n int _metile_register_index____________________________ = int(_metile_register_packed____________________________);\n int _metile_register_packed_____________________________ = _metile_bounded_thread + 928;\n int _metile_register_index_____________________________ = int(_metile_register_packed_____________________________);\n int _metile_register_packed______________________________ = _metile_bounded_thread + 960;\n int _metile_register_index______________________________ = int(_metile_register_packed______________________________);\n int _metile_register_packed_______________________________ = _metile_bounded_thread + 992;\n int _metile_register_index_______________________________ = int(_metile_register_packed_______________________________);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v16_r16 = _metile_register_index________________ >= 0;\n bool _metile_v16_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v16_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v16_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v16_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v16_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v16_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v16_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v16_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v16_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v16_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v16_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v16_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v16_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v16_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v16_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v17_r8 = _metile_register_index________ < 1009;\n bool _metile_v17_r9 = _metile_register_index_________ < 1009;\n bool _metile_v17_r10 = _metile_register_index__________ < 1009;\n bool _metile_v17_r11 = _metile_register_index___________ < 1009;\n bool _metile_v17_r12 = _metile_register_index____________ < 1009;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v17_r14 = _metile_register_index______________ < 1009;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v17_r16 = _metile_register_index________________ < 1009;\n bool _metile_v17_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v17_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v17_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v17_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v17_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v17_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v17_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v17_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v17_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v17_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v17_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v17_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v17_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v17_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v17_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n bool _metile_v18_r16 = _metile_v16_r16 & _metile_v17_r16;\n bool _metile_v18_r17 = _metile_v16_r17 & _metile_v17_r17;\n bool _metile_v18_r18 = _metile_v16_r18 & _metile_v17_r18;\n bool _metile_v18_r19 = _metile_v16_r19 & _metile_v17_r19;\n bool _metile_v18_r20 = _metile_v16_r20 & _metile_v17_r20;\n bool _metile_v18_r21 = _metile_v16_r21 & _metile_v17_r21;\n bool _metile_v18_r22 = _metile_v16_r22 & _metile_v17_r22;\n bool _metile_v18_r23 = _metile_v16_r23 & _metile_v17_r23;\n bool _metile_v18_r24 = _metile_v16_r24 & _metile_v17_r24;\n bool _metile_v18_r25 = _metile_v16_r25 & _metile_v17_r25;\n bool _metile_v18_r26 = _metile_v16_r26 & _metile_v17_r26;\n bool _metile_v18_r27 = _metile_v16_r27 & _metile_v17_r27;\n bool _metile_v18_r28 = _metile_v16_r28 & _metile_v17_r28;\n bool _metile_v18_r29 = _metile_v16_r29 & _metile_v17_r29;\n bool _metile_v18_r30 = _metile_v16_r30 & _metile_v17_r30;\n bool _metile_v18_r31 = _metile_v16_r31 & _metile_v17_r31;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n int _off__metile_v19_r16 = v2 + _metile_register_index________________;\n int _off__metile_v19_r17 = v2 + _metile_register_index_________________;\n int _off__metile_v19_r18 = v2 + _metile_register_index__________________;\n int _off__metile_v19_r19 = v2 + _metile_register_index___________________;\n int _off__metile_v19_r20 = v2 + _metile_register_index____________________;\n int _off__metile_v19_r21 = v2 + _metile_register_index_____________________;\n int _off__metile_v19_r22 = v2 + _metile_register_index______________________;\n int _off__metile_v19_r23 = v2 + _metile_register_index_______________________;\n int _off__metile_v19_r24 = v2 + _metile_register_index________________________;\n int _off__metile_v19_r25 = v2 + _metile_register_index_________________________;\n int _off__metile_v19_r26 = v2 + _metile_register_index__________________________;\n int _off__metile_v19_r27 = v2 + _metile_register_index___________________________;\n int _off__metile_v19_r28 = v2 + _metile_register_index____________________________;\n int _off__metile_v19_r29 = v2 + _metile_register_index_____________________________;\n int _off__metile_v19_r30 = v2 + _metile_register_index______________________________;\n int _off__metile_v19_r31 = v2 + _metile_register_index_______________________________;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n float _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n float _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n float _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n float _metile_v20_r8 = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n float _metile_v20_r9 = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n float _metile_v20_r10 = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n float _metile_v20_r11 = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n float _metile_v20_r12 = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n float _metile_v20_r13 = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n float _metile_v20_r14 = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n float _metile_v20_r15 = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n float _metile_v20_r16 = _metile_v18_r16 ? X[_off__metile_v19_r16] : static_cast(0);\n float _metile_v20_r17 = _metile_v18_r17 ? X[_off__metile_v19_r17] : static_cast(0);\n float _metile_v20_r18 = _metile_v18_r18 ? X[_off__metile_v19_r18] : static_cast(0);\n float _metile_v20_r19 = _metile_v18_r19 ? X[_off__metile_v19_r19] : static_cast(0);\n float _metile_v20_r20 = _metile_v18_r20 ? X[_off__metile_v19_r20] : static_cast(0);\n float _metile_v20_r21 = _metile_v18_r21 ? X[_off__metile_v19_r21] : static_cast(0);\n float _metile_v20_r22 = _metile_v18_r22 ? X[_off__metile_v19_r22] : static_cast(0);\n float _metile_v20_r23 = _metile_v18_r23 ? X[_off__metile_v19_r23] : static_cast(0);\n float _metile_v20_r24 = _metile_v18_r24 ? X[_off__metile_v19_r24] : static_cast(0);\n float _metile_v20_r25 = _metile_v18_r25 ? X[_off__metile_v19_r25] : static_cast(0);\n float _metile_v20_r26 = _metile_v18_r26 ? X[_off__metile_v19_r26] : static_cast(0);\n float _metile_v20_r27 = _metile_v18_r27 ? X[_off__metile_v19_r27] : static_cast(0);\n float _metile_v20_r28 = _metile_v18_r28 ? X[_off__metile_v19_r28] : static_cast(0);\n float _metile_v20_r29 = _metile_v18_r29 ? X[_off__metile_v19_r29] : static_cast(0);\n float _metile_v20_r30 = _metile_v18_r30 ? X[_off__metile_v19_r30] : static_cast(0);\n float _metile_v20_r31 = _metile_v18_r31 ? X[_off__metile_v19_r31] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v21_r16 = static_cast(_metile_v20_r16);\n float _metile_v21_r17 = static_cast(_metile_v20_r17);\n float _metile_v21_r18 = static_cast(_metile_v20_r18);\n float _metile_v21_r19 = static_cast(_metile_v20_r19);\n float _metile_v21_r20 = static_cast(_metile_v20_r20);\n float _metile_v21_r21 = static_cast(_metile_v20_r21);\n float _metile_v21_r22 = static_cast(_metile_v20_r22);\n float _metile_v21_r23 = static_cast(_metile_v20_r23);\n float _metile_v21_r24 = static_cast(_metile_v20_r24);\n float _metile_v21_r25 = static_cast(_metile_v20_r25);\n float _metile_v21_r26 = static_cast(_metile_v20_r26);\n float _metile_v21_r27 = static_cast(_metile_v20_r27);\n float _metile_v21_r28 = static_cast(_metile_v20_r28);\n float _metile_v21_r29 = static_cast(_metile_v20_r29);\n float _metile_v21_r30 = static_cast(_metile_v20_r30);\n float _metile_v21_r31 = static_cast(_metile_v20_r31);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_v22_r16 = _metile_v21_r16 * _metile_v21_r16;\n float _metile_v22_r17 = _metile_v21_r17 * _metile_v21_r17;\n float _metile_v22_r18 = _metile_v21_r18 * _metile_v21_r18;\n float _metile_v22_r19 = _metile_v21_r19 * _metile_v21_r19;\n float _metile_v22_r20 = _metile_v21_r20 * _metile_v21_r20;\n float _metile_v22_r21 = _metile_v21_r21 * _metile_v21_r21;\n float _metile_v22_r22 = _metile_v21_r22 * _metile_v21_r22;\n float _metile_v22_r23 = _metile_v21_r23 * _metile_v21_r23;\n float _metile_v22_r24 = _metile_v21_r24 * _metile_v21_r24;\n float _metile_v22_r25 = _metile_v21_r25 * _metile_v21_r25;\n float _metile_v22_r26 = _metile_v21_r26 * _metile_v21_r26;\n float _metile_v22_r27 = _metile_v21_r27 * _metile_v21_r27;\n float _metile_v22_r28 = _metile_v21_r28 * _metile_v21_r28;\n float _metile_v22_r29 = _metile_v21_r29 * _metile_v21_r29;\n float _metile_v22_r30 = _metile_v21_r30 * _metile_v21_r30;\n float _metile_v22_r31 = _metile_v21_r31 * _metile_v21_r31;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_v22_r16 + _metile_v22_r17;\n float _metile_register_sum_________ = _metile_v22_r18 + _metile_v22_r19;\n float _metile_register_sum__________ = _metile_v22_r20 + _metile_v22_r21;\n float _metile_register_sum___________ = _metile_v22_r22 + _metile_v22_r23;\n float _metile_register_sum____________ = _metile_v22_r24 + _metile_v22_r25;\n float _metile_register_sum_____________ = _metile_v22_r26 + _metile_v22_r27;\n float _metile_register_sum______________ = _metile_v22_r28 + _metile_v22_r29;\n float _metile_register_sum_______________ = _metile_v22_r30 + _metile_v22_r31;\n float _metile_register_sum________________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________________ = _metile_register_sum____________ + _metile_register_sum_____________;\n float _metile_register_sum_______________________ = _metile_register_sum______________ + _metile_register_sum_______________;\n float _metile_register_sum________________________ = _metile_register_sum________________ + _metile_register_sum_________________;\n float _metile_register_sum_________________________ = _metile_register_sum__________________ + _metile_register_sum___________________;\n float _metile_register_sum__________________________ = _metile_register_sum____________________ + _metile_register_sum_____________________;\n float _metile_register_sum___________________________ = _metile_register_sum______________________ + _metile_register_sum_______________________;\n float _metile_register_sum____________________________ = _metile_register_sum________________________ + _metile_register_sum_________________________;\n float _metile_register_sum_____________________________ = _metile_register_sum__________________________ + _metile_register_sum___________________________;\n float _metile_register_sum______________________________ = _metile_register_sum____________________________ + _metile_register_sum_____________________________;\n float v23 = simd_sum(_metile_register_sum______________________________);\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v32_r16 = _metile_register_index________________ >= 0;\n bool _metile_v32_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v32_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v32_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v32_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v32_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v32_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v32_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v32_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v32_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v32_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v32_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v32_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v32_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v32_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v32_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v33_r8 = _metile_register_index________ < 1009;\n bool _metile_v33_r9 = _metile_register_index_________ < 1009;\n bool _metile_v33_r10 = _metile_register_index__________ < 1009;\n bool _metile_v33_r11 = _metile_register_index___________ < 1009;\n bool _metile_v33_r12 = _metile_register_index____________ < 1009;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v33_r14 = _metile_register_index______________ < 1009;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v33_r16 = _metile_register_index________________ < 1009;\n bool _metile_v33_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v33_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v33_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v33_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v33_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v33_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v33_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v33_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v33_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v33_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v33_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v33_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v33_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v33_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v33_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n bool _metile_v34_r16 = _metile_v32_r16 & _metile_v33_r16;\n bool _metile_v34_r17 = _metile_v32_r17 & _metile_v33_r17;\n bool _metile_v34_r18 = _metile_v32_r18 & _metile_v33_r18;\n bool _metile_v34_r19 = _metile_v32_r19 & _metile_v33_r19;\n bool _metile_v34_r20 = _metile_v32_r20 & _metile_v33_r20;\n bool _metile_v34_r21 = _metile_v32_r21 & _metile_v33_r21;\n bool _metile_v34_r22 = _metile_v32_r22 & _metile_v33_r22;\n bool _metile_v34_r23 = _metile_v32_r23 & _metile_v33_r23;\n bool _metile_v34_r24 = _metile_v32_r24 & _metile_v33_r24;\n bool _metile_v34_r25 = _metile_v32_r25 & _metile_v33_r25;\n bool _metile_v34_r26 = _metile_v32_r26 & _metile_v33_r26;\n bool _metile_v34_r27 = _metile_v32_r27 & _metile_v33_r27;\n bool _metile_v34_r28 = _metile_v32_r28 & _metile_v33_r28;\n bool _metile_v34_r29 = _metile_v32_r29 & _metile_v33_r29;\n bool _metile_v34_r30 = _metile_v32_r30 & _metile_v33_r30;\n bool _metile_v34_r31 = _metile_v32_r31 & _metile_v33_r31;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n float _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n float _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n float _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n float _metile_v36_r8 = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n float _metile_v36_r9 = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n float _metile_v36_r10 = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n float _metile_v36_r11 = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n float _metile_v36_r12 = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n float _metile_v36_r13 = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n float _metile_v36_r14 = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n float _metile_v36_r15 = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n float _metile_v36_r16 = _metile_v34_r16 ? W[_metile_register_index________________] : static_cast(0);\n float _metile_v36_r17 = _metile_v34_r17 ? W[_metile_register_index_________________] : static_cast(0);\n float _metile_v36_r18 = _metile_v34_r18 ? W[_metile_register_index__________________] : static_cast(0);\n float _metile_v36_r19 = _metile_v34_r19 ? W[_metile_register_index___________________] : static_cast(0);\n float _metile_v36_r20 = _metile_v34_r20 ? W[_metile_register_index____________________] : static_cast(0);\n float _metile_v36_r21 = _metile_v34_r21 ? W[_metile_register_index_____________________] : static_cast(0);\n float _metile_v36_r22 = _metile_v34_r22 ? W[_metile_register_index______________________] : static_cast(0);\n float _metile_v36_r23 = _metile_v34_r23 ? W[_metile_register_index_______________________] : static_cast(0);\n float _metile_v36_r24 = _metile_v34_r24 ? W[_metile_register_index________________________] : static_cast(0);\n float _metile_v36_r25 = _metile_v34_r25 ? W[_metile_register_index_________________________] : static_cast(0);\n float _metile_v36_r26 = _metile_v34_r26 ? W[_metile_register_index__________________________] : static_cast(0);\n float _metile_v36_r27 = _metile_v34_r27 ? W[_metile_register_index___________________________] : static_cast(0);\n float _metile_v36_r28 = _metile_v34_r28 ? W[_metile_register_index____________________________] : static_cast(0);\n float _metile_v36_r29 = _metile_v34_r29 ? W[_metile_register_index_____________________________] : static_cast(0);\n float _metile_v36_r30 = _metile_v34_r30 ? W[_metile_register_index______________________________] : static_cast(0);\n float _metile_v36_r31 = _metile_v34_r31 ? W[_metile_register_index_______________________________] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v37_r16 = static_cast(_metile_v36_r16);\n float _metile_v37_r17 = static_cast(_metile_v36_r17);\n float _metile_v37_r18 = static_cast(_metile_v36_r18);\n float _metile_v37_r19 = static_cast(_metile_v36_r19);\n float _metile_v37_r20 = static_cast(_metile_v36_r20);\n float _metile_v37_r21 = static_cast(_metile_v36_r21);\n float _metile_v37_r22 = static_cast(_metile_v36_r22);\n float _metile_v37_r23 = static_cast(_metile_v36_r23);\n float _metile_v37_r24 = static_cast(_metile_v36_r24);\n float _metile_v37_r25 = static_cast(_metile_v36_r25);\n float _metile_v37_r26 = static_cast(_metile_v36_r26);\n float _metile_v37_r27 = static_cast(_metile_v36_r27);\n float _metile_v37_r28 = static_cast(_metile_v36_r28);\n float _metile_v37_r29 = static_cast(_metile_v36_r29);\n float _metile_v37_r30 = static_cast(_metile_v36_r30);\n float _metile_v37_r31 = static_cast(_metile_v36_r31);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v38_r16 = _metile_v21_r16 * v29;\n float _metile_v38_r17 = _metile_v21_r17 * v29;\n float _metile_v38_r18 = _metile_v21_r18 * v29;\n float _metile_v38_r19 = _metile_v21_r19 * v29;\n float _metile_v38_r20 = _metile_v21_r20 * v29;\n float _metile_v38_r21 = _metile_v21_r21 * v29;\n float _metile_v38_r22 = _metile_v21_r22 * v29;\n float _metile_v38_r23 = _metile_v21_r23 * v29;\n float _metile_v38_r24 = _metile_v21_r24 * v29;\n float _metile_v38_r25 = _metile_v21_r25 * v29;\n float _metile_v38_r26 = _metile_v21_r26 * v29;\n float _metile_v38_r27 = _metile_v21_r27 * v29;\n float _metile_v38_r28 = _metile_v21_r28 * v29;\n float _metile_v38_r29 = _metile_v21_r29 * v29;\n float _metile_v38_r30 = _metile_v21_r30 * v29;\n float _metile_v38_r31 = _metile_v21_r31 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n float _metile_v39_r16 = _metile_v38_r16 * _metile_v37_r16;\n float _metile_v39_r17 = _metile_v38_r17 * _metile_v37_r17;\n float _metile_v39_r18 = _metile_v38_r18 * _metile_v37_r18;\n float _metile_v39_r19 = _metile_v38_r19 * _metile_v37_r19;\n float _metile_v39_r20 = _metile_v38_r20 * _metile_v37_r20;\n float _metile_v39_r21 = _metile_v38_r21 * _metile_v37_r21;\n float _metile_v39_r22 = _metile_v38_r22 * _metile_v37_r22;\n float _metile_v39_r23 = _metile_v38_r23 * _metile_v37_r23;\n float _metile_v39_r24 = _metile_v38_r24 * _metile_v37_r24;\n float _metile_v39_r25 = _metile_v38_r25 * _metile_v37_r25;\n float _metile_v39_r26 = _metile_v38_r26 * _metile_v37_r26;\n float _metile_v39_r27 = _metile_v38_r27 * _metile_v37_r27;\n float _metile_v39_r28 = _metile_v38_r28 * _metile_v37_r28;\n float _metile_v39_r29 = _metile_v38_r29 * _metile_v37_r29;\n float _metile_v39_r30 = _metile_v38_r30 * _metile_v37_r30;\n float _metile_v39_r31 = _metile_v38_r31 * _metile_v37_r31;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v41_r16 = _metile_register_index________________ >= 0;\n bool _metile_v41_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v41_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v41_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v41_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v41_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v41_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v41_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v41_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v41_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v41_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v41_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v41_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v41_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v41_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v41_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v42_r8 = _metile_register_index________ < 1009;\n bool _metile_v42_r9 = _metile_register_index_________ < 1009;\n bool _metile_v42_r10 = _metile_register_index__________ < 1009;\n bool _metile_v42_r11 = _metile_register_index___________ < 1009;\n bool _metile_v42_r12 = _metile_register_index____________ < 1009;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v42_r14 = _metile_register_index______________ < 1009;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v42_r16 = _metile_register_index________________ < 1009;\n bool _metile_v42_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v42_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v42_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v42_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v42_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v42_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v42_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v42_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v42_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v42_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v42_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v42_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v42_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v42_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v42_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n bool _metile_v43_r16 = _metile_v41_r16 & _metile_v42_r16;\n bool _metile_v43_r17 = _metile_v41_r17 & _metile_v42_r17;\n bool _metile_v43_r18 = _metile_v41_r18 & _metile_v42_r18;\n bool _metile_v43_r19 = _metile_v41_r19 & _metile_v42_r19;\n bool _metile_v43_r20 = _metile_v41_r20 & _metile_v42_r20;\n bool _metile_v43_r21 = _metile_v41_r21 & _metile_v42_r21;\n bool _metile_v43_r22 = _metile_v41_r22 & _metile_v42_r22;\n bool _metile_v43_r23 = _metile_v41_r23 & _metile_v42_r23;\n bool _metile_v43_r24 = _metile_v41_r24 & _metile_v42_r24;\n bool _metile_v43_r25 = _metile_v41_r25 & _metile_v42_r25;\n bool _metile_v43_r26 = _metile_v41_r26 & _metile_v42_r26;\n bool _metile_v43_r27 = _metile_v41_r27 & _metile_v42_r27;\n bool _metile_v43_r28 = _metile_v41_r28 & _metile_v42_r28;\n bool _metile_v43_r29 = _metile_v41_r29 & _metile_v42_r29;\n bool _metile_v43_r30 = _metile_v41_r30 & _metile_v42_r30;\n bool _metile_v43_r31 = _metile_v41_r31 & _metile_v42_r31;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n int _off__metile_v44_r16 = v9 + _metile_register_index________________;\n int _off__metile_v44_r17 = v9 + _metile_register_index_________________;\n int _off__metile_v44_r18 = v9 + _metile_register_index__________________;\n int _off__metile_v44_r19 = v9 + _metile_register_index___________________;\n int _off__metile_v44_r20 = v9 + _metile_register_index____________________;\n int _off__metile_v44_r21 = v9 + _metile_register_index_____________________;\n int _off__metile_v44_r22 = v9 + _metile_register_index______________________;\n int _off__metile_v44_r23 = v9 + _metile_register_index_______________________;\n int _off__metile_v44_r24 = v9 + _metile_register_index________________________;\n int _off__metile_v44_r25 = v9 + _metile_register_index_________________________;\n int _off__metile_v44_r26 = v9 + _metile_register_index__________________________;\n int _off__metile_v44_r27 = v9 + _metile_register_index___________________________;\n int _off__metile_v44_r28 = v9 + _metile_register_index____________________________;\n int _off__metile_v44_r29 = v9 + _metile_register_index_____________________________;\n int _off__metile_v44_r30 = v9 + _metile_register_index______________________________;\n int _off__metile_v44_r31 = v9 + _metile_register_index_______________________________;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = _metile_v39_r8; }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = _metile_v39_r9; }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = _metile_v39_r10; }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = _metile_v39_r11; }\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = _metile_v39_r12; }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = _metile_v39_r13; }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = _metile_v39_r14; }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = _metile_v39_r15; }\n if (_metile_v43_r16) { Out[_off__metile_v44_r16] = _metile_v39_r16; }\n if (_metile_v43_r17) { Out[_off__metile_v44_r17] = _metile_v39_r17; }\n if (_metile_v43_r18) { Out[_off__metile_v44_r18] = _metile_v39_r18; }\n if (_metile_v43_r19) { Out[_off__metile_v44_r19] = _metile_v39_r19; }\n if (_metile_v43_r20) { Out[_off__metile_v44_r20] = _metile_v39_r20; }\n if (_metile_v43_r21) { Out[_off__metile_v44_r21] = _metile_v39_r21; }\n if (_metile_v43_r22) { Out[_off__metile_v44_r22] = _metile_v39_r22; }\n if (_metile_v43_r23) { Out[_off__metile_v44_r23] = _metile_v39_r23; }\n if (_metile_v43_r24) { Out[_off__metile_v44_r24] = _metile_v39_r24; }\n if (_metile_v43_r25) { Out[_off__metile_v44_r25] = _metile_v39_r25; }\n if (_metile_v43_r26) { Out[_off__metile_v44_r26] = _metile_v39_r26; }\n if (_metile_v43_r27) { Out[_off__metile_v44_r27] = _metile_v39_r27; }\n if (_metile_v43_r28) { Out[_off__metile_v44_r28] = _metile_v39_r28; }\n if (_metile_v43_r29) { Out[_off__metile_v44_r29] = _metile_v39_r29; }\n if (_metile_v43_r30) { Out[_off__metile_v44_r30] = _metile_v39_r30; }\n if (_metile_v43_r31) { Out[_off__metile_v44_r31] = _metile_v39_r31; }\n}", "source_sha256": "11365c357d8fbe48acbc6b54fb859a3d19b352b116d23e5955e6f3b1336584e2", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 32, 1, 1 ], "is_gemm": false, "prefer_ordered": false, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 32, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 32 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 32, "threads": 32, "scratch": null, "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 502, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.708, "control": 204.27100000000002, "speedup": 0.9978652519686578 }, "gpu_us": { "candidate": 2.7500209398567677, "control": 2.4583423510193825, "speedup": 0.8939358662292306 } } }, { "frozen_register4": { "pairs": 614, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.35399999999998, "control": 198.8955, "speedup": 0.992720384918694 }, "gpu_us": { "candidate": 2.7500209398567677, "control": 2.41666566580534, "speedup": 0.8787808233675521 } } }, { "frozen_register4": { "pairs": 614, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.6455, "control": 200.042, "speedup": 0.9969922076498102 }, "gpu_us": { "candidate": 2.7500209398567677, "control": 2.41666566580534, "speedup": 0.8787808233675521 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9958567419173117, "round_speedups": [ 0.9978652519686578, 0.992720384918694, 0.9969922076498102 ], "candidate": 201.8927632815213, "control": 201.0562694582189 }, "gpu_us": { "speedup": 0.883803739745151, "round_speedups": [ 0.8939358662292306, 0.8787808233675521, 0.8787808233675521 ], "candidate": 2.750020939856767, "control": 2.430478791022886 } } } }, { "name": "float32_256x1009", "dtype": "float32", "batches": 256, "width": 1009, "status": "measured", "variant": { "name": "register2_striped", "elements_per_thread": 2, "layout": "striped" }, "input_sha256": "7bf6ce415ddd84786a2d450acbead1c0e25e5540b52b07d28c1e7796b91c7626", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 511;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 512;\n int _metile_register_index_ = int(_metile_register_packed_);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n threadgroup float _metile_register_reduction[16];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 16u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n}", "source_sha256": "9bc3eb88c124547d7881e3d6279f1602e263cfc0456cb6238d2c206b0f83ac05", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 512, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 512, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 2 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 16, "bytes": 64 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 2, "threads": 512, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 567, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 217.75, "control": 219.084, "speedup": 1.006126291618829 }, "gpu_us": { "candidate": 8.374976459890604, "control": 8.374976459890604, "speedup": 1.0 } } }, { "frozen_register4": { "pairs": 524, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 218.41649999999998, "control": 219.6035, "speedup": 1.0054345711061208 }, "gpu_us": { "candidate": 8.374976459890604, "control": 8.375034667551517, "speedup": 1.0000069501880027 } } }, { "frozen_register4": { "pairs": 569, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 218.042, "control": 217.417, "speedup": 0.9971335797690353 }, "gpu_us": { "candidate": 8.374976459890604, "control": 8.375034667551517, "speedup": 1.0000069501880027 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0028898084749458, "round_speedups": [ 1.006126291618829, 1.0054345711061208, 0.9971335797690353 ], "candidate": 218.06932939864552, "control": 218.69950799486742 }, "gpu_us": { "speedup": 1.0000046334533013, "round_speedups": [ 1.0, 1.0000069501880027, 1.0000069501880027 ], "candidate": 8.374976459890606, "control": 8.375015264952932 } } } }, { "name": "float32_256x1009", "dtype": "float32", "batches": 256, "width": 1009, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "7bf6ce415ddd84786a2d450acbead1c0e25e5540b52b07d28c1e7796b91c7626", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "c1d33e27fc56debd55c6a508dc39b24b01c51c4f01d8ebe463b73c7d94ad343d", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 566, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 219.16649999999998, "control": 217.7295, "speedup": 0.9934433410215522 }, "gpu_us": { "candidate": 8.375034667551517, "control": 8.375034667551517, "speedup": 1.0 } } }, { "frozen_register4": { "pairs": 566, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 219.083, "control": 218.10399999999998, "speedup": 0.9955313739541635 }, "gpu_us": { "candidate": 8.374976459890604, "control": 8.416653145104647, "speedup": 1.0049763346098513 } } }, { "frozen_register4": { "pairs": 445, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 220.958, "control": 219.75, "speedup": 0.9945328976547579 }, "gpu_us": { "candidate": 8.375034667551517, "control": 8.416653145104647, "speedup": 1.0049693498839327 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9945021719686397, "round_speedups": [ 0.9934433410215522, 0.9955313739541635, 0.9945328976547579 ], "candidate": 219.73413439488618, "control": 218.52607391136337 }, "gpu_us": { "speedup": 1.0033124865313527, "round_speedups": [ 1.0, 1.0049763346098513, 1.0049693498839327 ], "candidate": 8.375015264952932, "control": 8.40275739021796 } } } }, { "name": "float32_256x1009", "dtype": "float32", "batches": 256, "width": 1009, "status": "measured", "variant": { "name": "register4_blocked4", "elements_per_thread": 4, "layout": "blocked4" }, "input_sha256": "7bf6ce415ddd84786a2d450acbead1c0e25e5540b52b07d28c1e7796b91c7626", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int((((_metile_bounded_thread >> 8) & 1u) << 0) | (((_metile_bounded_thread >> 9) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 6) & 1u) << 8) | (((_metile_bounded_thread >> 7) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 8) & 1u) << 0) | (((_metile_register_packed_ >> 9) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 6) & 1u) << 8) | (((_metile_register_packed_ >> 7) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 8) & 1u) << 0) | (((_metile_register_packed__ >> 9) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 6) & 1u) << 8) | (((_metile_register_packed__ >> 7) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 8) & 1u) << 0) | (((_metile_register_packed___ >> 9) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 6) & 1u) << 8) | (((_metile_register_packed___ >> 7) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = float4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n float _metile_v20_r0 = _metile_vector_load[0];\n float _metile_v20_r1 = _metile_vector_load[1];\n float _metile_v20_r2 = _metile_vector_load[2];\n float _metile_v20_r3 = _metile_vector_load[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float4 _metile_vector_load_;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load_ = float4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load_[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load_[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load_[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load_[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n float _metile_v36_r0 = _metile_vector_load_[0];\n float _metile_v36_r1 = _metile_vector_load_[1];\n float _metile_v36_r2 = _metile_vector_load_[2];\n float _metile_v36_r3 = _metile_vector_load_[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_float4(float4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n}", "source_sha256": "9c1852dfc63c9d26d086e577f959fcc52d4398d11ea3c1c13748f723d2747516", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 2, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 2, "grouped_stores": 1 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 560, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 217.2295, "control": 216.563, "speedup": 0.9969318163509099 }, "gpu_us": { "candidate": 9.374984074383974, "control": 8.375034667551517, "speedup": 0.8933385487486107 } } }, { "frozen_register4": { "pairs": 550, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 218.042, "control": 218.14600000000002, "speedup": 1.0004769723264326 }, "gpu_us": { "candidate": 9.374984074383974, "control": 8.416653145104647, "speedup": 0.8977778605621473 } } }, { "frozen_register4": { "pairs": 468, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 213.45850000000002, "control": 209.35399999999998, "speedup": 0.9807714380078562 }, "gpu_us": { "candidate": 9.45833744481206, "control": 8.416653145104647, "speedup": 0.8898660249979999 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9926895599131785, "round_speedups": [ 0.9969318163509099, 1.0004769723264326, 0.9807714380078562 ], "candidate": 216.2340773842852, "control": 214.65331111683798 }, "gpu_us": { "speedup": 0.8936549473006019, "round_speedups": [ 0.8933385487486107, 0.8977778605621473, 0.8898660249979999 ], "candidate": 9.402686591283976, "control": 8.40275739021796 } } } }, { "name": "float32_256x1009", "dtype": "float32", "batches": 256, "width": 1009, "status": "measured", "variant": { "name": "register8_striped", "elements_per_thread": 8, "layout": "striped" }, "input_sha256": "7bf6ce415ddd84786a2d450acbead1c0e25e5540b52b07d28c1e7796b91c7626", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 127;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 128;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 256;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 384;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 512;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 640;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 768;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 896;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n float _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n float _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n float _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_____ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum______ = _metile_register_sum____ + _metile_register_sum_____;\n threadgroup float _metile_register_reduction[4];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 4u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n float _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n float _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n float _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n}", "source_sha256": "81a1ee1fc79ce28ef50cf43c835b1d4e5d87eb35125d922f384a1baeea3fdb7d", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 128, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 128, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 8 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 4, "bytes": 16 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 8, "threads": 128, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 564, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 213.6455, "control": 210.3545, "speedup": 0.9845959779166891 }, "gpu_us": { "candidate": 8.375034667551517, "control": 8.416653145104647, "speedup": 1.0049693498839327 } } }, { "frozen_register4": { "pairs": 566, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 214.208, "control": 214.2295, "speedup": 1.0001003697340902 }, "gpu_us": { "candidate": 8.375034667551517, "control": 8.41671135276556, "speedup": 1.0049763000236305 } } }, { "frozen_register4": { "pairs": 490, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 220.4375, "control": 217.60399999999998, "speedup": 0.9871460164445703 }, "gpu_us": { "candidate": 8.416653145104647, "control": 8.45832983031869, "speedup": 1.0049516933269709 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9905909306667203, "round_speedups": [ 0.9845959779166891, 1.0001003697340902, 0.9871460164445703 ], "candidate": 216.0752235694515, "control": 214.04215680968264 }, "gpu_us": { "speedup": 1.0049657810248014, "round_speedups": [ 1.0049693498839327, 1.0049763000236305, 1.0049516933269709 ], "candidate": 8.388884576992352, "control": 8.43054194084403 } } } }, { "name": "float32_256x1009", "dtype": "float32", "batches": 256, "width": 1009, "status": "measured", "variant": { "name": "register8_blocked4", "elements_per_thread": 8, "layout": "blocked4" }, "input_sha256": "7bf6ce415ddd84786a2d450acbead1c0e25e5540b52b07d28c1e7796b91c7626", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 127;\n int _metile_register_index = int((((_metile_bounded_thread >> 7) & 1u) << 0) | (((_metile_bounded_thread >> 8) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 6) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 128;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 7) & 1u) << 0) | (((_metile_register_packed_ >> 8) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 6) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 256;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 7) & 1u) << 0) | (((_metile_register_packed__ >> 8) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 6) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 384;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 7) & 1u) << 0) | (((_metile_register_packed___ >> 8) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 6) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 512;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 7) & 1u) << 0) | (((_metile_register_packed____ >> 8) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 5) & 1u) << 7) | (((_metile_register_packed____ >> 6) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 640;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 7) & 1u) << 0) | (((_metile_register_packed_____ >> 8) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 5) & 1u) << 7) | (((_metile_register_packed_____ >> 6) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 768;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 7) & 1u) << 0) | (((_metile_register_packed______ >> 8) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 5) & 1u) << 7) | (((_metile_register_packed______ >> 6) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 896;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 7) & 1u) << 0) | (((_metile_register_packed_______ >> 8) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 5) & 1u) << 7) | (((_metile_register_packed_______ >> 6) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n float4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = float4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n float _metile_v20_r0 = _metile_vector_load[0];\n float _metile_v20_r1 = _metile_vector_load[1];\n float _metile_v20_r2 = _metile_vector_load[2];\n float _metile_v20_r3 = _metile_vector_load[3];\n float4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = float4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n float _metile_v20_r4 = _metile_vector_load_[0];\n float _metile_v20_r5 = _metile_vector_load_[1];\n float _metile_v20_r6 = _metile_vector_load_[2];\n float _metile_v20_r7 = _metile_vector_load_[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_____ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum______ = _metile_register_sum____ + _metile_register_sum_____;\n threadgroup float _metile_register_reduction[4];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 4u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n float4 _metile_vector_load__;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load__ = float4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load__[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load__[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load__[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load__[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n float _metile_v36_r0 = _metile_vector_load__[0];\n float _metile_v36_r1 = _metile_vector_load__[1];\n float _metile_v36_r2 = _metile_vector_load__[2];\n float _metile_v36_r3 = _metile_vector_load__[3];\n float4 _metile_vector_load___;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load___ = float4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load___[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load___[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load___[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load___[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n float _metile_v36_r4 = _metile_vector_load___[0];\n float _metile_v36_r5 = _metile_vector_load___[1];\n float _metile_v36_r6 = _metile_vector_load___[2];\n float _metile_v36_r7 = _metile_vector_load___[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_float4(float4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_float4(float4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n}", "source_sha256": "9f08087b05ab0b6f116b5c1e98de9acc212cb296d3daf05cb3d563f20cdce2ce", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 128, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 128, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 8 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 4, "bytes": 16 } ], "double_buffered": false, "vectorized_loads": 4, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 8, "threads": 128, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 4, "grouped_stores": 2 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 465, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 222.209, "control": 218.834, "speedup": 0.9848115962899793 }, "gpu_us": { "candidate": 9.83336940407753, "control": 8.500006515532732, "speedup": 0.8644042714400719 } } }, { "frozen_register4": { "pairs": 552, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 218.25, "control": 216.75, "speedup": 0.993127147766323 }, "gpu_us": { "candidate": 9.749986929818988, "control": 8.416653145104647, "speedup": 0.863247633631536 } } }, { "frozen_register4": { "pairs": 565, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 217.083, "control": 215.958, "speedup": 0.9948176503917856 }, "gpu_us": { "candidate": 9.708339348435402, "control": 8.375034667551517, "speedup": 0.8626639806221071 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9909091299400032, "round_speedups": [ 0.9848115962899793, 0.993127147766323, 0.9948176503917856 ], "candidate": 219.16972902306577, "control": 217.17728549543247 }, "gpu_us": { "speedup": 0.863438325764769, "round_speedups": [ 0.8644042714400719, 0.863247633631536, 0.8626639806221071 ], "candidate": 9.763760370186786, "control": 8.430404907202481 } } } }, { "name": "float32_256x1009", "dtype": "float32", "batches": 256, "width": 1009, "status": "measured", "variant": { "name": "register16_striped", "elements_per_thread": 16, "layout": "striped" }, "input_sha256": "7bf6ce415ddd84786a2d450acbead1c0e25e5540b52b07d28c1e7796b91c7626", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 63;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 64;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 128;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 192;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 256;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 320;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 384;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 448;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n int _metile_register_packed________ = _metile_bounded_thread + 512;\n int _metile_register_index________ = int(_metile_register_packed________);\n int _metile_register_packed_________ = _metile_bounded_thread + 576;\n int _metile_register_index_________ = int(_metile_register_packed_________);\n int _metile_register_packed__________ = _metile_bounded_thread + 640;\n int _metile_register_index__________ = int(_metile_register_packed__________);\n int _metile_register_packed___________ = _metile_bounded_thread + 704;\n int _metile_register_index___________ = int(_metile_register_packed___________);\n int _metile_register_packed____________ = _metile_bounded_thread + 768;\n int _metile_register_index____________ = int(_metile_register_packed____________);\n int _metile_register_packed_____________ = _metile_bounded_thread + 832;\n int _metile_register_index_____________ = int(_metile_register_packed_____________);\n int _metile_register_packed______________ = _metile_bounded_thread + 896;\n int _metile_register_index______________ = int(_metile_register_packed______________);\n int _metile_register_packed_______________ = _metile_bounded_thread + 960;\n int _metile_register_index_______________ = int(_metile_register_packed_______________);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v17_r8 = _metile_register_index________ < 1009;\n bool _metile_v17_r9 = _metile_register_index_________ < 1009;\n bool _metile_v17_r10 = _metile_register_index__________ < 1009;\n bool _metile_v17_r11 = _metile_register_index___________ < 1009;\n bool _metile_v17_r12 = _metile_register_index____________ < 1009;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v17_r14 = _metile_register_index______________ < 1009;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n float _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n float _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n float _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n float _metile_v20_r8 = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n float _metile_v20_r9 = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n float _metile_v20_r10 = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n float _metile_v20_r11 = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n float _metile_v20_r12 = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n float _metile_v20_r13 = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n float _metile_v20_r14 = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n float _metile_v20_r15 = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________ = _metile_register_sum____________ + _metile_register_sum_____________;\n threadgroup float _metile_register_reduction[2];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______________);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 2u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v33_r8 = _metile_register_index________ < 1009;\n bool _metile_v33_r9 = _metile_register_index_________ < 1009;\n bool _metile_v33_r10 = _metile_register_index__________ < 1009;\n bool _metile_v33_r11 = _metile_register_index___________ < 1009;\n bool _metile_v33_r12 = _metile_register_index____________ < 1009;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v33_r14 = _metile_register_index______________ < 1009;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n float _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n float _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n float _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n float _metile_v36_r8 = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n float _metile_v36_r9 = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n float _metile_v36_r10 = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n float _metile_v36_r11 = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n float _metile_v36_r12 = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n float _metile_v36_r13 = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n float _metile_v36_r14 = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n float _metile_v36_r15 = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v42_r8 = _metile_register_index________ < 1009;\n bool _metile_v42_r9 = _metile_register_index_________ < 1009;\n bool _metile_v42_r10 = _metile_register_index__________ < 1009;\n bool _metile_v42_r11 = _metile_register_index___________ < 1009;\n bool _metile_v42_r12 = _metile_register_index____________ < 1009;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v42_r14 = _metile_register_index______________ < 1009;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = _metile_v39_r8; }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = _metile_v39_r9; }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = _metile_v39_r10; }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = _metile_v39_r11; }\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = _metile_v39_r12; }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = _metile_v39_r13; }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = _metile_v39_r14; }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = _metile_v39_r15; }\n}", "source_sha256": "33426fa20c0c7f16979a8494e3077f7df7a4e0321c1045d73ed33afeb179b8e5", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 64, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 64, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 16 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 2, "bytes": 8 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 16, "threads": 64, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 572, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 215.5625, "control": 216.458, "speedup": 1.0041542476080023 }, "gpu_us": { "candidate": 8.500006515532732, "control": 8.375034667551517, "speedup": 0.9852974409192694 } } }, { "frozen_register4": { "pairs": 557, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 217.0, "control": 216.625, "speedup": 0.9982718894009217 }, "gpu_us": { "candidate": 8.500006515532732, "control": 8.416653145104647, "speedup": 0.9901937286429408 } } }, { "frozen_register4": { "pairs": 569, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 217.5, "control": 217.25, "speedup": 0.9988505747126437 }, "gpu_us": { "candidate": 8.500006515532732, "control": 8.375034667551517, "speedup": 0.9852974409192694 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0004220725999036, "round_speedups": [ 1.0041542476080023, 0.9982718894009217, 0.9988505747126437 ], "candidate": 216.68594162020096, "control": 216.77739881894308 }, "gpu_us": { "speedup": 0.9869268407809664, "round_speedups": [ 0.9852974409192694, 0.9901937286429408, 0.9852974409192694 ], "candidate": 8.50000651553273, "control": 8.388884576992352 } } } }, { "name": "float32_256x1009", "dtype": "float32", "batches": 256, "width": 1009, "status": "measured", "variant": { "name": "register16_blocked4", "elements_per_thread": 16, "layout": "blocked4" }, "input_sha256": "7bf6ce415ddd84786a2d450acbead1c0e25e5540b52b07d28c1e7796b91c7626", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 63;\n int _metile_register_index = int((((_metile_bounded_thread >> 6) & 1u) << 0) | (((_metile_bounded_thread >> 7) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 8) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 64;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 6) & 1u) << 0) | (((_metile_register_packed_ >> 7) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 8) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 128;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 6) & 1u) << 0) | (((_metile_register_packed__ >> 7) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 8) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 192;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 6) & 1u) << 0) | (((_metile_register_packed___ >> 7) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 8) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 256;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 6) & 1u) << 0) | (((_metile_register_packed____ >> 7) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 5) & 1u) << 7) | (((_metile_register_packed____ >> 8) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 320;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 6) & 1u) << 0) | (((_metile_register_packed_____ >> 7) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 5) & 1u) << 7) | (((_metile_register_packed_____ >> 8) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 384;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 6) & 1u) << 0) | (((_metile_register_packed______ >> 7) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 5) & 1u) << 7) | (((_metile_register_packed______ >> 8) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 448;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 6) & 1u) << 0) | (((_metile_register_packed_______ >> 7) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 5) & 1u) << 7) | (((_metile_register_packed_______ >> 8) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n int _metile_register_packed________ = _metile_bounded_thread + 512;\n int _metile_register_index________ = int((((_metile_register_packed________ >> 6) & 1u) << 0) | (((_metile_register_packed________ >> 7) & 1u) << 1) | (((_metile_register_packed________ >> 0) & 1u) << 2) | (((_metile_register_packed________ >> 1) & 1u) << 3) | (((_metile_register_packed________ >> 2) & 1u) << 4) | (((_metile_register_packed________ >> 3) & 1u) << 5) | (((_metile_register_packed________ >> 4) & 1u) << 6) | (((_metile_register_packed________ >> 5) & 1u) << 7) | (((_metile_register_packed________ >> 8) & 1u) << 8) | (((_metile_register_packed________ >> 9) & 1u) << 9));\n int _metile_register_packed_________ = _metile_bounded_thread + 576;\n int _metile_register_index_________ = int((((_metile_register_packed_________ >> 6) & 1u) << 0) | (((_metile_register_packed_________ >> 7) & 1u) << 1) | (((_metile_register_packed_________ >> 0) & 1u) << 2) | (((_metile_register_packed_________ >> 1) & 1u) << 3) | (((_metile_register_packed_________ >> 2) & 1u) << 4) | (((_metile_register_packed_________ >> 3) & 1u) << 5) | (((_metile_register_packed_________ >> 4) & 1u) << 6) | (((_metile_register_packed_________ >> 5) & 1u) << 7) | (((_metile_register_packed_________ >> 8) & 1u) << 8) | (((_metile_register_packed_________ >> 9) & 1u) << 9));\n int _metile_register_packed__________ = _metile_bounded_thread + 640;\n int _metile_register_index__________ = int((((_metile_register_packed__________ >> 6) & 1u) << 0) | (((_metile_register_packed__________ >> 7) & 1u) << 1) | (((_metile_register_packed__________ >> 0) & 1u) << 2) | (((_metile_register_packed__________ >> 1) & 1u) << 3) | (((_metile_register_packed__________ >> 2) & 1u) << 4) | (((_metile_register_packed__________ >> 3) & 1u) << 5) | (((_metile_register_packed__________ >> 4) & 1u) << 6) | (((_metile_register_packed__________ >> 5) & 1u) << 7) | (((_metile_register_packed__________ >> 8) & 1u) << 8) | (((_metile_register_packed__________ >> 9) & 1u) << 9));\n int _metile_register_packed___________ = _metile_bounded_thread + 704;\n int _metile_register_index___________ = int((((_metile_register_packed___________ >> 6) & 1u) << 0) | (((_metile_register_packed___________ >> 7) & 1u) << 1) | (((_metile_register_packed___________ >> 0) & 1u) << 2) | (((_metile_register_packed___________ >> 1) & 1u) << 3) | (((_metile_register_packed___________ >> 2) & 1u) << 4) | (((_metile_register_packed___________ >> 3) & 1u) << 5) | (((_metile_register_packed___________ >> 4) & 1u) << 6) | (((_metile_register_packed___________ >> 5) & 1u) << 7) | (((_metile_register_packed___________ >> 8) & 1u) << 8) | (((_metile_register_packed___________ >> 9) & 1u) << 9));\n int _metile_register_packed____________ = _metile_bounded_thread + 768;\n int _metile_register_index____________ = int((((_metile_register_packed____________ >> 6) & 1u) << 0) | (((_metile_register_packed____________ >> 7) & 1u) << 1) | (((_metile_register_packed____________ >> 0) & 1u) << 2) | (((_metile_register_packed____________ >> 1) & 1u) << 3) | (((_metile_register_packed____________ >> 2) & 1u) << 4) | (((_metile_register_packed____________ >> 3) & 1u) << 5) | (((_metile_register_packed____________ >> 4) & 1u) << 6) | (((_metile_register_packed____________ >> 5) & 1u) << 7) | (((_metile_register_packed____________ >> 8) & 1u) << 8) | (((_metile_register_packed____________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________ = _metile_bounded_thread + 832;\n int _metile_register_index_____________ = int((((_metile_register_packed_____________ >> 6) & 1u) << 0) | (((_metile_register_packed_____________ >> 7) & 1u) << 1) | (((_metile_register_packed_____________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________ >> 5) & 1u) << 7) | (((_metile_register_packed_____________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________ >> 9) & 1u) << 9));\n int _metile_register_packed______________ = _metile_bounded_thread + 896;\n int _metile_register_index______________ = int((((_metile_register_packed______________ >> 6) & 1u) << 0) | (((_metile_register_packed______________ >> 7) & 1u) << 1) | (((_metile_register_packed______________ >> 0) & 1u) << 2) | (((_metile_register_packed______________ >> 1) & 1u) << 3) | (((_metile_register_packed______________ >> 2) & 1u) << 4) | (((_metile_register_packed______________ >> 3) & 1u) << 5) | (((_metile_register_packed______________ >> 4) & 1u) << 6) | (((_metile_register_packed______________ >> 5) & 1u) << 7) | (((_metile_register_packed______________ >> 8) & 1u) << 8) | (((_metile_register_packed______________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________ = _metile_bounded_thread + 960;\n int _metile_register_index_______________ = int((((_metile_register_packed_______________ >> 6) & 1u) << 0) | (((_metile_register_packed_______________ >> 7) & 1u) << 1) | (((_metile_register_packed_______________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________ >> 5) & 1u) << 7) | (((_metile_register_packed_______________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v17_r8 = _metile_register_index________ < 1009;\n bool _metile_v17_r9 = _metile_register_index_________ < 1009;\n bool _metile_v17_r10 = _metile_register_index__________ < 1009;\n bool _metile_v17_r11 = _metile_register_index___________ < 1009;\n bool _metile_v17_r12 = _metile_register_index____________ < 1009;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v17_r14 = _metile_register_index______________ < 1009;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n float4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = float4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n float _metile_v20_r0 = _metile_vector_load[0];\n float _metile_v20_r1 = _metile_vector_load[1];\n float _metile_v20_r2 = _metile_vector_load[2];\n float _metile_v20_r3 = _metile_vector_load[3];\n float4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = float4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n float _metile_v20_r4 = _metile_vector_load_[0];\n float _metile_v20_r5 = _metile_vector_load_[1];\n float _metile_v20_r6 = _metile_vector_load_[2];\n float _metile_v20_r7 = _metile_vector_load_[3];\n float4 _metile_vector_load__;\n if ((_metile_v18_r8) && (_metile_v18_r9) && (_metile_v18_r10) && (_metile_v18_r11) && (long(_off__metile_v19_r9) == long(_off__metile_v19_r8) + 1) && (long(_off__metile_v19_r10) == long(_off__metile_v19_r8) + 2) && (long(_off__metile_v19_r11) == long(_off__metile_v19_r8) + 3)) {\n _metile_vector_load__ = float4(*reinterpret_cast(X + _off__metile_v19_r8));\n } else {\n _metile_vector_load__[0] = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n _metile_vector_load__[1] = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n _metile_vector_load__[2] = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n _metile_vector_load__[3] = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n }\n float _metile_v20_r8 = _metile_vector_load__[0];\n float _metile_v20_r9 = _metile_vector_load__[1];\n float _metile_v20_r10 = _metile_vector_load__[2];\n float _metile_v20_r11 = _metile_vector_load__[3];\n float4 _metile_vector_load___;\n if ((_metile_v18_r12) && (_metile_v18_r13) && (_metile_v18_r14) && (_metile_v18_r15) && (long(_off__metile_v19_r13) == long(_off__metile_v19_r12) + 1) && (long(_off__metile_v19_r14) == long(_off__metile_v19_r12) + 2) && (long(_off__metile_v19_r15) == long(_off__metile_v19_r12) + 3)) {\n _metile_vector_load___ = float4(*reinterpret_cast(X + _off__metile_v19_r12));\n } else {\n _metile_vector_load___[0] = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n _metile_vector_load___[1] = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n _metile_vector_load___[2] = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n _metile_vector_load___[3] = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n }\n float _metile_v20_r12 = _metile_vector_load___[0];\n float _metile_v20_r13 = _metile_vector_load___[1];\n float _metile_v20_r14 = _metile_vector_load___[2];\n float _metile_v20_r15 = _metile_vector_load___[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________ = _metile_register_sum____________ + _metile_register_sum_____________;\n threadgroup float _metile_register_reduction[2];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______________);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 2u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v33_r8 = _metile_register_index________ < 1009;\n bool _metile_v33_r9 = _metile_register_index_________ < 1009;\n bool _metile_v33_r10 = _metile_register_index__________ < 1009;\n bool _metile_v33_r11 = _metile_register_index___________ < 1009;\n bool _metile_v33_r12 = _metile_register_index____________ < 1009;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v33_r14 = _metile_register_index______________ < 1009;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n float4 _metile_vector_load____;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load____ = float4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load____[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load____[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load____[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load____[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n float _metile_v36_r0 = _metile_vector_load____[0];\n float _metile_v36_r1 = _metile_vector_load____[1];\n float _metile_v36_r2 = _metile_vector_load____[2];\n float _metile_v36_r3 = _metile_vector_load____[3];\n float4 _metile_vector_load_____;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load_____ = float4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load_____[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load_____[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load_____[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load_____[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n float _metile_v36_r4 = _metile_vector_load_____[0];\n float _metile_v36_r5 = _metile_vector_load_____[1];\n float _metile_v36_r6 = _metile_vector_load_____[2];\n float _metile_v36_r7 = _metile_vector_load_____[3];\n float4 _metile_vector_load______;\n if ((_metile_v34_r8) && (_metile_v34_r9) && (_metile_v34_r10) && (_metile_v34_r11) && (long(_metile_register_index_________) == long(_metile_register_index________) + 1) && (long(_metile_register_index__________) == long(_metile_register_index________) + 2) && (long(_metile_register_index___________) == long(_metile_register_index________) + 3)) {\n _metile_vector_load______ = float4(*reinterpret_cast(W + _metile_register_index________));\n } else {\n _metile_vector_load______[0] = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n _metile_vector_load______[1] = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n _metile_vector_load______[2] = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n _metile_vector_load______[3] = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n }\n float _metile_v36_r8 = _metile_vector_load______[0];\n float _metile_v36_r9 = _metile_vector_load______[1];\n float _metile_v36_r10 = _metile_vector_load______[2];\n float _metile_v36_r11 = _metile_vector_load______[3];\n float4 _metile_vector_load_______;\n if ((_metile_v34_r12) && (_metile_v34_r13) && (_metile_v34_r14) && (_metile_v34_r15) && (long(_metile_register_index_____________) == long(_metile_register_index____________) + 1) && (long(_metile_register_index______________) == long(_metile_register_index____________) + 2) && (long(_metile_register_index_______________) == long(_metile_register_index____________) + 3)) {\n _metile_vector_load_______ = float4(*reinterpret_cast(W + _metile_register_index____________));\n } else {\n _metile_vector_load_______[0] = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n _metile_vector_load_______[1] = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n _metile_vector_load_______[2] = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n _metile_vector_load_______[3] = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n }\n float _metile_v36_r12 = _metile_vector_load_______[0];\n float _metile_v36_r13 = _metile_vector_load_______[1];\n float _metile_v36_r14 = _metile_vector_load_______[2];\n float _metile_v36_r15 = _metile_vector_load_______[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v42_r8 = _metile_register_index________ < 1009;\n bool _metile_v42_r9 = _metile_register_index_________ < 1009;\n bool _metile_v42_r10 = _metile_register_index__________ < 1009;\n bool _metile_v42_r11 = _metile_register_index___________ < 1009;\n bool _metile_v42_r12 = _metile_register_index____________ < 1009;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v42_r14 = _metile_register_index______________ < 1009;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_float4(float4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_float4(float4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n if ((_metile_v43_r8) && (_metile_v43_r9) && (_metile_v43_r10) && (_metile_v43_r11) && (long(_off__metile_v44_r9) == long(_off__metile_v44_r8) + 1) && (long(_off__metile_v44_r10) == long(_off__metile_v44_r8) + 2) && (long(_off__metile_v44_r11) == long(_off__metile_v44_r8) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r8) = packed_float4(float4(static_cast(_metile_v39_r8), static_cast(_metile_v39_r9), static_cast(_metile_v39_r10), static_cast(_metile_v39_r11)));\n } else {\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = static_cast(_metile_v39_r8); }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = static_cast(_metile_v39_r9); }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = static_cast(_metile_v39_r10); }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = static_cast(_metile_v39_r11); }\n }\n if ((_metile_v43_r12) && (_metile_v43_r13) && (_metile_v43_r14) && (_metile_v43_r15) && (long(_off__metile_v44_r13) == long(_off__metile_v44_r12) + 1) && (long(_off__metile_v44_r14) == long(_off__metile_v44_r12) + 2) && (long(_off__metile_v44_r15) == long(_off__metile_v44_r12) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r12) = packed_float4(float4(static_cast(_metile_v39_r12), static_cast(_metile_v39_r13), static_cast(_metile_v39_r14), static_cast(_metile_v39_r15)));\n } else {\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = static_cast(_metile_v39_r12); }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = static_cast(_metile_v39_r13); }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = static_cast(_metile_v39_r14); }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = static_cast(_metile_v39_r15); }\n }\n}", "source_sha256": "2617a2e2182b7192b8def8bf914a9cd9d48eed7adf610815901d9692d304fd01", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 64, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 64, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 16 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 2, "bytes": 8 } ], "double_buffered": false, "vectorized_loads": 8, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 16, "threads": 64, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 8, "grouped_stores": 4 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 563, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 218.625, "control": 216.167, "speedup": 0.988757004002287 }, "gpu_us": { "candidate": 9.750016033649445, "control": 8.416653145104647, "speedup": 0.8632450568344636 } } }, { "frozen_register4": { "pairs": 564, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 218.5205, "control": 218.125, "speedup": 0.9981901011575574 }, "gpu_us": { "candidate": 9.750016033649445, "control": 8.416653145104647, "speedup": 0.8632450568344636 } } }, { "frozen_register4": { "pairs": 565, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 220.208, "control": 218.75, "speedup": 0.9933789871394318 }, "gpu_us": { "candidate": 9.750016033649445, "control": 8.416653145104647, "speedup": 0.8632450568344636 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9934345659568081, "round_speedups": [ 0.988757004002287, 0.9981901011575574, 0.9933789871394318 ], "candidate": 219.11647543614237, "control": 217.67788066888957 }, "gpu_us": { "speedup": 0.8632450568344636, "round_speedups": [ 0.8632450568344636, 0.8632450568344636, 0.8632450568344636 ], "candidate": 9.750016033649446, "control": 8.416653145104648 } } } }, { "name": "float32_256x1009", "dtype": "float32", "batches": 256, "width": 1009, "status": "measured", "variant": { "name": "register32_striped", "elements_per_thread": 32, "layout": "striped" }, "input_sha256": "7bf6ce415ddd84786a2d450acbead1c0e25e5540b52b07d28c1e7796b91c7626", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 31;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 32;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 64;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 96;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 128;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 160;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 192;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 224;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n int _metile_register_packed________ = _metile_bounded_thread + 256;\n int _metile_register_index________ = int(_metile_register_packed________);\n int _metile_register_packed_________ = _metile_bounded_thread + 288;\n int _metile_register_index_________ = int(_metile_register_packed_________);\n int _metile_register_packed__________ = _metile_bounded_thread + 320;\n int _metile_register_index__________ = int(_metile_register_packed__________);\n int _metile_register_packed___________ = _metile_bounded_thread + 352;\n int _metile_register_index___________ = int(_metile_register_packed___________);\n int _metile_register_packed____________ = _metile_bounded_thread + 384;\n int _metile_register_index____________ = int(_metile_register_packed____________);\n int _metile_register_packed_____________ = _metile_bounded_thread + 416;\n int _metile_register_index_____________ = int(_metile_register_packed_____________);\n int _metile_register_packed______________ = _metile_bounded_thread + 448;\n int _metile_register_index______________ = int(_metile_register_packed______________);\n int _metile_register_packed_______________ = _metile_bounded_thread + 480;\n int _metile_register_index_______________ = int(_metile_register_packed_______________);\n int _metile_register_packed________________ = _metile_bounded_thread + 512;\n int _metile_register_index________________ = int(_metile_register_packed________________);\n int _metile_register_packed_________________ = _metile_bounded_thread + 544;\n int _metile_register_index_________________ = int(_metile_register_packed_________________);\n int _metile_register_packed__________________ = _metile_bounded_thread + 576;\n int _metile_register_index__________________ = int(_metile_register_packed__________________);\n int _metile_register_packed___________________ = _metile_bounded_thread + 608;\n int _metile_register_index___________________ = int(_metile_register_packed___________________);\n int _metile_register_packed____________________ = _metile_bounded_thread + 640;\n int _metile_register_index____________________ = int(_metile_register_packed____________________);\n int _metile_register_packed_____________________ = _metile_bounded_thread + 672;\n int _metile_register_index_____________________ = int(_metile_register_packed_____________________);\n int _metile_register_packed______________________ = _metile_bounded_thread + 704;\n int _metile_register_index______________________ = int(_metile_register_packed______________________);\n int _metile_register_packed_______________________ = _metile_bounded_thread + 736;\n int _metile_register_index_______________________ = int(_metile_register_packed_______________________);\n int _metile_register_packed________________________ = _metile_bounded_thread + 768;\n int _metile_register_index________________________ = int(_metile_register_packed________________________);\n int _metile_register_packed_________________________ = _metile_bounded_thread + 800;\n int _metile_register_index_________________________ = int(_metile_register_packed_________________________);\n int _metile_register_packed__________________________ = _metile_bounded_thread + 832;\n int _metile_register_index__________________________ = int(_metile_register_packed__________________________);\n int _metile_register_packed___________________________ = _metile_bounded_thread + 864;\n int _metile_register_index___________________________ = int(_metile_register_packed___________________________);\n int _metile_register_packed____________________________ = _metile_bounded_thread + 896;\n int _metile_register_index____________________________ = int(_metile_register_packed____________________________);\n int _metile_register_packed_____________________________ = _metile_bounded_thread + 928;\n int _metile_register_index_____________________________ = int(_metile_register_packed_____________________________);\n int _metile_register_packed______________________________ = _metile_bounded_thread + 960;\n int _metile_register_index______________________________ = int(_metile_register_packed______________________________);\n int _metile_register_packed_______________________________ = _metile_bounded_thread + 992;\n int _metile_register_index_______________________________ = int(_metile_register_packed_______________________________);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v16_r16 = _metile_register_index________________ >= 0;\n bool _metile_v16_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v16_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v16_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v16_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v16_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v16_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v16_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v16_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v16_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v16_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v16_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v16_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v16_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v16_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v16_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v17_r8 = _metile_register_index________ < 1009;\n bool _metile_v17_r9 = _metile_register_index_________ < 1009;\n bool _metile_v17_r10 = _metile_register_index__________ < 1009;\n bool _metile_v17_r11 = _metile_register_index___________ < 1009;\n bool _metile_v17_r12 = _metile_register_index____________ < 1009;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v17_r14 = _metile_register_index______________ < 1009;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v17_r16 = _metile_register_index________________ < 1009;\n bool _metile_v17_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v17_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v17_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v17_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v17_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v17_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v17_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v17_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v17_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v17_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v17_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v17_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v17_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v17_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v17_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n bool _metile_v18_r16 = _metile_v16_r16 & _metile_v17_r16;\n bool _metile_v18_r17 = _metile_v16_r17 & _metile_v17_r17;\n bool _metile_v18_r18 = _metile_v16_r18 & _metile_v17_r18;\n bool _metile_v18_r19 = _metile_v16_r19 & _metile_v17_r19;\n bool _metile_v18_r20 = _metile_v16_r20 & _metile_v17_r20;\n bool _metile_v18_r21 = _metile_v16_r21 & _metile_v17_r21;\n bool _metile_v18_r22 = _metile_v16_r22 & _metile_v17_r22;\n bool _metile_v18_r23 = _metile_v16_r23 & _metile_v17_r23;\n bool _metile_v18_r24 = _metile_v16_r24 & _metile_v17_r24;\n bool _metile_v18_r25 = _metile_v16_r25 & _metile_v17_r25;\n bool _metile_v18_r26 = _metile_v16_r26 & _metile_v17_r26;\n bool _metile_v18_r27 = _metile_v16_r27 & _metile_v17_r27;\n bool _metile_v18_r28 = _metile_v16_r28 & _metile_v17_r28;\n bool _metile_v18_r29 = _metile_v16_r29 & _metile_v17_r29;\n bool _metile_v18_r30 = _metile_v16_r30 & _metile_v17_r30;\n bool _metile_v18_r31 = _metile_v16_r31 & _metile_v17_r31;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n int _off__metile_v19_r16 = v2 + _metile_register_index________________;\n int _off__metile_v19_r17 = v2 + _metile_register_index_________________;\n int _off__metile_v19_r18 = v2 + _metile_register_index__________________;\n int _off__metile_v19_r19 = v2 + _metile_register_index___________________;\n int _off__metile_v19_r20 = v2 + _metile_register_index____________________;\n int _off__metile_v19_r21 = v2 + _metile_register_index_____________________;\n int _off__metile_v19_r22 = v2 + _metile_register_index______________________;\n int _off__metile_v19_r23 = v2 + _metile_register_index_______________________;\n int _off__metile_v19_r24 = v2 + _metile_register_index________________________;\n int _off__metile_v19_r25 = v2 + _metile_register_index_________________________;\n int _off__metile_v19_r26 = v2 + _metile_register_index__________________________;\n int _off__metile_v19_r27 = v2 + _metile_register_index___________________________;\n int _off__metile_v19_r28 = v2 + _metile_register_index____________________________;\n int _off__metile_v19_r29 = v2 + _metile_register_index_____________________________;\n int _off__metile_v19_r30 = v2 + _metile_register_index______________________________;\n int _off__metile_v19_r31 = v2 + _metile_register_index_______________________________;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n float _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n float _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n float _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n float _metile_v20_r8 = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n float _metile_v20_r9 = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n float _metile_v20_r10 = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n float _metile_v20_r11 = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n float _metile_v20_r12 = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n float _metile_v20_r13 = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n float _metile_v20_r14 = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n float _metile_v20_r15 = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n float _metile_v20_r16 = _metile_v18_r16 ? X[_off__metile_v19_r16] : static_cast(0);\n float _metile_v20_r17 = _metile_v18_r17 ? X[_off__metile_v19_r17] : static_cast(0);\n float _metile_v20_r18 = _metile_v18_r18 ? X[_off__metile_v19_r18] : static_cast(0);\n float _metile_v20_r19 = _metile_v18_r19 ? X[_off__metile_v19_r19] : static_cast(0);\n float _metile_v20_r20 = _metile_v18_r20 ? X[_off__metile_v19_r20] : static_cast(0);\n float _metile_v20_r21 = _metile_v18_r21 ? X[_off__metile_v19_r21] : static_cast(0);\n float _metile_v20_r22 = _metile_v18_r22 ? X[_off__metile_v19_r22] : static_cast(0);\n float _metile_v20_r23 = _metile_v18_r23 ? X[_off__metile_v19_r23] : static_cast(0);\n float _metile_v20_r24 = _metile_v18_r24 ? X[_off__metile_v19_r24] : static_cast(0);\n float _metile_v20_r25 = _metile_v18_r25 ? X[_off__metile_v19_r25] : static_cast(0);\n float _metile_v20_r26 = _metile_v18_r26 ? X[_off__metile_v19_r26] : static_cast(0);\n float _metile_v20_r27 = _metile_v18_r27 ? X[_off__metile_v19_r27] : static_cast(0);\n float _metile_v20_r28 = _metile_v18_r28 ? X[_off__metile_v19_r28] : static_cast(0);\n float _metile_v20_r29 = _metile_v18_r29 ? X[_off__metile_v19_r29] : static_cast(0);\n float _metile_v20_r30 = _metile_v18_r30 ? X[_off__metile_v19_r30] : static_cast(0);\n float _metile_v20_r31 = _metile_v18_r31 ? X[_off__metile_v19_r31] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v21_r16 = static_cast(_metile_v20_r16);\n float _metile_v21_r17 = static_cast(_metile_v20_r17);\n float _metile_v21_r18 = static_cast(_metile_v20_r18);\n float _metile_v21_r19 = static_cast(_metile_v20_r19);\n float _metile_v21_r20 = static_cast(_metile_v20_r20);\n float _metile_v21_r21 = static_cast(_metile_v20_r21);\n float _metile_v21_r22 = static_cast(_metile_v20_r22);\n float _metile_v21_r23 = static_cast(_metile_v20_r23);\n float _metile_v21_r24 = static_cast(_metile_v20_r24);\n float _metile_v21_r25 = static_cast(_metile_v20_r25);\n float _metile_v21_r26 = static_cast(_metile_v20_r26);\n float _metile_v21_r27 = static_cast(_metile_v20_r27);\n float _metile_v21_r28 = static_cast(_metile_v20_r28);\n float _metile_v21_r29 = static_cast(_metile_v20_r29);\n float _metile_v21_r30 = static_cast(_metile_v20_r30);\n float _metile_v21_r31 = static_cast(_metile_v20_r31);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_v22_r16 = _metile_v21_r16 * _metile_v21_r16;\n float _metile_v22_r17 = _metile_v21_r17 * _metile_v21_r17;\n float _metile_v22_r18 = _metile_v21_r18 * _metile_v21_r18;\n float _metile_v22_r19 = _metile_v21_r19 * _metile_v21_r19;\n float _metile_v22_r20 = _metile_v21_r20 * _metile_v21_r20;\n float _metile_v22_r21 = _metile_v21_r21 * _metile_v21_r21;\n float _metile_v22_r22 = _metile_v21_r22 * _metile_v21_r22;\n float _metile_v22_r23 = _metile_v21_r23 * _metile_v21_r23;\n float _metile_v22_r24 = _metile_v21_r24 * _metile_v21_r24;\n float _metile_v22_r25 = _metile_v21_r25 * _metile_v21_r25;\n float _metile_v22_r26 = _metile_v21_r26 * _metile_v21_r26;\n float _metile_v22_r27 = _metile_v21_r27 * _metile_v21_r27;\n float _metile_v22_r28 = _metile_v21_r28 * _metile_v21_r28;\n float _metile_v22_r29 = _metile_v21_r29 * _metile_v21_r29;\n float _metile_v22_r30 = _metile_v21_r30 * _metile_v21_r30;\n float _metile_v22_r31 = _metile_v21_r31 * _metile_v21_r31;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_v22_r16 + _metile_v22_r17;\n float _metile_register_sum_________ = _metile_v22_r18 + _metile_v22_r19;\n float _metile_register_sum__________ = _metile_v22_r20 + _metile_v22_r21;\n float _metile_register_sum___________ = _metile_v22_r22 + _metile_v22_r23;\n float _metile_register_sum____________ = _metile_v22_r24 + _metile_v22_r25;\n float _metile_register_sum_____________ = _metile_v22_r26 + _metile_v22_r27;\n float _metile_register_sum______________ = _metile_v22_r28 + _metile_v22_r29;\n float _metile_register_sum_______________ = _metile_v22_r30 + _metile_v22_r31;\n float _metile_register_sum________________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________________ = _metile_register_sum____________ + _metile_register_sum_____________;\n float _metile_register_sum_______________________ = _metile_register_sum______________ + _metile_register_sum_______________;\n float _metile_register_sum________________________ = _metile_register_sum________________ + _metile_register_sum_________________;\n float _metile_register_sum_________________________ = _metile_register_sum__________________ + _metile_register_sum___________________;\n float _metile_register_sum__________________________ = _metile_register_sum____________________ + _metile_register_sum_____________________;\n float _metile_register_sum___________________________ = _metile_register_sum______________________ + _metile_register_sum_______________________;\n float _metile_register_sum____________________________ = _metile_register_sum________________________ + _metile_register_sum_________________________;\n float _metile_register_sum_____________________________ = _metile_register_sum__________________________ + _metile_register_sum___________________________;\n float _metile_register_sum______________________________ = _metile_register_sum____________________________ + _metile_register_sum_____________________________;\n float v23 = simd_sum(_metile_register_sum______________________________);\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v32_r16 = _metile_register_index________________ >= 0;\n bool _metile_v32_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v32_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v32_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v32_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v32_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v32_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v32_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v32_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v32_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v32_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v32_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v32_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v32_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v32_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v32_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v33_r8 = _metile_register_index________ < 1009;\n bool _metile_v33_r9 = _metile_register_index_________ < 1009;\n bool _metile_v33_r10 = _metile_register_index__________ < 1009;\n bool _metile_v33_r11 = _metile_register_index___________ < 1009;\n bool _metile_v33_r12 = _metile_register_index____________ < 1009;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v33_r14 = _metile_register_index______________ < 1009;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v33_r16 = _metile_register_index________________ < 1009;\n bool _metile_v33_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v33_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v33_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v33_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v33_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v33_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v33_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v33_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v33_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v33_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v33_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v33_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v33_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v33_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v33_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n bool _metile_v34_r16 = _metile_v32_r16 & _metile_v33_r16;\n bool _metile_v34_r17 = _metile_v32_r17 & _metile_v33_r17;\n bool _metile_v34_r18 = _metile_v32_r18 & _metile_v33_r18;\n bool _metile_v34_r19 = _metile_v32_r19 & _metile_v33_r19;\n bool _metile_v34_r20 = _metile_v32_r20 & _metile_v33_r20;\n bool _metile_v34_r21 = _metile_v32_r21 & _metile_v33_r21;\n bool _metile_v34_r22 = _metile_v32_r22 & _metile_v33_r22;\n bool _metile_v34_r23 = _metile_v32_r23 & _metile_v33_r23;\n bool _metile_v34_r24 = _metile_v32_r24 & _metile_v33_r24;\n bool _metile_v34_r25 = _metile_v32_r25 & _metile_v33_r25;\n bool _metile_v34_r26 = _metile_v32_r26 & _metile_v33_r26;\n bool _metile_v34_r27 = _metile_v32_r27 & _metile_v33_r27;\n bool _metile_v34_r28 = _metile_v32_r28 & _metile_v33_r28;\n bool _metile_v34_r29 = _metile_v32_r29 & _metile_v33_r29;\n bool _metile_v34_r30 = _metile_v32_r30 & _metile_v33_r30;\n bool _metile_v34_r31 = _metile_v32_r31 & _metile_v33_r31;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n float _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n float _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n float _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n float _metile_v36_r8 = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n float _metile_v36_r9 = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n float _metile_v36_r10 = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n float _metile_v36_r11 = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n float _metile_v36_r12 = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n float _metile_v36_r13 = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n float _metile_v36_r14 = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n float _metile_v36_r15 = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n float _metile_v36_r16 = _metile_v34_r16 ? W[_metile_register_index________________] : static_cast(0);\n float _metile_v36_r17 = _metile_v34_r17 ? W[_metile_register_index_________________] : static_cast(0);\n float _metile_v36_r18 = _metile_v34_r18 ? W[_metile_register_index__________________] : static_cast(0);\n float _metile_v36_r19 = _metile_v34_r19 ? W[_metile_register_index___________________] : static_cast(0);\n float _metile_v36_r20 = _metile_v34_r20 ? W[_metile_register_index____________________] : static_cast(0);\n float _metile_v36_r21 = _metile_v34_r21 ? W[_metile_register_index_____________________] : static_cast(0);\n float _metile_v36_r22 = _metile_v34_r22 ? W[_metile_register_index______________________] : static_cast(0);\n float _metile_v36_r23 = _metile_v34_r23 ? W[_metile_register_index_______________________] : static_cast(0);\n float _metile_v36_r24 = _metile_v34_r24 ? W[_metile_register_index________________________] : static_cast(0);\n float _metile_v36_r25 = _metile_v34_r25 ? W[_metile_register_index_________________________] : static_cast(0);\n float _metile_v36_r26 = _metile_v34_r26 ? W[_metile_register_index__________________________] : static_cast(0);\n float _metile_v36_r27 = _metile_v34_r27 ? W[_metile_register_index___________________________] : static_cast(0);\n float _metile_v36_r28 = _metile_v34_r28 ? W[_metile_register_index____________________________] : static_cast(0);\n float _metile_v36_r29 = _metile_v34_r29 ? W[_metile_register_index_____________________________] : static_cast(0);\n float _metile_v36_r30 = _metile_v34_r30 ? W[_metile_register_index______________________________] : static_cast(0);\n float _metile_v36_r31 = _metile_v34_r31 ? W[_metile_register_index_______________________________] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v37_r16 = static_cast(_metile_v36_r16);\n float _metile_v37_r17 = static_cast(_metile_v36_r17);\n float _metile_v37_r18 = static_cast(_metile_v36_r18);\n float _metile_v37_r19 = static_cast(_metile_v36_r19);\n float _metile_v37_r20 = static_cast(_metile_v36_r20);\n float _metile_v37_r21 = static_cast(_metile_v36_r21);\n float _metile_v37_r22 = static_cast(_metile_v36_r22);\n float _metile_v37_r23 = static_cast(_metile_v36_r23);\n float _metile_v37_r24 = static_cast(_metile_v36_r24);\n float _metile_v37_r25 = static_cast(_metile_v36_r25);\n float _metile_v37_r26 = static_cast(_metile_v36_r26);\n float _metile_v37_r27 = static_cast(_metile_v36_r27);\n float _metile_v37_r28 = static_cast(_metile_v36_r28);\n float _metile_v37_r29 = static_cast(_metile_v36_r29);\n float _metile_v37_r30 = static_cast(_metile_v36_r30);\n float _metile_v37_r31 = static_cast(_metile_v36_r31);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v38_r16 = _metile_v21_r16 * v29;\n float _metile_v38_r17 = _metile_v21_r17 * v29;\n float _metile_v38_r18 = _metile_v21_r18 * v29;\n float _metile_v38_r19 = _metile_v21_r19 * v29;\n float _metile_v38_r20 = _metile_v21_r20 * v29;\n float _metile_v38_r21 = _metile_v21_r21 * v29;\n float _metile_v38_r22 = _metile_v21_r22 * v29;\n float _metile_v38_r23 = _metile_v21_r23 * v29;\n float _metile_v38_r24 = _metile_v21_r24 * v29;\n float _metile_v38_r25 = _metile_v21_r25 * v29;\n float _metile_v38_r26 = _metile_v21_r26 * v29;\n float _metile_v38_r27 = _metile_v21_r27 * v29;\n float _metile_v38_r28 = _metile_v21_r28 * v29;\n float _metile_v38_r29 = _metile_v21_r29 * v29;\n float _metile_v38_r30 = _metile_v21_r30 * v29;\n float _metile_v38_r31 = _metile_v21_r31 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n float _metile_v39_r16 = _metile_v38_r16 * _metile_v37_r16;\n float _metile_v39_r17 = _metile_v38_r17 * _metile_v37_r17;\n float _metile_v39_r18 = _metile_v38_r18 * _metile_v37_r18;\n float _metile_v39_r19 = _metile_v38_r19 * _metile_v37_r19;\n float _metile_v39_r20 = _metile_v38_r20 * _metile_v37_r20;\n float _metile_v39_r21 = _metile_v38_r21 * _metile_v37_r21;\n float _metile_v39_r22 = _metile_v38_r22 * _metile_v37_r22;\n float _metile_v39_r23 = _metile_v38_r23 * _metile_v37_r23;\n float _metile_v39_r24 = _metile_v38_r24 * _metile_v37_r24;\n float _metile_v39_r25 = _metile_v38_r25 * _metile_v37_r25;\n float _metile_v39_r26 = _metile_v38_r26 * _metile_v37_r26;\n float _metile_v39_r27 = _metile_v38_r27 * _metile_v37_r27;\n float _metile_v39_r28 = _metile_v38_r28 * _metile_v37_r28;\n float _metile_v39_r29 = _metile_v38_r29 * _metile_v37_r29;\n float _metile_v39_r30 = _metile_v38_r30 * _metile_v37_r30;\n float _metile_v39_r31 = _metile_v38_r31 * _metile_v37_r31;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v41_r16 = _metile_register_index________________ >= 0;\n bool _metile_v41_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v41_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v41_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v41_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v41_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v41_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v41_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v41_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v41_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v41_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v41_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v41_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v41_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v41_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v41_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v42_r8 = _metile_register_index________ < 1009;\n bool _metile_v42_r9 = _metile_register_index_________ < 1009;\n bool _metile_v42_r10 = _metile_register_index__________ < 1009;\n bool _metile_v42_r11 = _metile_register_index___________ < 1009;\n bool _metile_v42_r12 = _metile_register_index____________ < 1009;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v42_r14 = _metile_register_index______________ < 1009;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v42_r16 = _metile_register_index________________ < 1009;\n bool _metile_v42_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v42_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v42_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v42_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v42_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v42_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v42_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v42_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v42_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v42_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v42_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v42_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v42_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v42_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v42_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n bool _metile_v43_r16 = _metile_v41_r16 & _metile_v42_r16;\n bool _metile_v43_r17 = _metile_v41_r17 & _metile_v42_r17;\n bool _metile_v43_r18 = _metile_v41_r18 & _metile_v42_r18;\n bool _metile_v43_r19 = _metile_v41_r19 & _metile_v42_r19;\n bool _metile_v43_r20 = _metile_v41_r20 & _metile_v42_r20;\n bool _metile_v43_r21 = _metile_v41_r21 & _metile_v42_r21;\n bool _metile_v43_r22 = _metile_v41_r22 & _metile_v42_r22;\n bool _metile_v43_r23 = _metile_v41_r23 & _metile_v42_r23;\n bool _metile_v43_r24 = _metile_v41_r24 & _metile_v42_r24;\n bool _metile_v43_r25 = _metile_v41_r25 & _metile_v42_r25;\n bool _metile_v43_r26 = _metile_v41_r26 & _metile_v42_r26;\n bool _metile_v43_r27 = _metile_v41_r27 & _metile_v42_r27;\n bool _metile_v43_r28 = _metile_v41_r28 & _metile_v42_r28;\n bool _metile_v43_r29 = _metile_v41_r29 & _metile_v42_r29;\n bool _metile_v43_r30 = _metile_v41_r30 & _metile_v42_r30;\n bool _metile_v43_r31 = _metile_v41_r31 & _metile_v42_r31;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n int _off__metile_v44_r16 = v9 + _metile_register_index________________;\n int _off__metile_v44_r17 = v9 + _metile_register_index_________________;\n int _off__metile_v44_r18 = v9 + _metile_register_index__________________;\n int _off__metile_v44_r19 = v9 + _metile_register_index___________________;\n int _off__metile_v44_r20 = v9 + _metile_register_index____________________;\n int _off__metile_v44_r21 = v9 + _metile_register_index_____________________;\n int _off__metile_v44_r22 = v9 + _metile_register_index______________________;\n int _off__metile_v44_r23 = v9 + _metile_register_index_______________________;\n int _off__metile_v44_r24 = v9 + _metile_register_index________________________;\n int _off__metile_v44_r25 = v9 + _metile_register_index_________________________;\n int _off__metile_v44_r26 = v9 + _metile_register_index__________________________;\n int _off__metile_v44_r27 = v9 + _metile_register_index___________________________;\n int _off__metile_v44_r28 = v9 + _metile_register_index____________________________;\n int _off__metile_v44_r29 = v9 + _metile_register_index_____________________________;\n int _off__metile_v44_r30 = v9 + _metile_register_index______________________________;\n int _off__metile_v44_r31 = v9 + _metile_register_index_______________________________;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = _metile_v39_r8; }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = _metile_v39_r9; }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = _metile_v39_r10; }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = _metile_v39_r11; }\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = _metile_v39_r12; }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = _metile_v39_r13; }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = _metile_v39_r14; }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = _metile_v39_r15; }\n if (_metile_v43_r16) { Out[_off__metile_v44_r16] = _metile_v39_r16; }\n if (_metile_v43_r17) { Out[_off__metile_v44_r17] = _metile_v39_r17; }\n if (_metile_v43_r18) { Out[_off__metile_v44_r18] = _metile_v39_r18; }\n if (_metile_v43_r19) { Out[_off__metile_v44_r19] = _metile_v39_r19; }\n if (_metile_v43_r20) { Out[_off__metile_v44_r20] = _metile_v39_r20; }\n if (_metile_v43_r21) { Out[_off__metile_v44_r21] = _metile_v39_r21; }\n if (_metile_v43_r22) { Out[_off__metile_v44_r22] = _metile_v39_r22; }\n if (_metile_v43_r23) { Out[_off__metile_v44_r23] = _metile_v39_r23; }\n if (_metile_v43_r24) { Out[_off__metile_v44_r24] = _metile_v39_r24; }\n if (_metile_v43_r25) { Out[_off__metile_v44_r25] = _metile_v39_r25; }\n if (_metile_v43_r26) { Out[_off__metile_v44_r26] = _metile_v39_r26; }\n if (_metile_v43_r27) { Out[_off__metile_v44_r27] = _metile_v39_r27; }\n if (_metile_v43_r28) { Out[_off__metile_v44_r28] = _metile_v39_r28; }\n if (_metile_v43_r29) { Out[_off__metile_v44_r29] = _metile_v39_r29; }\n if (_metile_v43_r30) { Out[_off__metile_v44_r30] = _metile_v39_r30; }\n if (_metile_v43_r31) { Out[_off__metile_v44_r31] = _metile_v39_r31; }\n}", "source_sha256": "11365c357d8fbe48acbc6b54fb859a3d19b352b116d23e5955e6f3b1336584e2", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 32, 1, 1 ], "is_gemm": false, "prefer_ordered": false, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 32, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 32 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 32, "threads": 32, "scratch": null, "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 567, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 217.833, "control": 217.25, "speedup": 0.9973236378326517 }, "gpu_us": { "candidate": 8.500006515532732, "control": 8.375034667551517, "speedup": 0.9852974409192694 } } }, { "frozen_register4": { "pairs": 530, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 220.8955, "control": 221.3955, "speedup": 1.0022635137429237 }, "gpu_us": { "candidate": 8.500006515532732, "control": 8.416653145104647, "speedup": 0.9901937286429408 } } }, { "frozen_register4": { "pairs": 489, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 221.25, "control": 221.042, "speedup": 0.9990598870056497 }, "gpu_us": { "candidate": 8.62503657117486, "control": 8.583301678299904, "speedup": 0.9951611923577883 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9995469195551252, "round_speedups": [ 0.9973236378326517, 1.0022635137429237, 0.9990598870056497 ], "candidate": 219.98746754466333, "control": 219.88779552500134 }, "gpu_us": { "speedup": 0.9902092660618366, "round_speedups": [ 0.9852974409192694, 0.9901937286429408, 0.9951611923577883 ], "candidate": 8.541480508000936, "control": 8.457853144909093 } } } }, { "name": "float32_256x1009", "dtype": "float32", "batches": 256, "width": 1009, "status": "measured", "variant": { "name": "register32_blocked4", "elements_per_thread": 32, "layout": "blocked4" }, "input_sha256": "7bf6ce415ddd84786a2d450acbead1c0e25e5540b52b07d28c1e7796b91c7626", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 31;\n int _metile_register_index = int((((_metile_bounded_thread >> 5) & 1u) << 0) | (((_metile_bounded_thread >> 6) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 7) & 1u) << 7) | (((_metile_bounded_thread >> 8) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 32;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 5) & 1u) << 0) | (((_metile_register_packed_ >> 6) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 7) & 1u) << 7) | (((_metile_register_packed_ >> 8) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 64;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 5) & 1u) << 0) | (((_metile_register_packed__ >> 6) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 7) & 1u) << 7) | (((_metile_register_packed__ >> 8) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 96;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 5) & 1u) << 0) | (((_metile_register_packed___ >> 6) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 7) & 1u) << 7) | (((_metile_register_packed___ >> 8) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 128;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 5) & 1u) << 0) | (((_metile_register_packed____ >> 6) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 7) & 1u) << 7) | (((_metile_register_packed____ >> 8) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 160;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 5) & 1u) << 0) | (((_metile_register_packed_____ >> 6) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 7) & 1u) << 7) | (((_metile_register_packed_____ >> 8) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 192;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 5) & 1u) << 0) | (((_metile_register_packed______ >> 6) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 7) & 1u) << 7) | (((_metile_register_packed______ >> 8) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 224;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 5) & 1u) << 0) | (((_metile_register_packed_______ >> 6) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 7) & 1u) << 7) | (((_metile_register_packed_______ >> 8) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n int _metile_register_packed________ = _metile_bounded_thread + 256;\n int _metile_register_index________ = int((((_metile_register_packed________ >> 5) & 1u) << 0) | (((_metile_register_packed________ >> 6) & 1u) << 1) | (((_metile_register_packed________ >> 0) & 1u) << 2) | (((_metile_register_packed________ >> 1) & 1u) << 3) | (((_metile_register_packed________ >> 2) & 1u) << 4) | (((_metile_register_packed________ >> 3) & 1u) << 5) | (((_metile_register_packed________ >> 4) & 1u) << 6) | (((_metile_register_packed________ >> 7) & 1u) << 7) | (((_metile_register_packed________ >> 8) & 1u) << 8) | (((_metile_register_packed________ >> 9) & 1u) << 9));\n int _metile_register_packed_________ = _metile_bounded_thread + 288;\n int _metile_register_index_________ = int((((_metile_register_packed_________ >> 5) & 1u) << 0) | (((_metile_register_packed_________ >> 6) & 1u) << 1) | (((_metile_register_packed_________ >> 0) & 1u) << 2) | (((_metile_register_packed_________ >> 1) & 1u) << 3) | (((_metile_register_packed_________ >> 2) & 1u) << 4) | (((_metile_register_packed_________ >> 3) & 1u) << 5) | (((_metile_register_packed_________ >> 4) & 1u) << 6) | (((_metile_register_packed_________ >> 7) & 1u) << 7) | (((_metile_register_packed_________ >> 8) & 1u) << 8) | (((_metile_register_packed_________ >> 9) & 1u) << 9));\n int _metile_register_packed__________ = _metile_bounded_thread + 320;\n int _metile_register_index__________ = int((((_metile_register_packed__________ >> 5) & 1u) << 0) | (((_metile_register_packed__________ >> 6) & 1u) << 1) | (((_metile_register_packed__________ >> 0) & 1u) << 2) | (((_metile_register_packed__________ >> 1) & 1u) << 3) | (((_metile_register_packed__________ >> 2) & 1u) << 4) | (((_metile_register_packed__________ >> 3) & 1u) << 5) | (((_metile_register_packed__________ >> 4) & 1u) << 6) | (((_metile_register_packed__________ >> 7) & 1u) << 7) | (((_metile_register_packed__________ >> 8) & 1u) << 8) | (((_metile_register_packed__________ >> 9) & 1u) << 9));\n int _metile_register_packed___________ = _metile_bounded_thread + 352;\n int _metile_register_index___________ = int((((_metile_register_packed___________ >> 5) & 1u) << 0) | (((_metile_register_packed___________ >> 6) & 1u) << 1) | (((_metile_register_packed___________ >> 0) & 1u) << 2) | (((_metile_register_packed___________ >> 1) & 1u) << 3) | (((_metile_register_packed___________ >> 2) & 1u) << 4) | (((_metile_register_packed___________ >> 3) & 1u) << 5) | (((_metile_register_packed___________ >> 4) & 1u) << 6) | (((_metile_register_packed___________ >> 7) & 1u) << 7) | (((_metile_register_packed___________ >> 8) & 1u) << 8) | (((_metile_register_packed___________ >> 9) & 1u) << 9));\n int _metile_register_packed____________ = _metile_bounded_thread + 384;\n int _metile_register_index____________ = int((((_metile_register_packed____________ >> 5) & 1u) << 0) | (((_metile_register_packed____________ >> 6) & 1u) << 1) | (((_metile_register_packed____________ >> 0) & 1u) << 2) | (((_metile_register_packed____________ >> 1) & 1u) << 3) | (((_metile_register_packed____________ >> 2) & 1u) << 4) | (((_metile_register_packed____________ >> 3) & 1u) << 5) | (((_metile_register_packed____________ >> 4) & 1u) << 6) | (((_metile_register_packed____________ >> 7) & 1u) << 7) | (((_metile_register_packed____________ >> 8) & 1u) << 8) | (((_metile_register_packed____________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________ = _metile_bounded_thread + 416;\n int _metile_register_index_____________ = int((((_metile_register_packed_____________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________ >> 9) & 1u) << 9));\n int _metile_register_packed______________ = _metile_bounded_thread + 448;\n int _metile_register_index______________ = int((((_metile_register_packed______________ >> 5) & 1u) << 0) | (((_metile_register_packed______________ >> 6) & 1u) << 1) | (((_metile_register_packed______________ >> 0) & 1u) << 2) | (((_metile_register_packed______________ >> 1) & 1u) << 3) | (((_metile_register_packed______________ >> 2) & 1u) << 4) | (((_metile_register_packed______________ >> 3) & 1u) << 5) | (((_metile_register_packed______________ >> 4) & 1u) << 6) | (((_metile_register_packed______________ >> 7) & 1u) << 7) | (((_metile_register_packed______________ >> 8) & 1u) << 8) | (((_metile_register_packed______________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________ = _metile_bounded_thread + 480;\n int _metile_register_index_______________ = int((((_metile_register_packed_______________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________ >> 9) & 1u) << 9));\n int _metile_register_packed________________ = _metile_bounded_thread + 512;\n int _metile_register_index________________ = int((((_metile_register_packed________________ >> 5) & 1u) << 0) | (((_metile_register_packed________________ >> 6) & 1u) << 1) | (((_metile_register_packed________________ >> 0) & 1u) << 2) | (((_metile_register_packed________________ >> 1) & 1u) << 3) | (((_metile_register_packed________________ >> 2) & 1u) << 4) | (((_metile_register_packed________________ >> 3) & 1u) << 5) | (((_metile_register_packed________________ >> 4) & 1u) << 6) | (((_metile_register_packed________________ >> 7) & 1u) << 7) | (((_metile_register_packed________________ >> 8) & 1u) << 8) | (((_metile_register_packed________________ >> 9) & 1u) << 9));\n int _metile_register_packed_________________ = _metile_bounded_thread + 544;\n int _metile_register_index_________________ = int((((_metile_register_packed_________________ >> 5) & 1u) << 0) | (((_metile_register_packed_________________ >> 6) & 1u) << 1) | (((_metile_register_packed_________________ >> 0) & 1u) << 2) | (((_metile_register_packed_________________ >> 1) & 1u) << 3) | (((_metile_register_packed_________________ >> 2) & 1u) << 4) | (((_metile_register_packed_________________ >> 3) & 1u) << 5) | (((_metile_register_packed_________________ >> 4) & 1u) << 6) | (((_metile_register_packed_________________ >> 7) & 1u) << 7) | (((_metile_register_packed_________________ >> 8) & 1u) << 8) | (((_metile_register_packed_________________ >> 9) & 1u) << 9));\n int _metile_register_packed__________________ = _metile_bounded_thread + 576;\n int _metile_register_index__________________ = int((((_metile_register_packed__________________ >> 5) & 1u) << 0) | (((_metile_register_packed__________________ >> 6) & 1u) << 1) | (((_metile_register_packed__________________ >> 0) & 1u) << 2) | (((_metile_register_packed__________________ >> 1) & 1u) << 3) | (((_metile_register_packed__________________ >> 2) & 1u) << 4) | (((_metile_register_packed__________________ >> 3) & 1u) << 5) | (((_metile_register_packed__________________ >> 4) & 1u) << 6) | (((_metile_register_packed__________________ >> 7) & 1u) << 7) | (((_metile_register_packed__________________ >> 8) & 1u) << 8) | (((_metile_register_packed__________________ >> 9) & 1u) << 9));\n int _metile_register_packed___________________ = _metile_bounded_thread + 608;\n int _metile_register_index___________________ = int((((_metile_register_packed___________________ >> 5) & 1u) << 0) | (((_metile_register_packed___________________ >> 6) & 1u) << 1) | (((_metile_register_packed___________________ >> 0) & 1u) << 2) | (((_metile_register_packed___________________ >> 1) & 1u) << 3) | (((_metile_register_packed___________________ >> 2) & 1u) << 4) | (((_metile_register_packed___________________ >> 3) & 1u) << 5) | (((_metile_register_packed___________________ >> 4) & 1u) << 6) | (((_metile_register_packed___________________ >> 7) & 1u) << 7) | (((_metile_register_packed___________________ >> 8) & 1u) << 8) | (((_metile_register_packed___________________ >> 9) & 1u) << 9));\n int _metile_register_packed____________________ = _metile_bounded_thread + 640;\n int _metile_register_index____________________ = int((((_metile_register_packed____________________ >> 5) & 1u) << 0) | (((_metile_register_packed____________________ >> 6) & 1u) << 1) | (((_metile_register_packed____________________ >> 0) & 1u) << 2) | (((_metile_register_packed____________________ >> 1) & 1u) << 3) | (((_metile_register_packed____________________ >> 2) & 1u) << 4) | (((_metile_register_packed____________________ >> 3) & 1u) << 5) | (((_metile_register_packed____________________ >> 4) & 1u) << 6) | (((_metile_register_packed____________________ >> 7) & 1u) << 7) | (((_metile_register_packed____________________ >> 8) & 1u) << 8) | (((_metile_register_packed____________________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________________ = _metile_bounded_thread + 672;\n int _metile_register_index_____________________ = int((((_metile_register_packed_____________________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________________ >> 9) & 1u) << 9));\n int _metile_register_packed______________________ = _metile_bounded_thread + 704;\n int _metile_register_index______________________ = int((((_metile_register_packed______________________ >> 5) & 1u) << 0) | (((_metile_register_packed______________________ >> 6) & 1u) << 1) | (((_metile_register_packed______________________ >> 0) & 1u) << 2) | (((_metile_register_packed______________________ >> 1) & 1u) << 3) | (((_metile_register_packed______________________ >> 2) & 1u) << 4) | (((_metile_register_packed______________________ >> 3) & 1u) << 5) | (((_metile_register_packed______________________ >> 4) & 1u) << 6) | (((_metile_register_packed______________________ >> 7) & 1u) << 7) | (((_metile_register_packed______________________ >> 8) & 1u) << 8) | (((_metile_register_packed______________________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________________ = _metile_bounded_thread + 736;\n int _metile_register_index_______________________ = int((((_metile_register_packed_______________________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________________ >> 9) & 1u) << 9));\n int _metile_register_packed________________________ = _metile_bounded_thread + 768;\n int _metile_register_index________________________ = int((((_metile_register_packed________________________ >> 5) & 1u) << 0) | (((_metile_register_packed________________________ >> 6) & 1u) << 1) | (((_metile_register_packed________________________ >> 0) & 1u) << 2) | (((_metile_register_packed________________________ >> 1) & 1u) << 3) | (((_metile_register_packed________________________ >> 2) & 1u) << 4) | (((_metile_register_packed________________________ >> 3) & 1u) << 5) | (((_metile_register_packed________________________ >> 4) & 1u) << 6) | (((_metile_register_packed________________________ >> 7) & 1u) << 7) | (((_metile_register_packed________________________ >> 8) & 1u) << 8) | (((_metile_register_packed________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_________________________ = _metile_bounded_thread + 800;\n int _metile_register_index_________________________ = int((((_metile_register_packed_________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_________________________ >> 9) & 1u) << 9));\n int _metile_register_packed__________________________ = _metile_bounded_thread + 832;\n int _metile_register_index__________________________ = int((((_metile_register_packed__________________________ >> 5) & 1u) << 0) | (((_metile_register_packed__________________________ >> 6) & 1u) << 1) | (((_metile_register_packed__________________________ >> 0) & 1u) << 2) | (((_metile_register_packed__________________________ >> 1) & 1u) << 3) | (((_metile_register_packed__________________________ >> 2) & 1u) << 4) | (((_metile_register_packed__________________________ >> 3) & 1u) << 5) | (((_metile_register_packed__________________________ >> 4) & 1u) << 6) | (((_metile_register_packed__________________________ >> 7) & 1u) << 7) | (((_metile_register_packed__________________________ >> 8) & 1u) << 8) | (((_metile_register_packed__________________________ >> 9) & 1u) << 9));\n int _metile_register_packed___________________________ = _metile_bounded_thread + 864;\n int _metile_register_index___________________________ = int((((_metile_register_packed___________________________ >> 5) & 1u) << 0) | (((_metile_register_packed___________________________ >> 6) & 1u) << 1) | (((_metile_register_packed___________________________ >> 0) & 1u) << 2) | (((_metile_register_packed___________________________ >> 1) & 1u) << 3) | (((_metile_register_packed___________________________ >> 2) & 1u) << 4) | (((_metile_register_packed___________________________ >> 3) & 1u) << 5) | (((_metile_register_packed___________________________ >> 4) & 1u) << 6) | (((_metile_register_packed___________________________ >> 7) & 1u) << 7) | (((_metile_register_packed___________________________ >> 8) & 1u) << 8) | (((_metile_register_packed___________________________ >> 9) & 1u) << 9));\n int _metile_register_packed____________________________ = _metile_bounded_thread + 896;\n int _metile_register_index____________________________ = int((((_metile_register_packed____________________________ >> 5) & 1u) << 0) | (((_metile_register_packed____________________________ >> 6) & 1u) << 1) | (((_metile_register_packed____________________________ >> 0) & 1u) << 2) | (((_metile_register_packed____________________________ >> 1) & 1u) << 3) | (((_metile_register_packed____________________________ >> 2) & 1u) << 4) | (((_metile_register_packed____________________________ >> 3) & 1u) << 5) | (((_metile_register_packed____________________________ >> 4) & 1u) << 6) | (((_metile_register_packed____________________________ >> 7) & 1u) << 7) | (((_metile_register_packed____________________________ >> 8) & 1u) << 8) | (((_metile_register_packed____________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________________________ = _metile_bounded_thread + 928;\n int _metile_register_index_____________________________ = int((((_metile_register_packed_____________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________________________ >> 9) & 1u) << 9));\n int _metile_register_packed______________________________ = _metile_bounded_thread + 960;\n int _metile_register_index______________________________ = int((((_metile_register_packed______________________________ >> 5) & 1u) << 0) | (((_metile_register_packed______________________________ >> 6) & 1u) << 1) | (((_metile_register_packed______________________________ >> 0) & 1u) << 2) | (((_metile_register_packed______________________________ >> 1) & 1u) << 3) | (((_metile_register_packed______________________________ >> 2) & 1u) << 4) | (((_metile_register_packed______________________________ >> 3) & 1u) << 5) | (((_metile_register_packed______________________________ >> 4) & 1u) << 6) | (((_metile_register_packed______________________________ >> 7) & 1u) << 7) | (((_metile_register_packed______________________________ >> 8) & 1u) << 8) | (((_metile_register_packed______________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________________________ = _metile_bounded_thread + 992;\n int _metile_register_index_______________________________ = int((((_metile_register_packed_______________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________________________ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v16_r16 = _metile_register_index________________ >= 0;\n bool _metile_v16_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v16_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v16_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v16_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v16_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v16_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v16_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v16_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v16_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v16_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v16_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v16_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v16_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v16_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v16_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v17_r4 = _metile_register_index____ < 1009;\n bool _metile_v17_r5 = _metile_register_index_____ < 1009;\n bool _metile_v17_r6 = _metile_register_index______ < 1009;\n bool _metile_v17_r7 = _metile_register_index_______ < 1009;\n bool _metile_v17_r8 = _metile_register_index________ < 1009;\n bool _metile_v17_r9 = _metile_register_index_________ < 1009;\n bool _metile_v17_r10 = _metile_register_index__________ < 1009;\n bool _metile_v17_r11 = _metile_register_index___________ < 1009;\n bool _metile_v17_r12 = _metile_register_index____________ < 1009;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v17_r14 = _metile_register_index______________ < 1009;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v17_r16 = _metile_register_index________________ < 1009;\n bool _metile_v17_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v17_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v17_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v17_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v17_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v17_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v17_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v17_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v17_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v17_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v17_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v17_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v17_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v17_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v17_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n bool _metile_v18_r16 = _metile_v16_r16 & _metile_v17_r16;\n bool _metile_v18_r17 = _metile_v16_r17 & _metile_v17_r17;\n bool _metile_v18_r18 = _metile_v16_r18 & _metile_v17_r18;\n bool _metile_v18_r19 = _metile_v16_r19 & _metile_v17_r19;\n bool _metile_v18_r20 = _metile_v16_r20 & _metile_v17_r20;\n bool _metile_v18_r21 = _metile_v16_r21 & _metile_v17_r21;\n bool _metile_v18_r22 = _metile_v16_r22 & _metile_v17_r22;\n bool _metile_v18_r23 = _metile_v16_r23 & _metile_v17_r23;\n bool _metile_v18_r24 = _metile_v16_r24 & _metile_v17_r24;\n bool _metile_v18_r25 = _metile_v16_r25 & _metile_v17_r25;\n bool _metile_v18_r26 = _metile_v16_r26 & _metile_v17_r26;\n bool _metile_v18_r27 = _metile_v16_r27 & _metile_v17_r27;\n bool _metile_v18_r28 = _metile_v16_r28 & _metile_v17_r28;\n bool _metile_v18_r29 = _metile_v16_r29 & _metile_v17_r29;\n bool _metile_v18_r30 = _metile_v16_r30 & _metile_v17_r30;\n bool _metile_v18_r31 = _metile_v16_r31 & _metile_v17_r31;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n int _off__metile_v19_r16 = v2 + _metile_register_index________________;\n int _off__metile_v19_r17 = v2 + _metile_register_index_________________;\n int _off__metile_v19_r18 = v2 + _metile_register_index__________________;\n int _off__metile_v19_r19 = v2 + _metile_register_index___________________;\n int _off__metile_v19_r20 = v2 + _metile_register_index____________________;\n int _off__metile_v19_r21 = v2 + _metile_register_index_____________________;\n int _off__metile_v19_r22 = v2 + _metile_register_index______________________;\n int _off__metile_v19_r23 = v2 + _metile_register_index_______________________;\n int _off__metile_v19_r24 = v2 + _metile_register_index________________________;\n int _off__metile_v19_r25 = v2 + _metile_register_index_________________________;\n int _off__metile_v19_r26 = v2 + _metile_register_index__________________________;\n int _off__metile_v19_r27 = v2 + _metile_register_index___________________________;\n int _off__metile_v19_r28 = v2 + _metile_register_index____________________________;\n int _off__metile_v19_r29 = v2 + _metile_register_index_____________________________;\n int _off__metile_v19_r30 = v2 + _metile_register_index______________________________;\n int _off__metile_v19_r31 = v2 + _metile_register_index_______________________________;\n float4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = float4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n float _metile_v20_r0 = _metile_vector_load[0];\n float _metile_v20_r1 = _metile_vector_load[1];\n float _metile_v20_r2 = _metile_vector_load[2];\n float _metile_v20_r3 = _metile_vector_load[3];\n float4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = float4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n float _metile_v20_r4 = _metile_vector_load_[0];\n float _metile_v20_r5 = _metile_vector_load_[1];\n float _metile_v20_r6 = _metile_vector_load_[2];\n float _metile_v20_r7 = _metile_vector_load_[3];\n float4 _metile_vector_load__;\n if ((_metile_v18_r8) && (_metile_v18_r9) && (_metile_v18_r10) && (_metile_v18_r11) && (long(_off__metile_v19_r9) == long(_off__metile_v19_r8) + 1) && (long(_off__metile_v19_r10) == long(_off__metile_v19_r8) + 2) && (long(_off__metile_v19_r11) == long(_off__metile_v19_r8) + 3)) {\n _metile_vector_load__ = float4(*reinterpret_cast(X + _off__metile_v19_r8));\n } else {\n _metile_vector_load__[0] = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n _metile_vector_load__[1] = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n _metile_vector_load__[2] = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n _metile_vector_load__[3] = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n }\n float _metile_v20_r8 = _metile_vector_load__[0];\n float _metile_v20_r9 = _metile_vector_load__[1];\n float _metile_v20_r10 = _metile_vector_load__[2];\n float _metile_v20_r11 = _metile_vector_load__[3];\n float4 _metile_vector_load___;\n if ((_metile_v18_r12) && (_metile_v18_r13) && (_metile_v18_r14) && (_metile_v18_r15) && (long(_off__metile_v19_r13) == long(_off__metile_v19_r12) + 1) && (long(_off__metile_v19_r14) == long(_off__metile_v19_r12) + 2) && (long(_off__metile_v19_r15) == long(_off__metile_v19_r12) + 3)) {\n _metile_vector_load___ = float4(*reinterpret_cast(X + _off__metile_v19_r12));\n } else {\n _metile_vector_load___[0] = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n _metile_vector_load___[1] = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n _metile_vector_load___[2] = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n _metile_vector_load___[3] = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n }\n float _metile_v20_r12 = _metile_vector_load___[0];\n float _metile_v20_r13 = _metile_vector_load___[1];\n float _metile_v20_r14 = _metile_vector_load___[2];\n float _metile_v20_r15 = _metile_vector_load___[3];\n float4 _metile_vector_load____;\n if ((_metile_v18_r16) && (_metile_v18_r17) && (_metile_v18_r18) && (_metile_v18_r19) && (long(_off__metile_v19_r17) == long(_off__metile_v19_r16) + 1) && (long(_off__metile_v19_r18) == long(_off__metile_v19_r16) + 2) && (long(_off__metile_v19_r19) == long(_off__metile_v19_r16) + 3)) {\n _metile_vector_load____ = float4(*reinterpret_cast(X + _off__metile_v19_r16));\n } else {\n _metile_vector_load____[0] = _metile_v18_r16 ? X[_off__metile_v19_r16] : static_cast(0);\n _metile_vector_load____[1] = _metile_v18_r17 ? X[_off__metile_v19_r17] : static_cast(0);\n _metile_vector_load____[2] = _metile_v18_r18 ? X[_off__metile_v19_r18] : static_cast(0);\n _metile_vector_load____[3] = _metile_v18_r19 ? X[_off__metile_v19_r19] : static_cast(0);\n }\n float _metile_v20_r16 = _metile_vector_load____[0];\n float _metile_v20_r17 = _metile_vector_load____[1];\n float _metile_v20_r18 = _metile_vector_load____[2];\n float _metile_v20_r19 = _metile_vector_load____[3];\n float4 _metile_vector_load_____;\n if ((_metile_v18_r20) && (_metile_v18_r21) && (_metile_v18_r22) && (_metile_v18_r23) && (long(_off__metile_v19_r21) == long(_off__metile_v19_r20) + 1) && (long(_off__metile_v19_r22) == long(_off__metile_v19_r20) + 2) && (long(_off__metile_v19_r23) == long(_off__metile_v19_r20) + 3)) {\n _metile_vector_load_____ = float4(*reinterpret_cast(X + _off__metile_v19_r20));\n } else {\n _metile_vector_load_____[0] = _metile_v18_r20 ? X[_off__metile_v19_r20] : static_cast(0);\n _metile_vector_load_____[1] = _metile_v18_r21 ? X[_off__metile_v19_r21] : static_cast(0);\n _metile_vector_load_____[2] = _metile_v18_r22 ? X[_off__metile_v19_r22] : static_cast(0);\n _metile_vector_load_____[3] = _metile_v18_r23 ? X[_off__metile_v19_r23] : static_cast(0);\n }\n float _metile_v20_r20 = _metile_vector_load_____[0];\n float _metile_v20_r21 = _metile_vector_load_____[1];\n float _metile_v20_r22 = _metile_vector_load_____[2];\n float _metile_v20_r23 = _metile_vector_load_____[3];\n float4 _metile_vector_load______;\n if ((_metile_v18_r24) && (_metile_v18_r25) && (_metile_v18_r26) && (_metile_v18_r27) && (long(_off__metile_v19_r25) == long(_off__metile_v19_r24) + 1) && (long(_off__metile_v19_r26) == long(_off__metile_v19_r24) + 2) && (long(_off__metile_v19_r27) == long(_off__metile_v19_r24) + 3)) {\n _metile_vector_load______ = float4(*reinterpret_cast(X + _off__metile_v19_r24));\n } else {\n _metile_vector_load______[0] = _metile_v18_r24 ? X[_off__metile_v19_r24] : static_cast(0);\n _metile_vector_load______[1] = _metile_v18_r25 ? X[_off__metile_v19_r25] : static_cast(0);\n _metile_vector_load______[2] = _metile_v18_r26 ? X[_off__metile_v19_r26] : static_cast(0);\n _metile_vector_load______[3] = _metile_v18_r27 ? X[_off__metile_v19_r27] : static_cast(0);\n }\n float _metile_v20_r24 = _metile_vector_load______[0];\n float _metile_v20_r25 = _metile_vector_load______[1];\n float _metile_v20_r26 = _metile_vector_load______[2];\n float _metile_v20_r27 = _metile_vector_load______[3];\n float4 _metile_vector_load_______;\n if ((_metile_v18_r28) && (_metile_v18_r29) && (_metile_v18_r30) && (_metile_v18_r31) && (long(_off__metile_v19_r29) == long(_off__metile_v19_r28) + 1) && (long(_off__metile_v19_r30) == long(_off__metile_v19_r28) + 2) && (long(_off__metile_v19_r31) == long(_off__metile_v19_r28) + 3)) {\n _metile_vector_load_______ = float4(*reinterpret_cast(X + _off__metile_v19_r28));\n } else {\n _metile_vector_load_______[0] = _metile_v18_r28 ? X[_off__metile_v19_r28] : static_cast(0);\n _metile_vector_load_______[1] = _metile_v18_r29 ? X[_off__metile_v19_r29] : static_cast(0);\n _metile_vector_load_______[2] = _metile_v18_r30 ? X[_off__metile_v19_r30] : static_cast(0);\n _metile_vector_load_______[3] = _metile_v18_r31 ? X[_off__metile_v19_r31] : static_cast(0);\n }\n float _metile_v20_r28 = _metile_vector_load_______[0];\n float _metile_v20_r29 = _metile_vector_load_______[1];\n float _metile_v20_r30 = _metile_vector_load_______[2];\n float _metile_v20_r31 = _metile_vector_load_______[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v21_r16 = static_cast(_metile_v20_r16);\n float _metile_v21_r17 = static_cast(_metile_v20_r17);\n float _metile_v21_r18 = static_cast(_metile_v20_r18);\n float _metile_v21_r19 = static_cast(_metile_v20_r19);\n float _metile_v21_r20 = static_cast(_metile_v20_r20);\n float _metile_v21_r21 = static_cast(_metile_v20_r21);\n float _metile_v21_r22 = static_cast(_metile_v20_r22);\n float _metile_v21_r23 = static_cast(_metile_v20_r23);\n float _metile_v21_r24 = static_cast(_metile_v20_r24);\n float _metile_v21_r25 = static_cast(_metile_v20_r25);\n float _metile_v21_r26 = static_cast(_metile_v20_r26);\n float _metile_v21_r27 = static_cast(_metile_v20_r27);\n float _metile_v21_r28 = static_cast(_metile_v20_r28);\n float _metile_v21_r29 = static_cast(_metile_v20_r29);\n float _metile_v21_r30 = static_cast(_metile_v20_r30);\n float _metile_v21_r31 = static_cast(_metile_v20_r31);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_v22_r16 = _metile_v21_r16 * _metile_v21_r16;\n float _metile_v22_r17 = _metile_v21_r17 * _metile_v21_r17;\n float _metile_v22_r18 = _metile_v21_r18 * _metile_v21_r18;\n float _metile_v22_r19 = _metile_v21_r19 * _metile_v21_r19;\n float _metile_v22_r20 = _metile_v21_r20 * _metile_v21_r20;\n float _metile_v22_r21 = _metile_v21_r21 * _metile_v21_r21;\n float _metile_v22_r22 = _metile_v21_r22 * _metile_v21_r22;\n float _metile_v22_r23 = _metile_v21_r23 * _metile_v21_r23;\n float _metile_v22_r24 = _metile_v21_r24 * _metile_v21_r24;\n float _metile_v22_r25 = _metile_v21_r25 * _metile_v21_r25;\n float _metile_v22_r26 = _metile_v21_r26 * _metile_v21_r26;\n float _metile_v22_r27 = _metile_v21_r27 * _metile_v21_r27;\n float _metile_v22_r28 = _metile_v21_r28 * _metile_v21_r28;\n float _metile_v22_r29 = _metile_v21_r29 * _metile_v21_r29;\n float _metile_v22_r30 = _metile_v21_r30 * _metile_v21_r30;\n float _metile_v22_r31 = _metile_v21_r31 * _metile_v21_r31;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_v22_r16 + _metile_v22_r17;\n float _metile_register_sum_________ = _metile_v22_r18 + _metile_v22_r19;\n float _metile_register_sum__________ = _metile_v22_r20 + _metile_v22_r21;\n float _metile_register_sum___________ = _metile_v22_r22 + _metile_v22_r23;\n float _metile_register_sum____________ = _metile_v22_r24 + _metile_v22_r25;\n float _metile_register_sum_____________ = _metile_v22_r26 + _metile_v22_r27;\n float _metile_register_sum______________ = _metile_v22_r28 + _metile_v22_r29;\n float _metile_register_sum_______________ = _metile_v22_r30 + _metile_v22_r31;\n float _metile_register_sum________________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________________ = _metile_register_sum____________ + _metile_register_sum_____________;\n float _metile_register_sum_______________________ = _metile_register_sum______________ + _metile_register_sum_______________;\n float _metile_register_sum________________________ = _metile_register_sum________________ + _metile_register_sum_________________;\n float _metile_register_sum_________________________ = _metile_register_sum__________________ + _metile_register_sum___________________;\n float _metile_register_sum__________________________ = _metile_register_sum____________________ + _metile_register_sum_____________________;\n float _metile_register_sum___________________________ = _metile_register_sum______________________ + _metile_register_sum_______________________;\n float _metile_register_sum____________________________ = _metile_register_sum________________________ + _metile_register_sum_________________________;\n float _metile_register_sum_____________________________ = _metile_register_sum__________________________ + _metile_register_sum___________________________;\n float _metile_register_sum______________________________ = _metile_register_sum____________________________ + _metile_register_sum_____________________________;\n float v23 = simd_sum(_metile_register_sum______________________________);\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v32_r16 = _metile_register_index________________ >= 0;\n bool _metile_v32_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v32_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v32_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v32_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v32_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v32_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v32_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v32_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v32_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v32_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v32_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v32_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v32_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v32_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v32_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v33_r4 = _metile_register_index____ < 1009;\n bool _metile_v33_r5 = _metile_register_index_____ < 1009;\n bool _metile_v33_r6 = _metile_register_index______ < 1009;\n bool _metile_v33_r7 = _metile_register_index_______ < 1009;\n bool _metile_v33_r8 = _metile_register_index________ < 1009;\n bool _metile_v33_r9 = _metile_register_index_________ < 1009;\n bool _metile_v33_r10 = _metile_register_index__________ < 1009;\n bool _metile_v33_r11 = _metile_register_index___________ < 1009;\n bool _metile_v33_r12 = _metile_register_index____________ < 1009;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v33_r14 = _metile_register_index______________ < 1009;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v33_r16 = _metile_register_index________________ < 1009;\n bool _metile_v33_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v33_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v33_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v33_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v33_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v33_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v33_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v33_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v33_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v33_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v33_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v33_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v33_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v33_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v33_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n bool _metile_v34_r16 = _metile_v32_r16 & _metile_v33_r16;\n bool _metile_v34_r17 = _metile_v32_r17 & _metile_v33_r17;\n bool _metile_v34_r18 = _metile_v32_r18 & _metile_v33_r18;\n bool _metile_v34_r19 = _metile_v32_r19 & _metile_v33_r19;\n bool _metile_v34_r20 = _metile_v32_r20 & _metile_v33_r20;\n bool _metile_v34_r21 = _metile_v32_r21 & _metile_v33_r21;\n bool _metile_v34_r22 = _metile_v32_r22 & _metile_v33_r22;\n bool _metile_v34_r23 = _metile_v32_r23 & _metile_v33_r23;\n bool _metile_v34_r24 = _metile_v32_r24 & _metile_v33_r24;\n bool _metile_v34_r25 = _metile_v32_r25 & _metile_v33_r25;\n bool _metile_v34_r26 = _metile_v32_r26 & _metile_v33_r26;\n bool _metile_v34_r27 = _metile_v32_r27 & _metile_v33_r27;\n bool _metile_v34_r28 = _metile_v32_r28 & _metile_v33_r28;\n bool _metile_v34_r29 = _metile_v32_r29 & _metile_v33_r29;\n bool _metile_v34_r30 = _metile_v32_r30 & _metile_v33_r30;\n bool _metile_v34_r31 = _metile_v32_r31 & _metile_v33_r31;\n float4 _metile_vector_load________;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load________ = float4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load________[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load________[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load________[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load________[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n float _metile_v36_r0 = _metile_vector_load________[0];\n float _metile_v36_r1 = _metile_vector_load________[1];\n float _metile_v36_r2 = _metile_vector_load________[2];\n float _metile_v36_r3 = _metile_vector_load________[3];\n float4 _metile_vector_load_________;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load_________ = float4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load_________[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load_________[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load_________[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load_________[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n float _metile_v36_r4 = _metile_vector_load_________[0];\n float _metile_v36_r5 = _metile_vector_load_________[1];\n float _metile_v36_r6 = _metile_vector_load_________[2];\n float _metile_v36_r7 = _metile_vector_load_________[3];\n float4 _metile_vector_load__________;\n if ((_metile_v34_r8) && (_metile_v34_r9) && (_metile_v34_r10) && (_metile_v34_r11) && (long(_metile_register_index_________) == long(_metile_register_index________) + 1) && (long(_metile_register_index__________) == long(_metile_register_index________) + 2) && (long(_metile_register_index___________) == long(_metile_register_index________) + 3)) {\n _metile_vector_load__________ = float4(*reinterpret_cast(W + _metile_register_index________));\n } else {\n _metile_vector_load__________[0] = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n _metile_vector_load__________[1] = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n _metile_vector_load__________[2] = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n _metile_vector_load__________[3] = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n }\n float _metile_v36_r8 = _metile_vector_load__________[0];\n float _metile_v36_r9 = _metile_vector_load__________[1];\n float _metile_v36_r10 = _metile_vector_load__________[2];\n float _metile_v36_r11 = _metile_vector_load__________[3];\n float4 _metile_vector_load___________;\n if ((_metile_v34_r12) && (_metile_v34_r13) && (_metile_v34_r14) && (_metile_v34_r15) && (long(_metile_register_index_____________) == long(_metile_register_index____________) + 1) && (long(_metile_register_index______________) == long(_metile_register_index____________) + 2) && (long(_metile_register_index_______________) == long(_metile_register_index____________) + 3)) {\n _metile_vector_load___________ = float4(*reinterpret_cast(W + _metile_register_index____________));\n } else {\n _metile_vector_load___________[0] = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n _metile_vector_load___________[1] = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n _metile_vector_load___________[2] = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n _metile_vector_load___________[3] = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n }\n float _metile_v36_r12 = _metile_vector_load___________[0];\n float _metile_v36_r13 = _metile_vector_load___________[1];\n float _metile_v36_r14 = _metile_vector_load___________[2];\n float _metile_v36_r15 = _metile_vector_load___________[3];\n float4 _metile_vector_load____________;\n if ((_metile_v34_r16) && (_metile_v34_r17) && (_metile_v34_r18) && (_metile_v34_r19) && (long(_metile_register_index_________________) == long(_metile_register_index________________) + 1) && (long(_metile_register_index__________________) == long(_metile_register_index________________) + 2) && (long(_metile_register_index___________________) == long(_metile_register_index________________) + 3)) {\n _metile_vector_load____________ = float4(*reinterpret_cast(W + _metile_register_index________________));\n } else {\n _metile_vector_load____________[0] = _metile_v34_r16 ? W[_metile_register_index________________] : static_cast(0);\n _metile_vector_load____________[1] = _metile_v34_r17 ? W[_metile_register_index_________________] : static_cast(0);\n _metile_vector_load____________[2] = _metile_v34_r18 ? W[_metile_register_index__________________] : static_cast(0);\n _metile_vector_load____________[3] = _metile_v34_r19 ? W[_metile_register_index___________________] : static_cast(0);\n }\n float _metile_v36_r16 = _metile_vector_load____________[0];\n float _metile_v36_r17 = _metile_vector_load____________[1];\n float _metile_v36_r18 = _metile_vector_load____________[2];\n float _metile_v36_r19 = _metile_vector_load____________[3];\n float4 _metile_vector_load_____________;\n if ((_metile_v34_r20) && (_metile_v34_r21) && (_metile_v34_r22) && (_metile_v34_r23) && (long(_metile_register_index_____________________) == long(_metile_register_index____________________) + 1) && (long(_metile_register_index______________________) == long(_metile_register_index____________________) + 2) && (long(_metile_register_index_______________________) == long(_metile_register_index____________________) + 3)) {\n _metile_vector_load_____________ = float4(*reinterpret_cast(W + _metile_register_index____________________));\n } else {\n _metile_vector_load_____________[0] = _metile_v34_r20 ? W[_metile_register_index____________________] : static_cast(0);\n _metile_vector_load_____________[1] = _metile_v34_r21 ? W[_metile_register_index_____________________] : static_cast(0);\n _metile_vector_load_____________[2] = _metile_v34_r22 ? W[_metile_register_index______________________] : static_cast(0);\n _metile_vector_load_____________[3] = _metile_v34_r23 ? W[_metile_register_index_______________________] : static_cast(0);\n }\n float _metile_v36_r20 = _metile_vector_load_____________[0];\n float _metile_v36_r21 = _metile_vector_load_____________[1];\n float _metile_v36_r22 = _metile_vector_load_____________[2];\n float _metile_v36_r23 = _metile_vector_load_____________[3];\n float4 _metile_vector_load______________;\n if ((_metile_v34_r24) && (_metile_v34_r25) && (_metile_v34_r26) && (_metile_v34_r27) && (long(_metile_register_index_________________________) == long(_metile_register_index________________________) + 1) && (long(_metile_register_index__________________________) == long(_metile_register_index________________________) + 2) && (long(_metile_register_index___________________________) == long(_metile_register_index________________________) + 3)) {\n _metile_vector_load______________ = float4(*reinterpret_cast(W + _metile_register_index________________________));\n } else {\n _metile_vector_load______________[0] = _metile_v34_r24 ? W[_metile_register_index________________________] : static_cast(0);\n _metile_vector_load______________[1] = _metile_v34_r25 ? W[_metile_register_index_________________________] : static_cast(0);\n _metile_vector_load______________[2] = _metile_v34_r26 ? W[_metile_register_index__________________________] : static_cast(0);\n _metile_vector_load______________[3] = _metile_v34_r27 ? W[_metile_register_index___________________________] : static_cast(0);\n }\n float _metile_v36_r24 = _metile_vector_load______________[0];\n float _metile_v36_r25 = _metile_vector_load______________[1];\n float _metile_v36_r26 = _metile_vector_load______________[2];\n float _metile_v36_r27 = _metile_vector_load______________[3];\n float4 _metile_vector_load_______________;\n if ((_metile_v34_r28) && (_metile_v34_r29) && (_metile_v34_r30) && (_metile_v34_r31) && (long(_metile_register_index_____________________________) == long(_metile_register_index____________________________) + 1) && (long(_metile_register_index______________________________) == long(_metile_register_index____________________________) + 2) && (long(_metile_register_index_______________________________) == long(_metile_register_index____________________________) + 3)) {\n _metile_vector_load_______________ = float4(*reinterpret_cast(W + _metile_register_index____________________________));\n } else {\n _metile_vector_load_______________[0] = _metile_v34_r28 ? W[_metile_register_index____________________________] : static_cast(0);\n _metile_vector_load_______________[1] = _metile_v34_r29 ? W[_metile_register_index_____________________________] : static_cast(0);\n _metile_vector_load_______________[2] = _metile_v34_r30 ? W[_metile_register_index______________________________] : static_cast(0);\n _metile_vector_load_______________[3] = _metile_v34_r31 ? W[_metile_register_index_______________________________] : static_cast(0);\n }\n float _metile_v36_r28 = _metile_vector_load_______________[0];\n float _metile_v36_r29 = _metile_vector_load_______________[1];\n float _metile_v36_r30 = _metile_vector_load_______________[2];\n float _metile_v36_r31 = _metile_vector_load_______________[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v37_r16 = static_cast(_metile_v36_r16);\n float _metile_v37_r17 = static_cast(_metile_v36_r17);\n float _metile_v37_r18 = static_cast(_metile_v36_r18);\n float _metile_v37_r19 = static_cast(_metile_v36_r19);\n float _metile_v37_r20 = static_cast(_metile_v36_r20);\n float _metile_v37_r21 = static_cast(_metile_v36_r21);\n float _metile_v37_r22 = static_cast(_metile_v36_r22);\n float _metile_v37_r23 = static_cast(_metile_v36_r23);\n float _metile_v37_r24 = static_cast(_metile_v36_r24);\n float _metile_v37_r25 = static_cast(_metile_v36_r25);\n float _metile_v37_r26 = static_cast(_metile_v36_r26);\n float _metile_v37_r27 = static_cast(_metile_v36_r27);\n float _metile_v37_r28 = static_cast(_metile_v36_r28);\n float _metile_v37_r29 = static_cast(_metile_v36_r29);\n float _metile_v37_r30 = static_cast(_metile_v36_r30);\n float _metile_v37_r31 = static_cast(_metile_v36_r31);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v38_r16 = _metile_v21_r16 * v29;\n float _metile_v38_r17 = _metile_v21_r17 * v29;\n float _metile_v38_r18 = _metile_v21_r18 * v29;\n float _metile_v38_r19 = _metile_v21_r19 * v29;\n float _metile_v38_r20 = _metile_v21_r20 * v29;\n float _metile_v38_r21 = _metile_v21_r21 * v29;\n float _metile_v38_r22 = _metile_v21_r22 * v29;\n float _metile_v38_r23 = _metile_v21_r23 * v29;\n float _metile_v38_r24 = _metile_v21_r24 * v29;\n float _metile_v38_r25 = _metile_v21_r25 * v29;\n float _metile_v38_r26 = _metile_v21_r26 * v29;\n float _metile_v38_r27 = _metile_v21_r27 * v29;\n float _metile_v38_r28 = _metile_v21_r28 * v29;\n float _metile_v38_r29 = _metile_v21_r29 * v29;\n float _metile_v38_r30 = _metile_v21_r30 * v29;\n float _metile_v38_r31 = _metile_v21_r31 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n float _metile_v39_r16 = _metile_v38_r16 * _metile_v37_r16;\n float _metile_v39_r17 = _metile_v38_r17 * _metile_v37_r17;\n float _metile_v39_r18 = _metile_v38_r18 * _metile_v37_r18;\n float _metile_v39_r19 = _metile_v38_r19 * _metile_v37_r19;\n float _metile_v39_r20 = _metile_v38_r20 * _metile_v37_r20;\n float _metile_v39_r21 = _metile_v38_r21 * _metile_v37_r21;\n float _metile_v39_r22 = _metile_v38_r22 * _metile_v37_r22;\n float _metile_v39_r23 = _metile_v38_r23 * _metile_v37_r23;\n float _metile_v39_r24 = _metile_v38_r24 * _metile_v37_r24;\n float _metile_v39_r25 = _metile_v38_r25 * _metile_v37_r25;\n float _metile_v39_r26 = _metile_v38_r26 * _metile_v37_r26;\n float _metile_v39_r27 = _metile_v38_r27 * _metile_v37_r27;\n float _metile_v39_r28 = _metile_v38_r28 * _metile_v37_r28;\n float _metile_v39_r29 = _metile_v38_r29 * _metile_v37_r29;\n float _metile_v39_r30 = _metile_v38_r30 * _metile_v37_r30;\n float _metile_v39_r31 = _metile_v38_r31 * _metile_v37_r31;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v41_r16 = _metile_register_index________________ >= 0;\n bool _metile_v41_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v41_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v41_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v41_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v41_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v41_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v41_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v41_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v41_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v41_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v41_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v41_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v41_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v41_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v41_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v42_r4 = _metile_register_index____ < 1009;\n bool _metile_v42_r5 = _metile_register_index_____ < 1009;\n bool _metile_v42_r6 = _metile_register_index______ < 1009;\n bool _metile_v42_r7 = _metile_register_index_______ < 1009;\n bool _metile_v42_r8 = _metile_register_index________ < 1009;\n bool _metile_v42_r9 = _metile_register_index_________ < 1009;\n bool _metile_v42_r10 = _metile_register_index__________ < 1009;\n bool _metile_v42_r11 = _metile_register_index___________ < 1009;\n bool _metile_v42_r12 = _metile_register_index____________ < 1009;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1009;\n bool _metile_v42_r14 = _metile_register_index______________ < 1009;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1009;\n bool _metile_v42_r16 = _metile_register_index________________ < 1009;\n bool _metile_v42_r17 = _metile_register_index_________________ < 1009;\n bool _metile_v42_r18 = _metile_register_index__________________ < 1009;\n bool _metile_v42_r19 = _metile_register_index___________________ < 1009;\n bool _metile_v42_r20 = _metile_register_index____________________ < 1009;\n bool _metile_v42_r21 = _metile_register_index_____________________ < 1009;\n bool _metile_v42_r22 = _metile_register_index______________________ < 1009;\n bool _metile_v42_r23 = _metile_register_index_______________________ < 1009;\n bool _metile_v42_r24 = _metile_register_index________________________ < 1009;\n bool _metile_v42_r25 = _metile_register_index_________________________ < 1009;\n bool _metile_v42_r26 = _metile_register_index__________________________ < 1009;\n bool _metile_v42_r27 = _metile_register_index___________________________ < 1009;\n bool _metile_v42_r28 = _metile_register_index____________________________ < 1009;\n bool _metile_v42_r29 = _metile_register_index_____________________________ < 1009;\n bool _metile_v42_r30 = _metile_register_index______________________________ < 1009;\n bool _metile_v42_r31 = _metile_register_index_______________________________ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n bool _metile_v43_r16 = _metile_v41_r16 & _metile_v42_r16;\n bool _metile_v43_r17 = _metile_v41_r17 & _metile_v42_r17;\n bool _metile_v43_r18 = _metile_v41_r18 & _metile_v42_r18;\n bool _metile_v43_r19 = _metile_v41_r19 & _metile_v42_r19;\n bool _metile_v43_r20 = _metile_v41_r20 & _metile_v42_r20;\n bool _metile_v43_r21 = _metile_v41_r21 & _metile_v42_r21;\n bool _metile_v43_r22 = _metile_v41_r22 & _metile_v42_r22;\n bool _metile_v43_r23 = _metile_v41_r23 & _metile_v42_r23;\n bool _metile_v43_r24 = _metile_v41_r24 & _metile_v42_r24;\n bool _metile_v43_r25 = _metile_v41_r25 & _metile_v42_r25;\n bool _metile_v43_r26 = _metile_v41_r26 & _metile_v42_r26;\n bool _metile_v43_r27 = _metile_v41_r27 & _metile_v42_r27;\n bool _metile_v43_r28 = _metile_v41_r28 & _metile_v42_r28;\n bool _metile_v43_r29 = _metile_v41_r29 & _metile_v42_r29;\n bool _metile_v43_r30 = _metile_v41_r30 & _metile_v42_r30;\n bool _metile_v43_r31 = _metile_v41_r31 & _metile_v42_r31;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n int _off__metile_v44_r16 = v9 + _metile_register_index________________;\n int _off__metile_v44_r17 = v9 + _metile_register_index_________________;\n int _off__metile_v44_r18 = v9 + _metile_register_index__________________;\n int _off__metile_v44_r19 = v9 + _metile_register_index___________________;\n int _off__metile_v44_r20 = v9 + _metile_register_index____________________;\n int _off__metile_v44_r21 = v9 + _metile_register_index_____________________;\n int _off__metile_v44_r22 = v9 + _metile_register_index______________________;\n int _off__metile_v44_r23 = v9 + _metile_register_index_______________________;\n int _off__metile_v44_r24 = v9 + _metile_register_index________________________;\n int _off__metile_v44_r25 = v9 + _metile_register_index_________________________;\n int _off__metile_v44_r26 = v9 + _metile_register_index__________________________;\n int _off__metile_v44_r27 = v9 + _metile_register_index___________________________;\n int _off__metile_v44_r28 = v9 + _metile_register_index____________________________;\n int _off__metile_v44_r29 = v9 + _metile_register_index_____________________________;\n int _off__metile_v44_r30 = v9 + _metile_register_index______________________________;\n int _off__metile_v44_r31 = v9 + _metile_register_index_______________________________;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_float4(float4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_float4(float4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n if ((_metile_v43_r8) && (_metile_v43_r9) && (_metile_v43_r10) && (_metile_v43_r11) && (long(_off__metile_v44_r9) == long(_off__metile_v44_r8) + 1) && (long(_off__metile_v44_r10) == long(_off__metile_v44_r8) + 2) && (long(_off__metile_v44_r11) == long(_off__metile_v44_r8) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r8) = packed_float4(float4(static_cast(_metile_v39_r8), static_cast(_metile_v39_r9), static_cast(_metile_v39_r10), static_cast(_metile_v39_r11)));\n } else {\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = static_cast(_metile_v39_r8); }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = static_cast(_metile_v39_r9); }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = static_cast(_metile_v39_r10); }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = static_cast(_metile_v39_r11); }\n }\n if ((_metile_v43_r12) && (_metile_v43_r13) && (_metile_v43_r14) && (_metile_v43_r15) && (long(_off__metile_v44_r13) == long(_off__metile_v44_r12) + 1) && (long(_off__metile_v44_r14) == long(_off__metile_v44_r12) + 2) && (long(_off__metile_v44_r15) == long(_off__metile_v44_r12) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r12) = packed_float4(float4(static_cast(_metile_v39_r12), static_cast(_metile_v39_r13), static_cast(_metile_v39_r14), static_cast(_metile_v39_r15)));\n } else {\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = static_cast(_metile_v39_r12); }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = static_cast(_metile_v39_r13); }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = static_cast(_metile_v39_r14); }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = static_cast(_metile_v39_r15); }\n }\n if ((_metile_v43_r16) && (_metile_v43_r17) && (_metile_v43_r18) && (_metile_v43_r19) && (long(_off__metile_v44_r17) == long(_off__metile_v44_r16) + 1) && (long(_off__metile_v44_r18) == long(_off__metile_v44_r16) + 2) && (long(_off__metile_v44_r19) == long(_off__metile_v44_r16) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r16) = packed_float4(float4(static_cast(_metile_v39_r16), static_cast(_metile_v39_r17), static_cast(_metile_v39_r18), static_cast(_metile_v39_r19)));\n } else {\n if (_metile_v43_r16) { Out[_off__metile_v44_r16] = static_cast(_metile_v39_r16); }\n if (_metile_v43_r17) { Out[_off__metile_v44_r17] = static_cast(_metile_v39_r17); }\n if (_metile_v43_r18) { Out[_off__metile_v44_r18] = static_cast(_metile_v39_r18); }\n if (_metile_v43_r19) { Out[_off__metile_v44_r19] = static_cast(_metile_v39_r19); }\n }\n if ((_metile_v43_r20) && (_metile_v43_r21) && (_metile_v43_r22) && (_metile_v43_r23) && (long(_off__metile_v44_r21) == long(_off__metile_v44_r20) + 1) && (long(_off__metile_v44_r22) == long(_off__metile_v44_r20) + 2) && (long(_off__metile_v44_r23) == long(_off__metile_v44_r20) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r20) = packed_float4(float4(static_cast(_metile_v39_r20), static_cast(_metile_v39_r21), static_cast(_metile_v39_r22), static_cast(_metile_v39_r23)));\n } else {\n if (_metile_v43_r20) { Out[_off__metile_v44_r20] = static_cast(_metile_v39_r20); }\n if (_metile_v43_r21) { Out[_off__metile_v44_r21] = static_cast(_metile_v39_r21); }\n if (_metile_v43_r22) { Out[_off__metile_v44_r22] = static_cast(_metile_v39_r22); }\n if (_metile_v43_r23) { Out[_off__metile_v44_r23] = static_cast(_metile_v39_r23); }\n }\n if ((_metile_v43_r24) && (_metile_v43_r25) && (_metile_v43_r26) && (_metile_v43_r27) && (long(_off__metile_v44_r25) == long(_off__metile_v44_r24) + 1) && (long(_off__metile_v44_r26) == long(_off__metile_v44_r24) + 2) && (long(_off__metile_v44_r27) == long(_off__metile_v44_r24) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r24) = packed_float4(float4(static_cast(_metile_v39_r24), static_cast(_metile_v39_r25), static_cast(_metile_v39_r26), static_cast(_metile_v39_r27)));\n } else {\n if (_metile_v43_r24) { Out[_off__metile_v44_r24] = static_cast(_metile_v39_r24); }\n if (_metile_v43_r25) { Out[_off__metile_v44_r25] = static_cast(_metile_v39_r25); }\n if (_metile_v43_r26) { Out[_off__metile_v44_r26] = static_cast(_metile_v39_r26); }\n if (_metile_v43_r27) { Out[_off__metile_v44_r27] = static_cast(_metile_v39_r27); }\n }\n if ((_metile_v43_r28) && (_metile_v43_r29) && (_metile_v43_r30) && (_metile_v43_r31) && (long(_off__metile_v44_r29) == long(_off__metile_v44_r28) + 1) && (long(_off__metile_v44_r30) == long(_off__metile_v44_r28) + 2) && (long(_off__metile_v44_r31) == long(_off__metile_v44_r28) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r28) = packed_float4(float4(static_cast(_metile_v39_r28), static_cast(_metile_v39_r29), static_cast(_metile_v39_r30), static_cast(_metile_v39_r31)));\n } else {\n if (_metile_v43_r28) { Out[_off__metile_v44_r28] = static_cast(_metile_v39_r28); }\n if (_metile_v43_r29) { Out[_off__metile_v44_r29] = static_cast(_metile_v39_r29); }\n if (_metile_v43_r30) { Out[_off__metile_v44_r30] = static_cast(_metile_v39_r30); }\n if (_metile_v43_r31) { Out[_off__metile_v44_r31] = static_cast(_metile_v39_r31); }\n }\n}", "source_sha256": "8205038bf6ba3e8bd71e472a270b8fc036d7a98adf4a40b12e66c4dc7e4b1644", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 32, 1, 1 ], "is_gemm": false, "prefer_ordered": false, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 32, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 32 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [], "double_buffered": false, "vectorized_loads": 16, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 32, "threads": 32, "scratch": null, "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 16, "grouped_stores": 8 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 312, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 284.5625, "control": 271.91700000000003, "speedup": 0.9555616077311664 }, "gpu_us": { "candidate": 33.729185815900564, "control": 25.249988539144397, "speedup": 0.7486094884401593 } } }, { "frozen_register4": { "pairs": 497, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 234.334, "control": 234.625, "speedup": 1.0012418172352284 }, "gpu_us": { "candidate": 15.124969650059938, "control": 10.374991688877344, "speedup": 0.6859512401624045 } } }, { "frozen_register4": { "pairs": 529, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 222.0, "control": 217.375, "speedup": 0.9791666666666666 }, "gpu_us": { "candidate": 11.374999303370714, "control": 8.45832983031869, "speedup": 0.7435894811714197 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9784788234126052, "round_speedups": [ 0.9555616077311664, 1.0012418172352284, 0.9791666666666666 ], "candidate": 245.53984799424748, "control": 240.25554156632109 }, "gpu_us": { "speedup": 0.7254830500951702, "round_speedups": [ 0.7486094884401593, 0.6859512401624045, 0.7435894811714197 ], "candidate": 17.970103681331924, "control": 13.037005629259129 } } } }, { "name": "float32_1x1024", "dtype": "float32", "batches": 1, "width": 1024, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "ddb1751346f69e81810fa3e5e4fc2fa3d8214ffaace8e689775a59ca252f7042", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 2.384185791015625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "26dcd97c409e667a170eb1ec796096fa645431253522d88e56e53edb0819b727", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 605, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 206.583, "control": 206.875, "speedup": 1.001413475455386 }, "gpu_us": { "candidate": 1.583306584507227, "control": 1.6666599549353123, "speedup": 1.0526451233410536 } } }, { "frozen_register4": { "pairs": 602, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 203.72899999999998, "control": 203.83350000000002, "speedup": 1.0005129363026375 }, "gpu_us": { "candidate": 1.5416881069540977, "control": 1.6249832697212696, "speedup": 1.054028543381409 } } }, { "frozen_register4": { "pairs": 509, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 203.542, "control": 203.0, "speedup": 0.9973371589156046 }, "gpu_us": { "candidate": 1.5416881069540977, "control": 1.6249832697212696, "speedup": 1.054028543381409 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9997529936720663, "round_speedups": [ 1.001413475455386, 1.0005129363026375, 0.9973371589156046 ], "candidate": 204.6132830125471, "control": 204.56274223686364 }, "gpu_us": { "speedup": 1.0535672014708575, "round_speedups": [ 1.0526451233410536, 1.054028543381409, 1.054028543381409 ], "candidate": 1.5554379378249839, "control": 1.6387583952158695 } } } }, { "name": "float32_1x1024", "dtype": "float32", "batches": 1, "width": 1024, "status": "measured", "variant": { "name": "register4_blocked4", "elements_per_thread": 4, "layout": "blocked4" }, "input_sha256": "ddb1751346f69e81810fa3e5e4fc2fa3d8214ffaace8e689775a59ca252f7042", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int((((_metile_bounded_thread >> 8) & 1u) << 0) | (((_metile_bounded_thread >> 9) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 6) & 1u) << 8) | (((_metile_bounded_thread >> 7) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 8) & 1u) << 0) | (((_metile_register_packed_ >> 9) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 6) & 1u) << 8) | (((_metile_register_packed_ >> 7) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 8) & 1u) << 0) | (((_metile_register_packed__ >> 9) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 6) & 1u) << 8) | (((_metile_register_packed__ >> 7) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 8) & 1u) << 0) | (((_metile_register_packed___ >> 9) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 6) & 1u) << 8) | (((_metile_register_packed___ >> 7) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = float4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n float _metile_v20_r0 = _metile_vector_load[0];\n float _metile_v20_r1 = _metile_vector_load[1];\n float _metile_v20_r2 = _metile_vector_load[2];\n float _metile_v20_r3 = _metile_vector_load[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float4 _metile_vector_load_;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load_ = float4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load_[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load_[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load_[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load_[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n float _metile_v36_r0 = _metile_vector_load_[0];\n float _metile_v36_r1 = _metile_vector_load_[1];\n float _metile_v36_r2 = _metile_vector_load_[2];\n float _metile_v36_r3 = _metile_vector_load_[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_float4(float4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n}", "source_sha256": "90092f2d024ec05aca53dadb1c2ad4b583c721cc8dccc7ae0562e9412f81c900", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 2, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 2, "grouped_stores": 1 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 549, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.916, "control": 199.125, "speedup": 0.9910858269127397 }, "gpu_us": { "candidate": 1.708336640149355, "control": 1.625041477382183, "speedup": 0.9512419503219871 } } }, { "frozen_register4": { "pairs": 617, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.625, "control": 198.334, "speedup": 0.9985349276274387 }, "gpu_us": { "candidate": 1.6666599549353123, "control": 1.6249832697212696, "speedup": 0.9749938881709915 } } }, { "frozen_register4": { "pairs": 473, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 211.791, "control": 214.167, "speedup": 1.0112186070229614 }, "gpu_us": { "candidate": 3.1249946914613247, "control": 3.041699528694153, "speedup": 0.9733455026356473 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0002453155852857, "round_speedups": [ 0.9910858269127397, 0.9985349276274387, 1.0112186070229614 ], "candidate": 203.6973182913737, "control": 203.7472884182313 }, "gpu_us": { "speedup": 0.9664661288418992, "round_speedups": [ 0.9512419503219871, 0.9749938881709915, 0.9733455026356473 ], "candidate": 2.072159812639354, "control": 2.0026722724633115 } } } }, { "name": "float32_1x1024", "dtype": "float32", "batches": 1, "width": 1024, "status": "measured", "variant": { "name": "register8_striped", "elements_per_thread": 8, "layout": "striped" }, "input_sha256": "ddb1751346f69e81810fa3e5e4fc2fa3d8214ffaace8e689775a59ca252f7042", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 2.384185791015625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 127;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 128;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 256;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 384;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 512;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 640;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 768;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 896;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n float _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n float _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n float _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_____ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum______ = _metile_register_sum____ + _metile_register_sum_____;\n threadgroup float _metile_register_reduction[4];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 4u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n float _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n float _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n float _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n}", "source_sha256": "34702ecd3ed2337fb2f6ddd5e80d06f362dc722ce7e9d0c31a768733f59fa7cf", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 128, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 128, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 8 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 4, "bytes": 16 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 8, "threads": 128, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 622, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 196.583, "control": 196.6875, "speedup": 1.000531582079834 }, "gpu_us": { "candidate": 1.6249832697212696, "control": 1.6249832697212696, "speedup": 1.0 } } }, { "frozen_register4": { "pairs": 628, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 195.938, "control": 194.917, "speedup": 0.9947891680021231 }, "gpu_us": { "candidate": 1.6249832697212696, "control": 1.6250123735517263, "speedup": 1.0000179102339077 } } }, { "frozen_register4": { "pairs": 623, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.125, "control": 196.625, "speedup": 0.9974635383639823 }, "gpu_us": { "candidate": 1.6249832697212696, "control": 1.6249832697212696, "speedup": 1.0 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9975920042858131, "round_speedups": [ 1.000531582079834, 0.9947891680021231, 0.9974635383639823 ], "candidate": 196.54806768204156, "control": 196.0747807774315 }, "gpu_us": { "speedup": 1.0000059700423278, "round_speedups": [ 1.0, 1.0000179102339077, 1.0 ], "candidate": 1.6249832697212696, "control": 1.6249929709401716 } } } }, { "name": "float32_1x1024", "dtype": "float32", "batches": 1, "width": 1024, "status": "measured", "variant": { "name": "register8_blocked4", "elements_per_thread": 8, "layout": "blocked4" }, "input_sha256": "ddb1751346f69e81810fa3e5e4fc2fa3d8214ffaace8e689775a59ca252f7042", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 4.76837158203125e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 127;\n int _metile_register_index = int((((_metile_bounded_thread >> 7) & 1u) << 0) | (((_metile_bounded_thread >> 8) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 6) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 128;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 7) & 1u) << 0) | (((_metile_register_packed_ >> 8) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 6) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 256;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 7) & 1u) << 0) | (((_metile_register_packed__ >> 8) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 6) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 384;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 7) & 1u) << 0) | (((_metile_register_packed___ >> 8) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 6) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 512;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 7) & 1u) << 0) | (((_metile_register_packed____ >> 8) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 5) & 1u) << 7) | (((_metile_register_packed____ >> 6) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 640;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 7) & 1u) << 0) | (((_metile_register_packed_____ >> 8) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 5) & 1u) << 7) | (((_metile_register_packed_____ >> 6) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 768;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 7) & 1u) << 0) | (((_metile_register_packed______ >> 8) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 5) & 1u) << 7) | (((_metile_register_packed______ >> 6) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 896;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 7) & 1u) << 0) | (((_metile_register_packed_______ >> 8) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 5) & 1u) << 7) | (((_metile_register_packed_______ >> 6) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n float4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = float4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n float _metile_v20_r0 = _metile_vector_load[0];\n float _metile_v20_r1 = _metile_vector_load[1];\n float _metile_v20_r2 = _metile_vector_load[2];\n float _metile_v20_r3 = _metile_vector_load[3];\n float4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = float4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n float _metile_v20_r4 = _metile_vector_load_[0];\n float _metile_v20_r5 = _metile_vector_load_[1];\n float _metile_v20_r6 = _metile_vector_load_[2];\n float _metile_v20_r7 = _metile_vector_load_[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_____ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum______ = _metile_register_sum____ + _metile_register_sum_____;\n threadgroup float _metile_register_reduction[4];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 4u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n float4 _metile_vector_load__;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load__ = float4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load__[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load__[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load__[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load__[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n float _metile_v36_r0 = _metile_vector_load__[0];\n float _metile_v36_r1 = _metile_vector_load__[1];\n float _metile_v36_r2 = _metile_vector_load__[2];\n float _metile_v36_r3 = _metile_vector_load__[3];\n float4 _metile_vector_load___;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load___ = float4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load___[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load___[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load___[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load___[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n float _metile_v36_r4 = _metile_vector_load___[0];\n float _metile_v36_r5 = _metile_vector_load___[1];\n float _metile_v36_r6 = _metile_vector_load___[2];\n float _metile_v36_r7 = _metile_vector_load___[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_float4(float4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_float4(float4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n}", "source_sha256": "6d76f908be757e95d29fcc3112125422c90cd6abc0b258ca9347b3c9175af34b", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 128, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 128, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 8 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 4, "bytes": 16 } ], "double_buffered": false, "vectorized_loads": 4, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 8, "threads": 128, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 4, "grouped_stores": 2 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 608, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 196.2705, "control": 197.3955, "speedup": 1.0057318853317234 }, "gpu_us": { "candidate": 1.9166618585586548, "control": 1.6249832697212696, "speedup": 0.8478194849368319 } } }, { "frozen_register4": { "pairs": 611, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 195.75, "control": 197.166, "speedup": 1.0072337164750957 }, "gpu_us": { "candidate": 1.9166618585586548, "control": 1.6249832697212696, "speedup": 0.8478194849368319 } } }, { "frozen_register4": { "pairs": 506, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 203.9375, "control": 204.85399999999998, "speedup": 1.0044940239043825 }, "gpu_us": { "candidate": 2.0416919142007828, "control": 1.708336640149355, "speedup": 0.836725966472802 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.005819251492949, "round_speedups": [ 1.0057318853317234, 1.0072337164750957, 1.0044940239043825 ], "candidate": 198.61770691916146, "control": 199.77351330667693 }, "gpu_us": { "speedup": 0.8441053987201986, "round_speedups": [ 0.8478194849368319, 0.8478194849368319, 0.836725966472802 ], "candidate": 1.9574637880835677, "control": 1.6523057513206303 } } } }, { "name": "float32_1x1024", "dtype": "float32", "batches": 1, "width": 1024, "status": "measured", "variant": { "name": "register16_striped", "elements_per_thread": 16, "layout": "striped" }, "input_sha256": "ddb1751346f69e81810fa3e5e4fc2fa3d8214ffaace8e689775a59ca252f7042", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 2.384185791015625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 63;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 64;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 128;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 192;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 256;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 320;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 384;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 448;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n int _metile_register_packed________ = _metile_bounded_thread + 512;\n int _metile_register_index________ = int(_metile_register_packed________);\n int _metile_register_packed_________ = _metile_bounded_thread + 576;\n int _metile_register_index_________ = int(_metile_register_packed_________);\n int _metile_register_packed__________ = _metile_bounded_thread + 640;\n int _metile_register_index__________ = int(_metile_register_packed__________);\n int _metile_register_packed___________ = _metile_bounded_thread + 704;\n int _metile_register_index___________ = int(_metile_register_packed___________);\n int _metile_register_packed____________ = _metile_bounded_thread + 768;\n int _metile_register_index____________ = int(_metile_register_packed____________);\n int _metile_register_packed_____________ = _metile_bounded_thread + 832;\n int _metile_register_index_____________ = int(_metile_register_packed_____________);\n int _metile_register_packed______________ = _metile_bounded_thread + 896;\n int _metile_register_index______________ = int(_metile_register_packed______________);\n int _metile_register_packed_______________ = _metile_bounded_thread + 960;\n int _metile_register_index_______________ = int(_metile_register_packed_______________);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v17_r8 = _metile_register_index________ < 1024;\n bool _metile_v17_r9 = _metile_register_index_________ < 1024;\n bool _metile_v17_r10 = _metile_register_index__________ < 1024;\n bool _metile_v17_r11 = _metile_register_index___________ < 1024;\n bool _metile_v17_r12 = _metile_register_index____________ < 1024;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v17_r14 = _metile_register_index______________ < 1024;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n float _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n float _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n float _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n float _metile_v20_r8 = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n float _metile_v20_r9 = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n float _metile_v20_r10 = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n float _metile_v20_r11 = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n float _metile_v20_r12 = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n float _metile_v20_r13 = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n float _metile_v20_r14 = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n float _metile_v20_r15 = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________ = _metile_register_sum____________ + _metile_register_sum_____________;\n threadgroup float _metile_register_reduction[2];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______________);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 2u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v33_r8 = _metile_register_index________ < 1024;\n bool _metile_v33_r9 = _metile_register_index_________ < 1024;\n bool _metile_v33_r10 = _metile_register_index__________ < 1024;\n bool _metile_v33_r11 = _metile_register_index___________ < 1024;\n bool _metile_v33_r12 = _metile_register_index____________ < 1024;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v33_r14 = _metile_register_index______________ < 1024;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n float _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n float _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n float _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n float _metile_v36_r8 = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n float _metile_v36_r9 = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n float _metile_v36_r10 = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n float _metile_v36_r11 = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n float _metile_v36_r12 = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n float _metile_v36_r13 = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n float _metile_v36_r14 = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n float _metile_v36_r15 = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v42_r8 = _metile_register_index________ < 1024;\n bool _metile_v42_r9 = _metile_register_index_________ < 1024;\n bool _metile_v42_r10 = _metile_register_index__________ < 1024;\n bool _metile_v42_r11 = _metile_register_index___________ < 1024;\n bool _metile_v42_r12 = _metile_register_index____________ < 1024;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v42_r14 = _metile_register_index______________ < 1024;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = _metile_v39_r8; }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = _metile_v39_r9; }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = _metile_v39_r10; }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = _metile_v39_r11; }\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = _metile_v39_r12; }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = _metile_v39_r13; }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = _metile_v39_r14; }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = _metile_v39_r15; }\n}", "source_sha256": "8d0e0811f88b35d004a56a9d076dee253811a6b9bdd8f46462f1664bdcec06df", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 64, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 64, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 16 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 2, "bytes": 8 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 16, "threads": 64, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 516, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.1045, "control": 199.1045, "speedup": 0.9950026111356816 }, "gpu_us": { "candidate": 1.7500133253633976, "control": 1.666689058765769, "speedup": 0.9523864959254947 } } }, { "frozen_register4": { "pairs": 603, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.541, "control": 198.75, "speedup": 1.0061202484547511 }, "gpu_us": { "candidate": 1.7082784324884415, "control": 1.6249832697212696, "speedup": 0.9512402889464359 } } }, { "frozen_register4": { "pairs": 594, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.3955, "control": 199.79149999999998, "speedup": 1.012138067990405 }, "gpu_us": { "candidate": 1.6666599549353123, "control": 1.6249832697212696, "speedup": 0.9749938881709915 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0043951874983994, "round_speedups": [ 0.9950026111356816, 1.0061202484547511, 1.012138067990405 ], "candidate": 198.34310926425817, "control": 199.21486441849007 }, "gpu_us": { "speedup": 0.9594782170400632, "round_speedups": [ 0.9523864959254947, 0.9512402889464359, 0.9749938881709915 ], "candidate": 1.7079782583116543, "control": 1.6387679340280588 } } } }, { "name": "float32_1x1024", "dtype": "float32", "batches": 1, "width": 1024, "status": "measured", "variant": { "name": "register16_blocked4", "elements_per_thread": 16, "layout": "blocked4" }, "input_sha256": "ddb1751346f69e81810fa3e5e4fc2fa3d8214ffaace8e689775a59ca252f7042", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 63;\n int _metile_register_index = int((((_metile_bounded_thread >> 6) & 1u) << 0) | (((_metile_bounded_thread >> 7) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 8) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 64;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 6) & 1u) << 0) | (((_metile_register_packed_ >> 7) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 8) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 128;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 6) & 1u) << 0) | (((_metile_register_packed__ >> 7) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 8) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 192;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 6) & 1u) << 0) | (((_metile_register_packed___ >> 7) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 8) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 256;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 6) & 1u) << 0) | (((_metile_register_packed____ >> 7) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 5) & 1u) << 7) | (((_metile_register_packed____ >> 8) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 320;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 6) & 1u) << 0) | (((_metile_register_packed_____ >> 7) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 5) & 1u) << 7) | (((_metile_register_packed_____ >> 8) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 384;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 6) & 1u) << 0) | (((_metile_register_packed______ >> 7) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 5) & 1u) << 7) | (((_metile_register_packed______ >> 8) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 448;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 6) & 1u) << 0) | (((_metile_register_packed_______ >> 7) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 5) & 1u) << 7) | (((_metile_register_packed_______ >> 8) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n int _metile_register_packed________ = _metile_bounded_thread + 512;\n int _metile_register_index________ = int((((_metile_register_packed________ >> 6) & 1u) << 0) | (((_metile_register_packed________ >> 7) & 1u) << 1) | (((_metile_register_packed________ >> 0) & 1u) << 2) | (((_metile_register_packed________ >> 1) & 1u) << 3) | (((_metile_register_packed________ >> 2) & 1u) << 4) | (((_metile_register_packed________ >> 3) & 1u) << 5) | (((_metile_register_packed________ >> 4) & 1u) << 6) | (((_metile_register_packed________ >> 5) & 1u) << 7) | (((_metile_register_packed________ >> 8) & 1u) << 8) | (((_metile_register_packed________ >> 9) & 1u) << 9));\n int _metile_register_packed_________ = _metile_bounded_thread + 576;\n int _metile_register_index_________ = int((((_metile_register_packed_________ >> 6) & 1u) << 0) | (((_metile_register_packed_________ >> 7) & 1u) << 1) | (((_metile_register_packed_________ >> 0) & 1u) << 2) | (((_metile_register_packed_________ >> 1) & 1u) << 3) | (((_metile_register_packed_________ >> 2) & 1u) << 4) | (((_metile_register_packed_________ >> 3) & 1u) << 5) | (((_metile_register_packed_________ >> 4) & 1u) << 6) | (((_metile_register_packed_________ >> 5) & 1u) << 7) | (((_metile_register_packed_________ >> 8) & 1u) << 8) | (((_metile_register_packed_________ >> 9) & 1u) << 9));\n int _metile_register_packed__________ = _metile_bounded_thread + 640;\n int _metile_register_index__________ = int((((_metile_register_packed__________ >> 6) & 1u) << 0) | (((_metile_register_packed__________ >> 7) & 1u) << 1) | (((_metile_register_packed__________ >> 0) & 1u) << 2) | (((_metile_register_packed__________ >> 1) & 1u) << 3) | (((_metile_register_packed__________ >> 2) & 1u) << 4) | (((_metile_register_packed__________ >> 3) & 1u) << 5) | (((_metile_register_packed__________ >> 4) & 1u) << 6) | (((_metile_register_packed__________ >> 5) & 1u) << 7) | (((_metile_register_packed__________ >> 8) & 1u) << 8) | (((_metile_register_packed__________ >> 9) & 1u) << 9));\n int _metile_register_packed___________ = _metile_bounded_thread + 704;\n int _metile_register_index___________ = int((((_metile_register_packed___________ >> 6) & 1u) << 0) | (((_metile_register_packed___________ >> 7) & 1u) << 1) | (((_metile_register_packed___________ >> 0) & 1u) << 2) | (((_metile_register_packed___________ >> 1) & 1u) << 3) | (((_metile_register_packed___________ >> 2) & 1u) << 4) | (((_metile_register_packed___________ >> 3) & 1u) << 5) | (((_metile_register_packed___________ >> 4) & 1u) << 6) | (((_metile_register_packed___________ >> 5) & 1u) << 7) | (((_metile_register_packed___________ >> 8) & 1u) << 8) | (((_metile_register_packed___________ >> 9) & 1u) << 9));\n int _metile_register_packed____________ = _metile_bounded_thread + 768;\n int _metile_register_index____________ = int((((_metile_register_packed____________ >> 6) & 1u) << 0) | (((_metile_register_packed____________ >> 7) & 1u) << 1) | (((_metile_register_packed____________ >> 0) & 1u) << 2) | (((_metile_register_packed____________ >> 1) & 1u) << 3) | (((_metile_register_packed____________ >> 2) & 1u) << 4) | (((_metile_register_packed____________ >> 3) & 1u) << 5) | (((_metile_register_packed____________ >> 4) & 1u) << 6) | (((_metile_register_packed____________ >> 5) & 1u) << 7) | (((_metile_register_packed____________ >> 8) & 1u) << 8) | (((_metile_register_packed____________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________ = _metile_bounded_thread + 832;\n int _metile_register_index_____________ = int((((_metile_register_packed_____________ >> 6) & 1u) << 0) | (((_metile_register_packed_____________ >> 7) & 1u) << 1) | (((_metile_register_packed_____________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________ >> 5) & 1u) << 7) | (((_metile_register_packed_____________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________ >> 9) & 1u) << 9));\n int _metile_register_packed______________ = _metile_bounded_thread + 896;\n int _metile_register_index______________ = int((((_metile_register_packed______________ >> 6) & 1u) << 0) | (((_metile_register_packed______________ >> 7) & 1u) << 1) | (((_metile_register_packed______________ >> 0) & 1u) << 2) | (((_metile_register_packed______________ >> 1) & 1u) << 3) | (((_metile_register_packed______________ >> 2) & 1u) << 4) | (((_metile_register_packed______________ >> 3) & 1u) << 5) | (((_metile_register_packed______________ >> 4) & 1u) << 6) | (((_metile_register_packed______________ >> 5) & 1u) << 7) | (((_metile_register_packed______________ >> 8) & 1u) << 8) | (((_metile_register_packed______________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________ = _metile_bounded_thread + 960;\n int _metile_register_index_______________ = int((((_metile_register_packed_______________ >> 6) & 1u) << 0) | (((_metile_register_packed_______________ >> 7) & 1u) << 1) | (((_metile_register_packed_______________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________ >> 5) & 1u) << 7) | (((_metile_register_packed_______________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v17_r8 = _metile_register_index________ < 1024;\n bool _metile_v17_r9 = _metile_register_index_________ < 1024;\n bool _metile_v17_r10 = _metile_register_index__________ < 1024;\n bool _metile_v17_r11 = _metile_register_index___________ < 1024;\n bool _metile_v17_r12 = _metile_register_index____________ < 1024;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v17_r14 = _metile_register_index______________ < 1024;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n float4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = float4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n float _metile_v20_r0 = _metile_vector_load[0];\n float _metile_v20_r1 = _metile_vector_load[1];\n float _metile_v20_r2 = _metile_vector_load[2];\n float _metile_v20_r3 = _metile_vector_load[3];\n float4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = float4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n float _metile_v20_r4 = _metile_vector_load_[0];\n float _metile_v20_r5 = _metile_vector_load_[1];\n float _metile_v20_r6 = _metile_vector_load_[2];\n float _metile_v20_r7 = _metile_vector_load_[3];\n float4 _metile_vector_load__;\n if ((_metile_v18_r8) && (_metile_v18_r9) && (_metile_v18_r10) && (_metile_v18_r11) && (long(_off__metile_v19_r9) == long(_off__metile_v19_r8) + 1) && (long(_off__metile_v19_r10) == long(_off__metile_v19_r8) + 2) && (long(_off__metile_v19_r11) == long(_off__metile_v19_r8) + 3)) {\n _metile_vector_load__ = float4(*reinterpret_cast(X + _off__metile_v19_r8));\n } else {\n _metile_vector_load__[0] = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n _metile_vector_load__[1] = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n _metile_vector_load__[2] = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n _metile_vector_load__[3] = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n }\n float _metile_v20_r8 = _metile_vector_load__[0];\n float _metile_v20_r9 = _metile_vector_load__[1];\n float _metile_v20_r10 = _metile_vector_load__[2];\n float _metile_v20_r11 = _metile_vector_load__[3];\n float4 _metile_vector_load___;\n if ((_metile_v18_r12) && (_metile_v18_r13) && (_metile_v18_r14) && (_metile_v18_r15) && (long(_off__metile_v19_r13) == long(_off__metile_v19_r12) + 1) && (long(_off__metile_v19_r14) == long(_off__metile_v19_r12) + 2) && (long(_off__metile_v19_r15) == long(_off__metile_v19_r12) + 3)) {\n _metile_vector_load___ = float4(*reinterpret_cast(X + _off__metile_v19_r12));\n } else {\n _metile_vector_load___[0] = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n _metile_vector_load___[1] = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n _metile_vector_load___[2] = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n _metile_vector_load___[3] = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n }\n float _metile_v20_r12 = _metile_vector_load___[0];\n float _metile_v20_r13 = _metile_vector_load___[1];\n float _metile_v20_r14 = _metile_vector_load___[2];\n float _metile_v20_r15 = _metile_vector_load___[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________ = _metile_register_sum____________ + _metile_register_sum_____________;\n threadgroup float _metile_register_reduction[2];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______________);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 2u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v33_r8 = _metile_register_index________ < 1024;\n bool _metile_v33_r9 = _metile_register_index_________ < 1024;\n bool _metile_v33_r10 = _metile_register_index__________ < 1024;\n bool _metile_v33_r11 = _metile_register_index___________ < 1024;\n bool _metile_v33_r12 = _metile_register_index____________ < 1024;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v33_r14 = _metile_register_index______________ < 1024;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n float4 _metile_vector_load____;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load____ = float4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load____[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load____[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load____[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load____[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n float _metile_v36_r0 = _metile_vector_load____[0];\n float _metile_v36_r1 = _metile_vector_load____[1];\n float _metile_v36_r2 = _metile_vector_load____[2];\n float _metile_v36_r3 = _metile_vector_load____[3];\n float4 _metile_vector_load_____;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load_____ = float4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load_____[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load_____[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load_____[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load_____[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n float _metile_v36_r4 = _metile_vector_load_____[0];\n float _metile_v36_r5 = _metile_vector_load_____[1];\n float _metile_v36_r6 = _metile_vector_load_____[2];\n float _metile_v36_r7 = _metile_vector_load_____[3];\n float4 _metile_vector_load______;\n if ((_metile_v34_r8) && (_metile_v34_r9) && (_metile_v34_r10) && (_metile_v34_r11) && (long(_metile_register_index_________) == long(_metile_register_index________) + 1) && (long(_metile_register_index__________) == long(_metile_register_index________) + 2) && (long(_metile_register_index___________) == long(_metile_register_index________) + 3)) {\n _metile_vector_load______ = float4(*reinterpret_cast(W + _metile_register_index________));\n } else {\n _metile_vector_load______[0] = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n _metile_vector_load______[1] = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n _metile_vector_load______[2] = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n _metile_vector_load______[3] = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n }\n float _metile_v36_r8 = _metile_vector_load______[0];\n float _metile_v36_r9 = _metile_vector_load______[1];\n float _metile_v36_r10 = _metile_vector_load______[2];\n float _metile_v36_r11 = _metile_vector_load______[3];\n float4 _metile_vector_load_______;\n if ((_metile_v34_r12) && (_metile_v34_r13) && (_metile_v34_r14) && (_metile_v34_r15) && (long(_metile_register_index_____________) == long(_metile_register_index____________) + 1) && (long(_metile_register_index______________) == long(_metile_register_index____________) + 2) && (long(_metile_register_index_______________) == long(_metile_register_index____________) + 3)) {\n _metile_vector_load_______ = float4(*reinterpret_cast(W + _metile_register_index____________));\n } else {\n _metile_vector_load_______[0] = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n _metile_vector_load_______[1] = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n _metile_vector_load_______[2] = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n _metile_vector_load_______[3] = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n }\n float _metile_v36_r12 = _metile_vector_load_______[0];\n float _metile_v36_r13 = _metile_vector_load_______[1];\n float _metile_v36_r14 = _metile_vector_load_______[2];\n float _metile_v36_r15 = _metile_vector_load_______[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v42_r8 = _metile_register_index________ < 1024;\n bool _metile_v42_r9 = _metile_register_index_________ < 1024;\n bool _metile_v42_r10 = _metile_register_index__________ < 1024;\n bool _metile_v42_r11 = _metile_register_index___________ < 1024;\n bool _metile_v42_r12 = _metile_register_index____________ < 1024;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v42_r14 = _metile_register_index______________ < 1024;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_float4(float4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_float4(float4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n if ((_metile_v43_r8) && (_metile_v43_r9) && (_metile_v43_r10) && (_metile_v43_r11) && (long(_off__metile_v44_r9) == long(_off__metile_v44_r8) + 1) && (long(_off__metile_v44_r10) == long(_off__metile_v44_r8) + 2) && (long(_off__metile_v44_r11) == long(_off__metile_v44_r8) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r8) = packed_float4(float4(static_cast(_metile_v39_r8), static_cast(_metile_v39_r9), static_cast(_metile_v39_r10), static_cast(_metile_v39_r11)));\n } else {\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = static_cast(_metile_v39_r8); }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = static_cast(_metile_v39_r9); }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = static_cast(_metile_v39_r10); }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = static_cast(_metile_v39_r11); }\n }\n if ((_metile_v43_r12) && (_metile_v43_r13) && (_metile_v43_r14) && (_metile_v43_r15) && (long(_off__metile_v44_r13) == long(_off__metile_v44_r12) + 1) && (long(_off__metile_v44_r14) == long(_off__metile_v44_r12) + 2) && (long(_off__metile_v44_r15) == long(_off__metile_v44_r12) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r12) = packed_float4(float4(static_cast(_metile_v39_r12), static_cast(_metile_v39_r13), static_cast(_metile_v39_r14), static_cast(_metile_v39_r15)));\n } else {\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = static_cast(_metile_v39_r12); }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = static_cast(_metile_v39_r13); }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = static_cast(_metile_v39_r14); }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = static_cast(_metile_v39_r15); }\n }\n}", "source_sha256": "638bb86de40e605f8a6ccd7a4a97089454fbe67cb9c226a6b7a7e2134cb962f6", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 64, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 64, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 16 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 2, "bytes": 8 } ], "double_buffered": false, "vectorized_loads": 8, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 16, "threads": 64, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 8, "grouped_stores": 4 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 604, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.5, "control": 197.042, "speedup": 0.9976810126582278 }, "gpu_us": { "candidate": 2.374988980591297, "control": 1.6249832697212696, "speedup": 0.6842066565364443 } } }, { "frozen_register4": { "pairs": 638, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 195.375, "control": 194.8955, "speedup": 0.9975457453614843 }, "gpu_us": { "candidate": 2.3541797418147326, "control": 1.6249832697212696, "speedup": 0.6902545463536451 } } }, { "frozen_register4": { "pairs": 593, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.417, "control": 197.375, "speedup": 0.9848216468662838 }, "gpu_us": { "candidate": 2.374988980591297, "control": 1.6249832697212696, "speedup": 0.6842066565364443 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9933311114017306, "round_speedups": [ 0.9976810126582278, 0.9975457453614843, 0.9848216468662838 ], "candidate": 197.75321340373412, "control": 196.4344192535949 }, "gpu_us": { "speedup": 0.6862167089234682, "round_speedups": [ 0.6842066565364443, 0.6902545463536451, 0.6842066565364443 ], "candidate": 2.3680322099275775, "control": 1.6249832697212696 } } } }, { "name": "float32_1x1024", "dtype": "float32", "batches": 1, "width": 1024, "status": "measured", "variant": { "name": "register32_striped", "elements_per_thread": 32, "layout": "striped" }, "input_sha256": "ddb1751346f69e81810fa3e5e4fc2fa3d8214ffaace8e689775a59ca252f7042", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 4.76837158203125e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 31;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 32;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 64;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 96;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 128;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 160;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 192;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 224;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n int _metile_register_packed________ = _metile_bounded_thread + 256;\n int _metile_register_index________ = int(_metile_register_packed________);\n int _metile_register_packed_________ = _metile_bounded_thread + 288;\n int _metile_register_index_________ = int(_metile_register_packed_________);\n int _metile_register_packed__________ = _metile_bounded_thread + 320;\n int _metile_register_index__________ = int(_metile_register_packed__________);\n int _metile_register_packed___________ = _metile_bounded_thread + 352;\n int _metile_register_index___________ = int(_metile_register_packed___________);\n int _metile_register_packed____________ = _metile_bounded_thread + 384;\n int _metile_register_index____________ = int(_metile_register_packed____________);\n int _metile_register_packed_____________ = _metile_bounded_thread + 416;\n int _metile_register_index_____________ = int(_metile_register_packed_____________);\n int _metile_register_packed______________ = _metile_bounded_thread + 448;\n int _metile_register_index______________ = int(_metile_register_packed______________);\n int _metile_register_packed_______________ = _metile_bounded_thread + 480;\n int _metile_register_index_______________ = int(_metile_register_packed_______________);\n int _metile_register_packed________________ = _metile_bounded_thread + 512;\n int _metile_register_index________________ = int(_metile_register_packed________________);\n int _metile_register_packed_________________ = _metile_bounded_thread + 544;\n int _metile_register_index_________________ = int(_metile_register_packed_________________);\n int _metile_register_packed__________________ = _metile_bounded_thread + 576;\n int _metile_register_index__________________ = int(_metile_register_packed__________________);\n int _metile_register_packed___________________ = _metile_bounded_thread + 608;\n int _metile_register_index___________________ = int(_metile_register_packed___________________);\n int _metile_register_packed____________________ = _metile_bounded_thread + 640;\n int _metile_register_index____________________ = int(_metile_register_packed____________________);\n int _metile_register_packed_____________________ = _metile_bounded_thread + 672;\n int _metile_register_index_____________________ = int(_metile_register_packed_____________________);\n int _metile_register_packed______________________ = _metile_bounded_thread + 704;\n int _metile_register_index______________________ = int(_metile_register_packed______________________);\n int _metile_register_packed_______________________ = _metile_bounded_thread + 736;\n int _metile_register_index_______________________ = int(_metile_register_packed_______________________);\n int _metile_register_packed________________________ = _metile_bounded_thread + 768;\n int _metile_register_index________________________ = int(_metile_register_packed________________________);\n int _metile_register_packed_________________________ = _metile_bounded_thread + 800;\n int _metile_register_index_________________________ = int(_metile_register_packed_________________________);\n int _metile_register_packed__________________________ = _metile_bounded_thread + 832;\n int _metile_register_index__________________________ = int(_metile_register_packed__________________________);\n int _metile_register_packed___________________________ = _metile_bounded_thread + 864;\n int _metile_register_index___________________________ = int(_metile_register_packed___________________________);\n int _metile_register_packed____________________________ = _metile_bounded_thread + 896;\n int _metile_register_index____________________________ = int(_metile_register_packed____________________________);\n int _metile_register_packed_____________________________ = _metile_bounded_thread + 928;\n int _metile_register_index_____________________________ = int(_metile_register_packed_____________________________);\n int _metile_register_packed______________________________ = _metile_bounded_thread + 960;\n int _metile_register_index______________________________ = int(_metile_register_packed______________________________);\n int _metile_register_packed_______________________________ = _metile_bounded_thread + 992;\n int _metile_register_index_______________________________ = int(_metile_register_packed_______________________________);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v16_r16 = _metile_register_index________________ >= 0;\n bool _metile_v16_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v16_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v16_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v16_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v16_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v16_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v16_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v16_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v16_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v16_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v16_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v16_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v16_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v16_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v16_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v17_r8 = _metile_register_index________ < 1024;\n bool _metile_v17_r9 = _metile_register_index_________ < 1024;\n bool _metile_v17_r10 = _metile_register_index__________ < 1024;\n bool _metile_v17_r11 = _metile_register_index___________ < 1024;\n bool _metile_v17_r12 = _metile_register_index____________ < 1024;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v17_r14 = _metile_register_index______________ < 1024;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v17_r16 = _metile_register_index________________ < 1024;\n bool _metile_v17_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v17_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v17_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v17_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v17_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v17_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v17_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v17_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v17_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v17_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v17_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v17_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v17_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v17_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v17_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n bool _metile_v18_r16 = _metile_v16_r16 & _metile_v17_r16;\n bool _metile_v18_r17 = _metile_v16_r17 & _metile_v17_r17;\n bool _metile_v18_r18 = _metile_v16_r18 & _metile_v17_r18;\n bool _metile_v18_r19 = _metile_v16_r19 & _metile_v17_r19;\n bool _metile_v18_r20 = _metile_v16_r20 & _metile_v17_r20;\n bool _metile_v18_r21 = _metile_v16_r21 & _metile_v17_r21;\n bool _metile_v18_r22 = _metile_v16_r22 & _metile_v17_r22;\n bool _metile_v18_r23 = _metile_v16_r23 & _metile_v17_r23;\n bool _metile_v18_r24 = _metile_v16_r24 & _metile_v17_r24;\n bool _metile_v18_r25 = _metile_v16_r25 & _metile_v17_r25;\n bool _metile_v18_r26 = _metile_v16_r26 & _metile_v17_r26;\n bool _metile_v18_r27 = _metile_v16_r27 & _metile_v17_r27;\n bool _metile_v18_r28 = _metile_v16_r28 & _metile_v17_r28;\n bool _metile_v18_r29 = _metile_v16_r29 & _metile_v17_r29;\n bool _metile_v18_r30 = _metile_v16_r30 & _metile_v17_r30;\n bool _metile_v18_r31 = _metile_v16_r31 & _metile_v17_r31;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n int _off__metile_v19_r16 = v2 + _metile_register_index________________;\n int _off__metile_v19_r17 = v2 + _metile_register_index_________________;\n int _off__metile_v19_r18 = v2 + _metile_register_index__________________;\n int _off__metile_v19_r19 = v2 + _metile_register_index___________________;\n int _off__metile_v19_r20 = v2 + _metile_register_index____________________;\n int _off__metile_v19_r21 = v2 + _metile_register_index_____________________;\n int _off__metile_v19_r22 = v2 + _metile_register_index______________________;\n int _off__metile_v19_r23 = v2 + _metile_register_index_______________________;\n int _off__metile_v19_r24 = v2 + _metile_register_index________________________;\n int _off__metile_v19_r25 = v2 + _metile_register_index_________________________;\n int _off__metile_v19_r26 = v2 + _metile_register_index__________________________;\n int _off__metile_v19_r27 = v2 + _metile_register_index___________________________;\n int _off__metile_v19_r28 = v2 + _metile_register_index____________________________;\n int _off__metile_v19_r29 = v2 + _metile_register_index_____________________________;\n int _off__metile_v19_r30 = v2 + _metile_register_index______________________________;\n int _off__metile_v19_r31 = v2 + _metile_register_index_______________________________;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n float _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n float _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n float _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n float _metile_v20_r8 = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n float _metile_v20_r9 = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n float _metile_v20_r10 = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n float _metile_v20_r11 = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n float _metile_v20_r12 = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n float _metile_v20_r13 = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n float _metile_v20_r14 = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n float _metile_v20_r15 = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n float _metile_v20_r16 = _metile_v18_r16 ? X[_off__metile_v19_r16] : static_cast(0);\n float _metile_v20_r17 = _metile_v18_r17 ? X[_off__metile_v19_r17] : static_cast(0);\n float _metile_v20_r18 = _metile_v18_r18 ? X[_off__metile_v19_r18] : static_cast(0);\n float _metile_v20_r19 = _metile_v18_r19 ? X[_off__metile_v19_r19] : static_cast(0);\n float _metile_v20_r20 = _metile_v18_r20 ? X[_off__metile_v19_r20] : static_cast(0);\n float _metile_v20_r21 = _metile_v18_r21 ? X[_off__metile_v19_r21] : static_cast(0);\n float _metile_v20_r22 = _metile_v18_r22 ? X[_off__metile_v19_r22] : static_cast(0);\n float _metile_v20_r23 = _metile_v18_r23 ? X[_off__metile_v19_r23] : static_cast(0);\n float _metile_v20_r24 = _metile_v18_r24 ? X[_off__metile_v19_r24] : static_cast(0);\n float _metile_v20_r25 = _metile_v18_r25 ? X[_off__metile_v19_r25] : static_cast(0);\n float _metile_v20_r26 = _metile_v18_r26 ? X[_off__metile_v19_r26] : static_cast(0);\n float _metile_v20_r27 = _metile_v18_r27 ? X[_off__metile_v19_r27] : static_cast(0);\n float _metile_v20_r28 = _metile_v18_r28 ? X[_off__metile_v19_r28] : static_cast(0);\n float _metile_v20_r29 = _metile_v18_r29 ? X[_off__metile_v19_r29] : static_cast(0);\n float _metile_v20_r30 = _metile_v18_r30 ? X[_off__metile_v19_r30] : static_cast(0);\n float _metile_v20_r31 = _metile_v18_r31 ? X[_off__metile_v19_r31] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v21_r16 = static_cast(_metile_v20_r16);\n float _metile_v21_r17 = static_cast(_metile_v20_r17);\n float _metile_v21_r18 = static_cast(_metile_v20_r18);\n float _metile_v21_r19 = static_cast(_metile_v20_r19);\n float _metile_v21_r20 = static_cast(_metile_v20_r20);\n float _metile_v21_r21 = static_cast(_metile_v20_r21);\n float _metile_v21_r22 = static_cast(_metile_v20_r22);\n float _metile_v21_r23 = static_cast(_metile_v20_r23);\n float _metile_v21_r24 = static_cast(_metile_v20_r24);\n float _metile_v21_r25 = static_cast(_metile_v20_r25);\n float _metile_v21_r26 = static_cast(_metile_v20_r26);\n float _metile_v21_r27 = static_cast(_metile_v20_r27);\n float _metile_v21_r28 = static_cast(_metile_v20_r28);\n float _metile_v21_r29 = static_cast(_metile_v20_r29);\n float _metile_v21_r30 = static_cast(_metile_v20_r30);\n float _metile_v21_r31 = static_cast(_metile_v20_r31);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_v22_r16 = _metile_v21_r16 * _metile_v21_r16;\n float _metile_v22_r17 = _metile_v21_r17 * _metile_v21_r17;\n float _metile_v22_r18 = _metile_v21_r18 * _metile_v21_r18;\n float _metile_v22_r19 = _metile_v21_r19 * _metile_v21_r19;\n float _metile_v22_r20 = _metile_v21_r20 * _metile_v21_r20;\n float _metile_v22_r21 = _metile_v21_r21 * _metile_v21_r21;\n float _metile_v22_r22 = _metile_v21_r22 * _metile_v21_r22;\n float _metile_v22_r23 = _metile_v21_r23 * _metile_v21_r23;\n float _metile_v22_r24 = _metile_v21_r24 * _metile_v21_r24;\n float _metile_v22_r25 = _metile_v21_r25 * _metile_v21_r25;\n float _metile_v22_r26 = _metile_v21_r26 * _metile_v21_r26;\n float _metile_v22_r27 = _metile_v21_r27 * _metile_v21_r27;\n float _metile_v22_r28 = _metile_v21_r28 * _metile_v21_r28;\n float _metile_v22_r29 = _metile_v21_r29 * _metile_v21_r29;\n float _metile_v22_r30 = _metile_v21_r30 * _metile_v21_r30;\n float _metile_v22_r31 = _metile_v21_r31 * _metile_v21_r31;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_v22_r16 + _metile_v22_r17;\n float _metile_register_sum_________ = _metile_v22_r18 + _metile_v22_r19;\n float _metile_register_sum__________ = _metile_v22_r20 + _metile_v22_r21;\n float _metile_register_sum___________ = _metile_v22_r22 + _metile_v22_r23;\n float _metile_register_sum____________ = _metile_v22_r24 + _metile_v22_r25;\n float _metile_register_sum_____________ = _metile_v22_r26 + _metile_v22_r27;\n float _metile_register_sum______________ = _metile_v22_r28 + _metile_v22_r29;\n float _metile_register_sum_______________ = _metile_v22_r30 + _metile_v22_r31;\n float _metile_register_sum________________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________________ = _metile_register_sum____________ + _metile_register_sum_____________;\n float _metile_register_sum_______________________ = _metile_register_sum______________ + _metile_register_sum_______________;\n float _metile_register_sum________________________ = _metile_register_sum________________ + _metile_register_sum_________________;\n float _metile_register_sum_________________________ = _metile_register_sum__________________ + _metile_register_sum___________________;\n float _metile_register_sum__________________________ = _metile_register_sum____________________ + _metile_register_sum_____________________;\n float _metile_register_sum___________________________ = _metile_register_sum______________________ + _metile_register_sum_______________________;\n float _metile_register_sum____________________________ = _metile_register_sum________________________ + _metile_register_sum_________________________;\n float _metile_register_sum_____________________________ = _metile_register_sum__________________________ + _metile_register_sum___________________________;\n float _metile_register_sum______________________________ = _metile_register_sum____________________________ + _metile_register_sum_____________________________;\n float v23 = simd_sum(_metile_register_sum______________________________);\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v32_r16 = _metile_register_index________________ >= 0;\n bool _metile_v32_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v32_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v32_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v32_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v32_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v32_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v32_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v32_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v32_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v32_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v32_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v32_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v32_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v32_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v32_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v33_r8 = _metile_register_index________ < 1024;\n bool _metile_v33_r9 = _metile_register_index_________ < 1024;\n bool _metile_v33_r10 = _metile_register_index__________ < 1024;\n bool _metile_v33_r11 = _metile_register_index___________ < 1024;\n bool _metile_v33_r12 = _metile_register_index____________ < 1024;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v33_r14 = _metile_register_index______________ < 1024;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v33_r16 = _metile_register_index________________ < 1024;\n bool _metile_v33_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v33_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v33_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v33_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v33_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v33_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v33_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v33_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v33_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v33_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v33_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v33_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v33_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v33_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v33_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n bool _metile_v34_r16 = _metile_v32_r16 & _metile_v33_r16;\n bool _metile_v34_r17 = _metile_v32_r17 & _metile_v33_r17;\n bool _metile_v34_r18 = _metile_v32_r18 & _metile_v33_r18;\n bool _metile_v34_r19 = _metile_v32_r19 & _metile_v33_r19;\n bool _metile_v34_r20 = _metile_v32_r20 & _metile_v33_r20;\n bool _metile_v34_r21 = _metile_v32_r21 & _metile_v33_r21;\n bool _metile_v34_r22 = _metile_v32_r22 & _metile_v33_r22;\n bool _metile_v34_r23 = _metile_v32_r23 & _metile_v33_r23;\n bool _metile_v34_r24 = _metile_v32_r24 & _metile_v33_r24;\n bool _metile_v34_r25 = _metile_v32_r25 & _metile_v33_r25;\n bool _metile_v34_r26 = _metile_v32_r26 & _metile_v33_r26;\n bool _metile_v34_r27 = _metile_v32_r27 & _metile_v33_r27;\n bool _metile_v34_r28 = _metile_v32_r28 & _metile_v33_r28;\n bool _metile_v34_r29 = _metile_v32_r29 & _metile_v33_r29;\n bool _metile_v34_r30 = _metile_v32_r30 & _metile_v33_r30;\n bool _metile_v34_r31 = _metile_v32_r31 & _metile_v33_r31;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n float _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n float _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n float _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n float _metile_v36_r8 = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n float _metile_v36_r9 = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n float _metile_v36_r10 = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n float _metile_v36_r11 = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n float _metile_v36_r12 = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n float _metile_v36_r13 = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n float _metile_v36_r14 = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n float _metile_v36_r15 = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n float _metile_v36_r16 = _metile_v34_r16 ? W[_metile_register_index________________] : static_cast(0);\n float _metile_v36_r17 = _metile_v34_r17 ? W[_metile_register_index_________________] : static_cast(0);\n float _metile_v36_r18 = _metile_v34_r18 ? W[_metile_register_index__________________] : static_cast(0);\n float _metile_v36_r19 = _metile_v34_r19 ? W[_metile_register_index___________________] : static_cast(0);\n float _metile_v36_r20 = _metile_v34_r20 ? W[_metile_register_index____________________] : static_cast(0);\n float _metile_v36_r21 = _metile_v34_r21 ? W[_metile_register_index_____________________] : static_cast(0);\n float _metile_v36_r22 = _metile_v34_r22 ? W[_metile_register_index______________________] : static_cast(0);\n float _metile_v36_r23 = _metile_v34_r23 ? W[_metile_register_index_______________________] : static_cast(0);\n float _metile_v36_r24 = _metile_v34_r24 ? W[_metile_register_index________________________] : static_cast(0);\n float _metile_v36_r25 = _metile_v34_r25 ? W[_metile_register_index_________________________] : static_cast(0);\n float _metile_v36_r26 = _metile_v34_r26 ? W[_metile_register_index__________________________] : static_cast(0);\n float _metile_v36_r27 = _metile_v34_r27 ? W[_metile_register_index___________________________] : static_cast(0);\n float _metile_v36_r28 = _metile_v34_r28 ? W[_metile_register_index____________________________] : static_cast(0);\n float _metile_v36_r29 = _metile_v34_r29 ? W[_metile_register_index_____________________________] : static_cast(0);\n float _metile_v36_r30 = _metile_v34_r30 ? W[_metile_register_index______________________________] : static_cast(0);\n float _metile_v36_r31 = _metile_v34_r31 ? W[_metile_register_index_______________________________] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v37_r16 = static_cast(_metile_v36_r16);\n float _metile_v37_r17 = static_cast(_metile_v36_r17);\n float _metile_v37_r18 = static_cast(_metile_v36_r18);\n float _metile_v37_r19 = static_cast(_metile_v36_r19);\n float _metile_v37_r20 = static_cast(_metile_v36_r20);\n float _metile_v37_r21 = static_cast(_metile_v36_r21);\n float _metile_v37_r22 = static_cast(_metile_v36_r22);\n float _metile_v37_r23 = static_cast(_metile_v36_r23);\n float _metile_v37_r24 = static_cast(_metile_v36_r24);\n float _metile_v37_r25 = static_cast(_metile_v36_r25);\n float _metile_v37_r26 = static_cast(_metile_v36_r26);\n float _metile_v37_r27 = static_cast(_metile_v36_r27);\n float _metile_v37_r28 = static_cast(_metile_v36_r28);\n float _metile_v37_r29 = static_cast(_metile_v36_r29);\n float _metile_v37_r30 = static_cast(_metile_v36_r30);\n float _metile_v37_r31 = static_cast(_metile_v36_r31);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v38_r16 = _metile_v21_r16 * v29;\n float _metile_v38_r17 = _metile_v21_r17 * v29;\n float _metile_v38_r18 = _metile_v21_r18 * v29;\n float _metile_v38_r19 = _metile_v21_r19 * v29;\n float _metile_v38_r20 = _metile_v21_r20 * v29;\n float _metile_v38_r21 = _metile_v21_r21 * v29;\n float _metile_v38_r22 = _metile_v21_r22 * v29;\n float _metile_v38_r23 = _metile_v21_r23 * v29;\n float _metile_v38_r24 = _metile_v21_r24 * v29;\n float _metile_v38_r25 = _metile_v21_r25 * v29;\n float _metile_v38_r26 = _metile_v21_r26 * v29;\n float _metile_v38_r27 = _metile_v21_r27 * v29;\n float _metile_v38_r28 = _metile_v21_r28 * v29;\n float _metile_v38_r29 = _metile_v21_r29 * v29;\n float _metile_v38_r30 = _metile_v21_r30 * v29;\n float _metile_v38_r31 = _metile_v21_r31 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n float _metile_v39_r16 = _metile_v38_r16 * _metile_v37_r16;\n float _metile_v39_r17 = _metile_v38_r17 * _metile_v37_r17;\n float _metile_v39_r18 = _metile_v38_r18 * _metile_v37_r18;\n float _metile_v39_r19 = _metile_v38_r19 * _metile_v37_r19;\n float _metile_v39_r20 = _metile_v38_r20 * _metile_v37_r20;\n float _metile_v39_r21 = _metile_v38_r21 * _metile_v37_r21;\n float _metile_v39_r22 = _metile_v38_r22 * _metile_v37_r22;\n float _metile_v39_r23 = _metile_v38_r23 * _metile_v37_r23;\n float _metile_v39_r24 = _metile_v38_r24 * _metile_v37_r24;\n float _metile_v39_r25 = _metile_v38_r25 * _metile_v37_r25;\n float _metile_v39_r26 = _metile_v38_r26 * _metile_v37_r26;\n float _metile_v39_r27 = _metile_v38_r27 * _metile_v37_r27;\n float _metile_v39_r28 = _metile_v38_r28 * _metile_v37_r28;\n float _metile_v39_r29 = _metile_v38_r29 * _metile_v37_r29;\n float _metile_v39_r30 = _metile_v38_r30 * _metile_v37_r30;\n float _metile_v39_r31 = _metile_v38_r31 * _metile_v37_r31;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v41_r16 = _metile_register_index________________ >= 0;\n bool _metile_v41_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v41_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v41_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v41_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v41_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v41_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v41_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v41_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v41_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v41_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v41_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v41_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v41_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v41_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v41_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v42_r8 = _metile_register_index________ < 1024;\n bool _metile_v42_r9 = _metile_register_index_________ < 1024;\n bool _metile_v42_r10 = _metile_register_index__________ < 1024;\n bool _metile_v42_r11 = _metile_register_index___________ < 1024;\n bool _metile_v42_r12 = _metile_register_index____________ < 1024;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v42_r14 = _metile_register_index______________ < 1024;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v42_r16 = _metile_register_index________________ < 1024;\n bool _metile_v42_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v42_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v42_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v42_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v42_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v42_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v42_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v42_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v42_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v42_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v42_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v42_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v42_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v42_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v42_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n bool _metile_v43_r16 = _metile_v41_r16 & _metile_v42_r16;\n bool _metile_v43_r17 = _metile_v41_r17 & _metile_v42_r17;\n bool _metile_v43_r18 = _metile_v41_r18 & _metile_v42_r18;\n bool _metile_v43_r19 = _metile_v41_r19 & _metile_v42_r19;\n bool _metile_v43_r20 = _metile_v41_r20 & _metile_v42_r20;\n bool _metile_v43_r21 = _metile_v41_r21 & _metile_v42_r21;\n bool _metile_v43_r22 = _metile_v41_r22 & _metile_v42_r22;\n bool _metile_v43_r23 = _metile_v41_r23 & _metile_v42_r23;\n bool _metile_v43_r24 = _metile_v41_r24 & _metile_v42_r24;\n bool _metile_v43_r25 = _metile_v41_r25 & _metile_v42_r25;\n bool _metile_v43_r26 = _metile_v41_r26 & _metile_v42_r26;\n bool _metile_v43_r27 = _metile_v41_r27 & _metile_v42_r27;\n bool _metile_v43_r28 = _metile_v41_r28 & _metile_v42_r28;\n bool _metile_v43_r29 = _metile_v41_r29 & _metile_v42_r29;\n bool _metile_v43_r30 = _metile_v41_r30 & _metile_v42_r30;\n bool _metile_v43_r31 = _metile_v41_r31 & _metile_v42_r31;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n int _off__metile_v44_r16 = v9 + _metile_register_index________________;\n int _off__metile_v44_r17 = v9 + _metile_register_index_________________;\n int _off__metile_v44_r18 = v9 + _metile_register_index__________________;\n int _off__metile_v44_r19 = v9 + _metile_register_index___________________;\n int _off__metile_v44_r20 = v9 + _metile_register_index____________________;\n int _off__metile_v44_r21 = v9 + _metile_register_index_____________________;\n int _off__metile_v44_r22 = v9 + _metile_register_index______________________;\n int _off__metile_v44_r23 = v9 + _metile_register_index_______________________;\n int _off__metile_v44_r24 = v9 + _metile_register_index________________________;\n int _off__metile_v44_r25 = v9 + _metile_register_index_________________________;\n int _off__metile_v44_r26 = v9 + _metile_register_index__________________________;\n int _off__metile_v44_r27 = v9 + _metile_register_index___________________________;\n int _off__metile_v44_r28 = v9 + _metile_register_index____________________________;\n int _off__metile_v44_r29 = v9 + _metile_register_index_____________________________;\n int _off__metile_v44_r30 = v9 + _metile_register_index______________________________;\n int _off__metile_v44_r31 = v9 + _metile_register_index_______________________________;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = _metile_v39_r8; }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = _metile_v39_r9; }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = _metile_v39_r10; }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = _metile_v39_r11; }\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = _metile_v39_r12; }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = _metile_v39_r13; }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = _metile_v39_r14; }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = _metile_v39_r15; }\n if (_metile_v43_r16) { Out[_off__metile_v44_r16] = _metile_v39_r16; }\n if (_metile_v43_r17) { Out[_off__metile_v44_r17] = _metile_v39_r17; }\n if (_metile_v43_r18) { Out[_off__metile_v44_r18] = _metile_v39_r18; }\n if (_metile_v43_r19) { Out[_off__metile_v44_r19] = _metile_v39_r19; }\n if (_metile_v43_r20) { Out[_off__metile_v44_r20] = _metile_v39_r20; }\n if (_metile_v43_r21) { Out[_off__metile_v44_r21] = _metile_v39_r21; }\n if (_metile_v43_r22) { Out[_off__metile_v44_r22] = _metile_v39_r22; }\n if (_metile_v43_r23) { Out[_off__metile_v44_r23] = _metile_v39_r23; }\n if (_metile_v43_r24) { Out[_off__metile_v44_r24] = _metile_v39_r24; }\n if (_metile_v43_r25) { Out[_off__metile_v44_r25] = _metile_v39_r25; }\n if (_metile_v43_r26) { Out[_off__metile_v44_r26] = _metile_v39_r26; }\n if (_metile_v43_r27) { Out[_off__metile_v44_r27] = _metile_v39_r27; }\n if (_metile_v43_r28) { Out[_off__metile_v44_r28] = _metile_v39_r28; }\n if (_metile_v43_r29) { Out[_off__metile_v44_r29] = _metile_v39_r29; }\n if (_metile_v43_r30) { Out[_off__metile_v44_r30] = _metile_v39_r30; }\n if (_metile_v43_r31) { Out[_off__metile_v44_r31] = _metile_v39_r31; }\n}", "source_sha256": "ad4bf6c168b8be3158fdb141b4692d160c0a3ff22ae8336b2fe017e3812a192f", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 32, 1, 1 ], "is_gemm": false, "prefer_ordered": false, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 32, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 32 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 32, "threads": 32, "scratch": null, "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 573, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.917, "control": 202.916, "speedup": 1.015001225508586 }, "gpu_us": { "candidate": 2.2082822397351265, "control": 1.7082784324884415, "speedup": 0.7735779429595656 } } }, { "frozen_register4": { "pairs": 600, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.375, "control": 199.29149999999998, "speedup": 1.0046200378071832 }, "gpu_us": { "candidate": 2.1249870769679546, "control": 1.6249832697212696, "speedup": 0.7647026597638809 } } }, { "frozen_register4": { "pairs": 627, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.75, "control": 196.042, "speedup": 0.9863748427672956 }, "gpu_us": { "candidate": 2.1249870769679546, "control": 1.6249832697212696, "speedup": 0.7647026597638809 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0019286529750369, "round_speedups": [ 1.015001225508586, 1.0046200378071832, 0.9863748427672956 ], "candidate": 199.01291808101348, "control": 199.39674493754114 }, "gpu_us": { "speedup": 0.7676497153712811, "round_speedups": [ 0.7735779429595656, 0.7647026597638809, 0.7647026597638809 ], "candidate": 2.152397052774871, "control": 1.652286984928614 } } } }, { "name": "float32_1x1024", "dtype": "float32", "batches": 1, "width": 1024, "status": "measured", "variant": { "name": "register32_blocked4", "elements_per_thread": 32, "layout": "blocked4" }, "input_sha256": "ddb1751346f69e81810fa3e5e4fc2fa3d8214ffaace8e689775a59ca252f7042", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 4.76837158203125e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 31;\n int _metile_register_index = int((((_metile_bounded_thread >> 5) & 1u) << 0) | (((_metile_bounded_thread >> 6) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 7) & 1u) << 7) | (((_metile_bounded_thread >> 8) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 32;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 5) & 1u) << 0) | (((_metile_register_packed_ >> 6) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 7) & 1u) << 7) | (((_metile_register_packed_ >> 8) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 64;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 5) & 1u) << 0) | (((_metile_register_packed__ >> 6) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 7) & 1u) << 7) | (((_metile_register_packed__ >> 8) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 96;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 5) & 1u) << 0) | (((_metile_register_packed___ >> 6) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 7) & 1u) << 7) | (((_metile_register_packed___ >> 8) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 128;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 5) & 1u) << 0) | (((_metile_register_packed____ >> 6) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 7) & 1u) << 7) | (((_metile_register_packed____ >> 8) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 160;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 5) & 1u) << 0) | (((_metile_register_packed_____ >> 6) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 7) & 1u) << 7) | (((_metile_register_packed_____ >> 8) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 192;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 5) & 1u) << 0) | (((_metile_register_packed______ >> 6) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 7) & 1u) << 7) | (((_metile_register_packed______ >> 8) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 224;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 5) & 1u) << 0) | (((_metile_register_packed_______ >> 6) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 7) & 1u) << 7) | (((_metile_register_packed_______ >> 8) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n int _metile_register_packed________ = _metile_bounded_thread + 256;\n int _metile_register_index________ = int((((_metile_register_packed________ >> 5) & 1u) << 0) | (((_metile_register_packed________ >> 6) & 1u) << 1) | (((_metile_register_packed________ >> 0) & 1u) << 2) | (((_metile_register_packed________ >> 1) & 1u) << 3) | (((_metile_register_packed________ >> 2) & 1u) << 4) | (((_metile_register_packed________ >> 3) & 1u) << 5) | (((_metile_register_packed________ >> 4) & 1u) << 6) | (((_metile_register_packed________ >> 7) & 1u) << 7) | (((_metile_register_packed________ >> 8) & 1u) << 8) | (((_metile_register_packed________ >> 9) & 1u) << 9));\n int _metile_register_packed_________ = _metile_bounded_thread + 288;\n int _metile_register_index_________ = int((((_metile_register_packed_________ >> 5) & 1u) << 0) | (((_metile_register_packed_________ >> 6) & 1u) << 1) | (((_metile_register_packed_________ >> 0) & 1u) << 2) | (((_metile_register_packed_________ >> 1) & 1u) << 3) | (((_metile_register_packed_________ >> 2) & 1u) << 4) | (((_metile_register_packed_________ >> 3) & 1u) << 5) | (((_metile_register_packed_________ >> 4) & 1u) << 6) | (((_metile_register_packed_________ >> 7) & 1u) << 7) | (((_metile_register_packed_________ >> 8) & 1u) << 8) | (((_metile_register_packed_________ >> 9) & 1u) << 9));\n int _metile_register_packed__________ = _metile_bounded_thread + 320;\n int _metile_register_index__________ = int((((_metile_register_packed__________ >> 5) & 1u) << 0) | (((_metile_register_packed__________ >> 6) & 1u) << 1) | (((_metile_register_packed__________ >> 0) & 1u) << 2) | (((_metile_register_packed__________ >> 1) & 1u) << 3) | (((_metile_register_packed__________ >> 2) & 1u) << 4) | (((_metile_register_packed__________ >> 3) & 1u) << 5) | (((_metile_register_packed__________ >> 4) & 1u) << 6) | (((_metile_register_packed__________ >> 7) & 1u) << 7) | (((_metile_register_packed__________ >> 8) & 1u) << 8) | (((_metile_register_packed__________ >> 9) & 1u) << 9));\n int _metile_register_packed___________ = _metile_bounded_thread + 352;\n int _metile_register_index___________ = int((((_metile_register_packed___________ >> 5) & 1u) << 0) | (((_metile_register_packed___________ >> 6) & 1u) << 1) | (((_metile_register_packed___________ >> 0) & 1u) << 2) | (((_metile_register_packed___________ >> 1) & 1u) << 3) | (((_metile_register_packed___________ >> 2) & 1u) << 4) | (((_metile_register_packed___________ >> 3) & 1u) << 5) | (((_metile_register_packed___________ >> 4) & 1u) << 6) | (((_metile_register_packed___________ >> 7) & 1u) << 7) | (((_metile_register_packed___________ >> 8) & 1u) << 8) | (((_metile_register_packed___________ >> 9) & 1u) << 9));\n int _metile_register_packed____________ = _metile_bounded_thread + 384;\n int _metile_register_index____________ = int((((_metile_register_packed____________ >> 5) & 1u) << 0) | (((_metile_register_packed____________ >> 6) & 1u) << 1) | (((_metile_register_packed____________ >> 0) & 1u) << 2) | (((_metile_register_packed____________ >> 1) & 1u) << 3) | (((_metile_register_packed____________ >> 2) & 1u) << 4) | (((_metile_register_packed____________ >> 3) & 1u) << 5) | (((_metile_register_packed____________ >> 4) & 1u) << 6) | (((_metile_register_packed____________ >> 7) & 1u) << 7) | (((_metile_register_packed____________ >> 8) & 1u) << 8) | (((_metile_register_packed____________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________ = _metile_bounded_thread + 416;\n int _metile_register_index_____________ = int((((_metile_register_packed_____________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________ >> 9) & 1u) << 9));\n int _metile_register_packed______________ = _metile_bounded_thread + 448;\n int _metile_register_index______________ = int((((_metile_register_packed______________ >> 5) & 1u) << 0) | (((_metile_register_packed______________ >> 6) & 1u) << 1) | (((_metile_register_packed______________ >> 0) & 1u) << 2) | (((_metile_register_packed______________ >> 1) & 1u) << 3) | (((_metile_register_packed______________ >> 2) & 1u) << 4) | (((_metile_register_packed______________ >> 3) & 1u) << 5) | (((_metile_register_packed______________ >> 4) & 1u) << 6) | (((_metile_register_packed______________ >> 7) & 1u) << 7) | (((_metile_register_packed______________ >> 8) & 1u) << 8) | (((_metile_register_packed______________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________ = _metile_bounded_thread + 480;\n int _metile_register_index_______________ = int((((_metile_register_packed_______________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________ >> 9) & 1u) << 9));\n int _metile_register_packed________________ = _metile_bounded_thread + 512;\n int _metile_register_index________________ = int((((_metile_register_packed________________ >> 5) & 1u) << 0) | (((_metile_register_packed________________ >> 6) & 1u) << 1) | (((_metile_register_packed________________ >> 0) & 1u) << 2) | (((_metile_register_packed________________ >> 1) & 1u) << 3) | (((_metile_register_packed________________ >> 2) & 1u) << 4) | (((_metile_register_packed________________ >> 3) & 1u) << 5) | (((_metile_register_packed________________ >> 4) & 1u) << 6) | (((_metile_register_packed________________ >> 7) & 1u) << 7) | (((_metile_register_packed________________ >> 8) & 1u) << 8) | (((_metile_register_packed________________ >> 9) & 1u) << 9));\n int _metile_register_packed_________________ = _metile_bounded_thread + 544;\n int _metile_register_index_________________ = int((((_metile_register_packed_________________ >> 5) & 1u) << 0) | (((_metile_register_packed_________________ >> 6) & 1u) << 1) | (((_metile_register_packed_________________ >> 0) & 1u) << 2) | (((_metile_register_packed_________________ >> 1) & 1u) << 3) | (((_metile_register_packed_________________ >> 2) & 1u) << 4) | (((_metile_register_packed_________________ >> 3) & 1u) << 5) | (((_metile_register_packed_________________ >> 4) & 1u) << 6) | (((_metile_register_packed_________________ >> 7) & 1u) << 7) | (((_metile_register_packed_________________ >> 8) & 1u) << 8) | (((_metile_register_packed_________________ >> 9) & 1u) << 9));\n int _metile_register_packed__________________ = _metile_bounded_thread + 576;\n int _metile_register_index__________________ = int((((_metile_register_packed__________________ >> 5) & 1u) << 0) | (((_metile_register_packed__________________ >> 6) & 1u) << 1) | (((_metile_register_packed__________________ >> 0) & 1u) << 2) | (((_metile_register_packed__________________ >> 1) & 1u) << 3) | (((_metile_register_packed__________________ >> 2) & 1u) << 4) | (((_metile_register_packed__________________ >> 3) & 1u) << 5) | (((_metile_register_packed__________________ >> 4) & 1u) << 6) | (((_metile_register_packed__________________ >> 7) & 1u) << 7) | (((_metile_register_packed__________________ >> 8) & 1u) << 8) | (((_metile_register_packed__________________ >> 9) & 1u) << 9));\n int _metile_register_packed___________________ = _metile_bounded_thread + 608;\n int _metile_register_index___________________ = int((((_metile_register_packed___________________ >> 5) & 1u) << 0) | (((_metile_register_packed___________________ >> 6) & 1u) << 1) | (((_metile_register_packed___________________ >> 0) & 1u) << 2) | (((_metile_register_packed___________________ >> 1) & 1u) << 3) | (((_metile_register_packed___________________ >> 2) & 1u) << 4) | (((_metile_register_packed___________________ >> 3) & 1u) << 5) | (((_metile_register_packed___________________ >> 4) & 1u) << 6) | (((_metile_register_packed___________________ >> 7) & 1u) << 7) | (((_metile_register_packed___________________ >> 8) & 1u) << 8) | (((_metile_register_packed___________________ >> 9) & 1u) << 9));\n int _metile_register_packed____________________ = _metile_bounded_thread + 640;\n int _metile_register_index____________________ = int((((_metile_register_packed____________________ >> 5) & 1u) << 0) | (((_metile_register_packed____________________ >> 6) & 1u) << 1) | (((_metile_register_packed____________________ >> 0) & 1u) << 2) | (((_metile_register_packed____________________ >> 1) & 1u) << 3) | (((_metile_register_packed____________________ >> 2) & 1u) << 4) | (((_metile_register_packed____________________ >> 3) & 1u) << 5) | (((_metile_register_packed____________________ >> 4) & 1u) << 6) | (((_metile_register_packed____________________ >> 7) & 1u) << 7) | (((_metile_register_packed____________________ >> 8) & 1u) << 8) | (((_metile_register_packed____________________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________________ = _metile_bounded_thread + 672;\n int _metile_register_index_____________________ = int((((_metile_register_packed_____________________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________________ >> 9) & 1u) << 9));\n int _metile_register_packed______________________ = _metile_bounded_thread + 704;\n int _metile_register_index______________________ = int((((_metile_register_packed______________________ >> 5) & 1u) << 0) | (((_metile_register_packed______________________ >> 6) & 1u) << 1) | (((_metile_register_packed______________________ >> 0) & 1u) << 2) | (((_metile_register_packed______________________ >> 1) & 1u) << 3) | (((_metile_register_packed______________________ >> 2) & 1u) << 4) | (((_metile_register_packed______________________ >> 3) & 1u) << 5) | (((_metile_register_packed______________________ >> 4) & 1u) << 6) | (((_metile_register_packed______________________ >> 7) & 1u) << 7) | (((_metile_register_packed______________________ >> 8) & 1u) << 8) | (((_metile_register_packed______________________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________________ = _metile_bounded_thread + 736;\n int _metile_register_index_______________________ = int((((_metile_register_packed_______________________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________________ >> 9) & 1u) << 9));\n int _metile_register_packed________________________ = _metile_bounded_thread + 768;\n int _metile_register_index________________________ = int((((_metile_register_packed________________________ >> 5) & 1u) << 0) | (((_metile_register_packed________________________ >> 6) & 1u) << 1) | (((_metile_register_packed________________________ >> 0) & 1u) << 2) | (((_metile_register_packed________________________ >> 1) & 1u) << 3) | (((_metile_register_packed________________________ >> 2) & 1u) << 4) | (((_metile_register_packed________________________ >> 3) & 1u) << 5) | (((_metile_register_packed________________________ >> 4) & 1u) << 6) | (((_metile_register_packed________________________ >> 7) & 1u) << 7) | (((_metile_register_packed________________________ >> 8) & 1u) << 8) | (((_metile_register_packed________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_________________________ = _metile_bounded_thread + 800;\n int _metile_register_index_________________________ = int((((_metile_register_packed_________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_________________________ >> 9) & 1u) << 9));\n int _metile_register_packed__________________________ = _metile_bounded_thread + 832;\n int _metile_register_index__________________________ = int((((_metile_register_packed__________________________ >> 5) & 1u) << 0) | (((_metile_register_packed__________________________ >> 6) & 1u) << 1) | (((_metile_register_packed__________________________ >> 0) & 1u) << 2) | (((_metile_register_packed__________________________ >> 1) & 1u) << 3) | (((_metile_register_packed__________________________ >> 2) & 1u) << 4) | (((_metile_register_packed__________________________ >> 3) & 1u) << 5) | (((_metile_register_packed__________________________ >> 4) & 1u) << 6) | (((_metile_register_packed__________________________ >> 7) & 1u) << 7) | (((_metile_register_packed__________________________ >> 8) & 1u) << 8) | (((_metile_register_packed__________________________ >> 9) & 1u) << 9));\n int _metile_register_packed___________________________ = _metile_bounded_thread + 864;\n int _metile_register_index___________________________ = int((((_metile_register_packed___________________________ >> 5) & 1u) << 0) | (((_metile_register_packed___________________________ >> 6) & 1u) << 1) | (((_metile_register_packed___________________________ >> 0) & 1u) << 2) | (((_metile_register_packed___________________________ >> 1) & 1u) << 3) | (((_metile_register_packed___________________________ >> 2) & 1u) << 4) | (((_metile_register_packed___________________________ >> 3) & 1u) << 5) | (((_metile_register_packed___________________________ >> 4) & 1u) << 6) | (((_metile_register_packed___________________________ >> 7) & 1u) << 7) | (((_metile_register_packed___________________________ >> 8) & 1u) << 8) | (((_metile_register_packed___________________________ >> 9) & 1u) << 9));\n int _metile_register_packed____________________________ = _metile_bounded_thread + 896;\n int _metile_register_index____________________________ = int((((_metile_register_packed____________________________ >> 5) & 1u) << 0) | (((_metile_register_packed____________________________ >> 6) & 1u) << 1) | (((_metile_register_packed____________________________ >> 0) & 1u) << 2) | (((_metile_register_packed____________________________ >> 1) & 1u) << 3) | (((_metile_register_packed____________________________ >> 2) & 1u) << 4) | (((_metile_register_packed____________________________ >> 3) & 1u) << 5) | (((_metile_register_packed____________________________ >> 4) & 1u) << 6) | (((_metile_register_packed____________________________ >> 7) & 1u) << 7) | (((_metile_register_packed____________________________ >> 8) & 1u) << 8) | (((_metile_register_packed____________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________________________ = _metile_bounded_thread + 928;\n int _metile_register_index_____________________________ = int((((_metile_register_packed_____________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________________________ >> 9) & 1u) << 9));\n int _metile_register_packed______________________________ = _metile_bounded_thread + 960;\n int _metile_register_index______________________________ = int((((_metile_register_packed______________________________ >> 5) & 1u) << 0) | (((_metile_register_packed______________________________ >> 6) & 1u) << 1) | (((_metile_register_packed______________________________ >> 0) & 1u) << 2) | (((_metile_register_packed______________________________ >> 1) & 1u) << 3) | (((_metile_register_packed______________________________ >> 2) & 1u) << 4) | (((_metile_register_packed______________________________ >> 3) & 1u) << 5) | (((_metile_register_packed______________________________ >> 4) & 1u) << 6) | (((_metile_register_packed______________________________ >> 7) & 1u) << 7) | (((_metile_register_packed______________________________ >> 8) & 1u) << 8) | (((_metile_register_packed______________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________________________ = _metile_bounded_thread + 992;\n int _metile_register_index_______________________________ = int((((_metile_register_packed_______________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________________________ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v16_r16 = _metile_register_index________________ >= 0;\n bool _metile_v16_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v16_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v16_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v16_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v16_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v16_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v16_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v16_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v16_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v16_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v16_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v16_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v16_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v16_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v16_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v17_r8 = _metile_register_index________ < 1024;\n bool _metile_v17_r9 = _metile_register_index_________ < 1024;\n bool _metile_v17_r10 = _metile_register_index__________ < 1024;\n bool _metile_v17_r11 = _metile_register_index___________ < 1024;\n bool _metile_v17_r12 = _metile_register_index____________ < 1024;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v17_r14 = _metile_register_index______________ < 1024;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v17_r16 = _metile_register_index________________ < 1024;\n bool _metile_v17_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v17_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v17_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v17_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v17_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v17_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v17_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v17_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v17_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v17_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v17_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v17_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v17_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v17_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v17_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n bool _metile_v18_r16 = _metile_v16_r16 & _metile_v17_r16;\n bool _metile_v18_r17 = _metile_v16_r17 & _metile_v17_r17;\n bool _metile_v18_r18 = _metile_v16_r18 & _metile_v17_r18;\n bool _metile_v18_r19 = _metile_v16_r19 & _metile_v17_r19;\n bool _metile_v18_r20 = _metile_v16_r20 & _metile_v17_r20;\n bool _metile_v18_r21 = _metile_v16_r21 & _metile_v17_r21;\n bool _metile_v18_r22 = _metile_v16_r22 & _metile_v17_r22;\n bool _metile_v18_r23 = _metile_v16_r23 & _metile_v17_r23;\n bool _metile_v18_r24 = _metile_v16_r24 & _metile_v17_r24;\n bool _metile_v18_r25 = _metile_v16_r25 & _metile_v17_r25;\n bool _metile_v18_r26 = _metile_v16_r26 & _metile_v17_r26;\n bool _metile_v18_r27 = _metile_v16_r27 & _metile_v17_r27;\n bool _metile_v18_r28 = _metile_v16_r28 & _metile_v17_r28;\n bool _metile_v18_r29 = _metile_v16_r29 & _metile_v17_r29;\n bool _metile_v18_r30 = _metile_v16_r30 & _metile_v17_r30;\n bool _metile_v18_r31 = _metile_v16_r31 & _metile_v17_r31;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n int _off__metile_v19_r16 = v2 + _metile_register_index________________;\n int _off__metile_v19_r17 = v2 + _metile_register_index_________________;\n int _off__metile_v19_r18 = v2 + _metile_register_index__________________;\n int _off__metile_v19_r19 = v2 + _metile_register_index___________________;\n int _off__metile_v19_r20 = v2 + _metile_register_index____________________;\n int _off__metile_v19_r21 = v2 + _metile_register_index_____________________;\n int _off__metile_v19_r22 = v2 + _metile_register_index______________________;\n int _off__metile_v19_r23 = v2 + _metile_register_index_______________________;\n int _off__metile_v19_r24 = v2 + _metile_register_index________________________;\n int _off__metile_v19_r25 = v2 + _metile_register_index_________________________;\n int _off__metile_v19_r26 = v2 + _metile_register_index__________________________;\n int _off__metile_v19_r27 = v2 + _metile_register_index___________________________;\n int _off__metile_v19_r28 = v2 + _metile_register_index____________________________;\n int _off__metile_v19_r29 = v2 + _metile_register_index_____________________________;\n int _off__metile_v19_r30 = v2 + _metile_register_index______________________________;\n int _off__metile_v19_r31 = v2 + _metile_register_index_______________________________;\n float4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = float4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n float _metile_v20_r0 = _metile_vector_load[0];\n float _metile_v20_r1 = _metile_vector_load[1];\n float _metile_v20_r2 = _metile_vector_load[2];\n float _metile_v20_r3 = _metile_vector_load[3];\n float4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = float4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n float _metile_v20_r4 = _metile_vector_load_[0];\n float _metile_v20_r5 = _metile_vector_load_[1];\n float _metile_v20_r6 = _metile_vector_load_[2];\n float _metile_v20_r7 = _metile_vector_load_[3];\n float4 _metile_vector_load__;\n if ((_metile_v18_r8) && (_metile_v18_r9) && (_metile_v18_r10) && (_metile_v18_r11) && (long(_off__metile_v19_r9) == long(_off__metile_v19_r8) + 1) && (long(_off__metile_v19_r10) == long(_off__metile_v19_r8) + 2) && (long(_off__metile_v19_r11) == long(_off__metile_v19_r8) + 3)) {\n _metile_vector_load__ = float4(*reinterpret_cast(X + _off__metile_v19_r8));\n } else {\n _metile_vector_load__[0] = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n _metile_vector_load__[1] = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n _metile_vector_load__[2] = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n _metile_vector_load__[3] = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n }\n float _metile_v20_r8 = _metile_vector_load__[0];\n float _metile_v20_r9 = _metile_vector_load__[1];\n float _metile_v20_r10 = _metile_vector_load__[2];\n float _metile_v20_r11 = _metile_vector_load__[3];\n float4 _metile_vector_load___;\n if ((_metile_v18_r12) && (_metile_v18_r13) && (_metile_v18_r14) && (_metile_v18_r15) && (long(_off__metile_v19_r13) == long(_off__metile_v19_r12) + 1) && (long(_off__metile_v19_r14) == long(_off__metile_v19_r12) + 2) && (long(_off__metile_v19_r15) == long(_off__metile_v19_r12) + 3)) {\n _metile_vector_load___ = float4(*reinterpret_cast(X + _off__metile_v19_r12));\n } else {\n _metile_vector_load___[0] = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n _metile_vector_load___[1] = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n _metile_vector_load___[2] = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n _metile_vector_load___[3] = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n }\n float _metile_v20_r12 = _metile_vector_load___[0];\n float _metile_v20_r13 = _metile_vector_load___[1];\n float _metile_v20_r14 = _metile_vector_load___[2];\n float _metile_v20_r15 = _metile_vector_load___[3];\n float4 _metile_vector_load____;\n if ((_metile_v18_r16) && (_metile_v18_r17) && (_metile_v18_r18) && (_metile_v18_r19) && (long(_off__metile_v19_r17) == long(_off__metile_v19_r16) + 1) && (long(_off__metile_v19_r18) == long(_off__metile_v19_r16) + 2) && (long(_off__metile_v19_r19) == long(_off__metile_v19_r16) + 3)) {\n _metile_vector_load____ = float4(*reinterpret_cast(X + _off__metile_v19_r16));\n } else {\n _metile_vector_load____[0] = _metile_v18_r16 ? X[_off__metile_v19_r16] : static_cast(0);\n _metile_vector_load____[1] = _metile_v18_r17 ? X[_off__metile_v19_r17] : static_cast(0);\n _metile_vector_load____[2] = _metile_v18_r18 ? X[_off__metile_v19_r18] : static_cast(0);\n _metile_vector_load____[3] = _metile_v18_r19 ? X[_off__metile_v19_r19] : static_cast(0);\n }\n float _metile_v20_r16 = _metile_vector_load____[0];\n float _metile_v20_r17 = _metile_vector_load____[1];\n float _metile_v20_r18 = _metile_vector_load____[2];\n float _metile_v20_r19 = _metile_vector_load____[3];\n float4 _metile_vector_load_____;\n if ((_metile_v18_r20) && (_metile_v18_r21) && (_metile_v18_r22) && (_metile_v18_r23) && (long(_off__metile_v19_r21) == long(_off__metile_v19_r20) + 1) && (long(_off__metile_v19_r22) == long(_off__metile_v19_r20) + 2) && (long(_off__metile_v19_r23) == long(_off__metile_v19_r20) + 3)) {\n _metile_vector_load_____ = float4(*reinterpret_cast(X + _off__metile_v19_r20));\n } else {\n _metile_vector_load_____[0] = _metile_v18_r20 ? X[_off__metile_v19_r20] : static_cast(0);\n _metile_vector_load_____[1] = _metile_v18_r21 ? X[_off__metile_v19_r21] : static_cast(0);\n _metile_vector_load_____[2] = _metile_v18_r22 ? X[_off__metile_v19_r22] : static_cast(0);\n _metile_vector_load_____[3] = _metile_v18_r23 ? X[_off__metile_v19_r23] : static_cast(0);\n }\n float _metile_v20_r20 = _metile_vector_load_____[0];\n float _metile_v20_r21 = _metile_vector_load_____[1];\n float _metile_v20_r22 = _metile_vector_load_____[2];\n float _metile_v20_r23 = _metile_vector_load_____[3];\n float4 _metile_vector_load______;\n if ((_metile_v18_r24) && (_metile_v18_r25) && (_metile_v18_r26) && (_metile_v18_r27) && (long(_off__metile_v19_r25) == long(_off__metile_v19_r24) + 1) && (long(_off__metile_v19_r26) == long(_off__metile_v19_r24) + 2) && (long(_off__metile_v19_r27) == long(_off__metile_v19_r24) + 3)) {\n _metile_vector_load______ = float4(*reinterpret_cast(X + _off__metile_v19_r24));\n } else {\n _metile_vector_load______[0] = _metile_v18_r24 ? X[_off__metile_v19_r24] : static_cast(0);\n _metile_vector_load______[1] = _metile_v18_r25 ? X[_off__metile_v19_r25] : static_cast(0);\n _metile_vector_load______[2] = _metile_v18_r26 ? X[_off__metile_v19_r26] : static_cast(0);\n _metile_vector_load______[3] = _metile_v18_r27 ? X[_off__metile_v19_r27] : static_cast(0);\n }\n float _metile_v20_r24 = _metile_vector_load______[0];\n float _metile_v20_r25 = _metile_vector_load______[1];\n float _metile_v20_r26 = _metile_vector_load______[2];\n float _metile_v20_r27 = _metile_vector_load______[3];\n float4 _metile_vector_load_______;\n if ((_metile_v18_r28) && (_metile_v18_r29) && (_metile_v18_r30) && (_metile_v18_r31) && (long(_off__metile_v19_r29) == long(_off__metile_v19_r28) + 1) && (long(_off__metile_v19_r30) == long(_off__metile_v19_r28) + 2) && (long(_off__metile_v19_r31) == long(_off__metile_v19_r28) + 3)) {\n _metile_vector_load_______ = float4(*reinterpret_cast(X + _off__metile_v19_r28));\n } else {\n _metile_vector_load_______[0] = _metile_v18_r28 ? X[_off__metile_v19_r28] : static_cast(0);\n _metile_vector_load_______[1] = _metile_v18_r29 ? X[_off__metile_v19_r29] : static_cast(0);\n _metile_vector_load_______[2] = _metile_v18_r30 ? X[_off__metile_v19_r30] : static_cast(0);\n _metile_vector_load_______[3] = _metile_v18_r31 ? X[_off__metile_v19_r31] : static_cast(0);\n }\n float _metile_v20_r28 = _metile_vector_load_______[0];\n float _metile_v20_r29 = _metile_vector_load_______[1];\n float _metile_v20_r30 = _metile_vector_load_______[2];\n float _metile_v20_r31 = _metile_vector_load_______[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v21_r16 = static_cast(_metile_v20_r16);\n float _metile_v21_r17 = static_cast(_metile_v20_r17);\n float _metile_v21_r18 = static_cast(_metile_v20_r18);\n float _metile_v21_r19 = static_cast(_metile_v20_r19);\n float _metile_v21_r20 = static_cast(_metile_v20_r20);\n float _metile_v21_r21 = static_cast(_metile_v20_r21);\n float _metile_v21_r22 = static_cast(_metile_v20_r22);\n float _metile_v21_r23 = static_cast(_metile_v20_r23);\n float _metile_v21_r24 = static_cast(_metile_v20_r24);\n float _metile_v21_r25 = static_cast(_metile_v20_r25);\n float _metile_v21_r26 = static_cast(_metile_v20_r26);\n float _metile_v21_r27 = static_cast(_metile_v20_r27);\n float _metile_v21_r28 = static_cast(_metile_v20_r28);\n float _metile_v21_r29 = static_cast(_metile_v20_r29);\n float _metile_v21_r30 = static_cast(_metile_v20_r30);\n float _metile_v21_r31 = static_cast(_metile_v20_r31);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_v22_r16 = _metile_v21_r16 * _metile_v21_r16;\n float _metile_v22_r17 = _metile_v21_r17 * _metile_v21_r17;\n float _metile_v22_r18 = _metile_v21_r18 * _metile_v21_r18;\n float _metile_v22_r19 = _metile_v21_r19 * _metile_v21_r19;\n float _metile_v22_r20 = _metile_v21_r20 * _metile_v21_r20;\n float _metile_v22_r21 = _metile_v21_r21 * _metile_v21_r21;\n float _metile_v22_r22 = _metile_v21_r22 * _metile_v21_r22;\n float _metile_v22_r23 = _metile_v21_r23 * _metile_v21_r23;\n float _metile_v22_r24 = _metile_v21_r24 * _metile_v21_r24;\n float _metile_v22_r25 = _metile_v21_r25 * _metile_v21_r25;\n float _metile_v22_r26 = _metile_v21_r26 * _metile_v21_r26;\n float _metile_v22_r27 = _metile_v21_r27 * _metile_v21_r27;\n float _metile_v22_r28 = _metile_v21_r28 * _metile_v21_r28;\n float _metile_v22_r29 = _metile_v21_r29 * _metile_v21_r29;\n float _metile_v22_r30 = _metile_v21_r30 * _metile_v21_r30;\n float _metile_v22_r31 = _metile_v21_r31 * _metile_v21_r31;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_v22_r16 + _metile_v22_r17;\n float _metile_register_sum_________ = _metile_v22_r18 + _metile_v22_r19;\n float _metile_register_sum__________ = _metile_v22_r20 + _metile_v22_r21;\n float _metile_register_sum___________ = _metile_v22_r22 + _metile_v22_r23;\n float _metile_register_sum____________ = _metile_v22_r24 + _metile_v22_r25;\n float _metile_register_sum_____________ = _metile_v22_r26 + _metile_v22_r27;\n float _metile_register_sum______________ = _metile_v22_r28 + _metile_v22_r29;\n float _metile_register_sum_______________ = _metile_v22_r30 + _metile_v22_r31;\n float _metile_register_sum________________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________________ = _metile_register_sum____________ + _metile_register_sum_____________;\n float _metile_register_sum_______________________ = _metile_register_sum______________ + _metile_register_sum_______________;\n float _metile_register_sum________________________ = _metile_register_sum________________ + _metile_register_sum_________________;\n float _metile_register_sum_________________________ = _metile_register_sum__________________ + _metile_register_sum___________________;\n float _metile_register_sum__________________________ = _metile_register_sum____________________ + _metile_register_sum_____________________;\n float _metile_register_sum___________________________ = _metile_register_sum______________________ + _metile_register_sum_______________________;\n float _metile_register_sum____________________________ = _metile_register_sum________________________ + _metile_register_sum_________________________;\n float _metile_register_sum_____________________________ = _metile_register_sum__________________________ + _metile_register_sum___________________________;\n float _metile_register_sum______________________________ = _metile_register_sum____________________________ + _metile_register_sum_____________________________;\n float v23 = simd_sum(_metile_register_sum______________________________);\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v32_r16 = _metile_register_index________________ >= 0;\n bool _metile_v32_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v32_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v32_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v32_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v32_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v32_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v32_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v32_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v32_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v32_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v32_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v32_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v32_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v32_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v32_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v33_r8 = _metile_register_index________ < 1024;\n bool _metile_v33_r9 = _metile_register_index_________ < 1024;\n bool _metile_v33_r10 = _metile_register_index__________ < 1024;\n bool _metile_v33_r11 = _metile_register_index___________ < 1024;\n bool _metile_v33_r12 = _metile_register_index____________ < 1024;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v33_r14 = _metile_register_index______________ < 1024;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v33_r16 = _metile_register_index________________ < 1024;\n bool _metile_v33_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v33_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v33_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v33_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v33_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v33_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v33_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v33_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v33_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v33_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v33_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v33_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v33_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v33_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v33_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n bool _metile_v34_r16 = _metile_v32_r16 & _metile_v33_r16;\n bool _metile_v34_r17 = _metile_v32_r17 & _metile_v33_r17;\n bool _metile_v34_r18 = _metile_v32_r18 & _metile_v33_r18;\n bool _metile_v34_r19 = _metile_v32_r19 & _metile_v33_r19;\n bool _metile_v34_r20 = _metile_v32_r20 & _metile_v33_r20;\n bool _metile_v34_r21 = _metile_v32_r21 & _metile_v33_r21;\n bool _metile_v34_r22 = _metile_v32_r22 & _metile_v33_r22;\n bool _metile_v34_r23 = _metile_v32_r23 & _metile_v33_r23;\n bool _metile_v34_r24 = _metile_v32_r24 & _metile_v33_r24;\n bool _metile_v34_r25 = _metile_v32_r25 & _metile_v33_r25;\n bool _metile_v34_r26 = _metile_v32_r26 & _metile_v33_r26;\n bool _metile_v34_r27 = _metile_v32_r27 & _metile_v33_r27;\n bool _metile_v34_r28 = _metile_v32_r28 & _metile_v33_r28;\n bool _metile_v34_r29 = _metile_v32_r29 & _metile_v33_r29;\n bool _metile_v34_r30 = _metile_v32_r30 & _metile_v33_r30;\n bool _metile_v34_r31 = _metile_v32_r31 & _metile_v33_r31;\n float4 _metile_vector_load________;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load________ = float4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load________[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load________[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load________[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load________[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n float _metile_v36_r0 = _metile_vector_load________[0];\n float _metile_v36_r1 = _metile_vector_load________[1];\n float _metile_v36_r2 = _metile_vector_load________[2];\n float _metile_v36_r3 = _metile_vector_load________[3];\n float4 _metile_vector_load_________;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load_________ = float4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load_________[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load_________[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load_________[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load_________[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n float _metile_v36_r4 = _metile_vector_load_________[0];\n float _metile_v36_r5 = _metile_vector_load_________[1];\n float _metile_v36_r6 = _metile_vector_load_________[2];\n float _metile_v36_r7 = _metile_vector_load_________[3];\n float4 _metile_vector_load__________;\n if ((_metile_v34_r8) && (_metile_v34_r9) && (_metile_v34_r10) && (_metile_v34_r11) && (long(_metile_register_index_________) == long(_metile_register_index________) + 1) && (long(_metile_register_index__________) == long(_metile_register_index________) + 2) && (long(_metile_register_index___________) == long(_metile_register_index________) + 3)) {\n _metile_vector_load__________ = float4(*reinterpret_cast(W + _metile_register_index________));\n } else {\n _metile_vector_load__________[0] = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n _metile_vector_load__________[1] = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n _metile_vector_load__________[2] = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n _metile_vector_load__________[3] = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n }\n float _metile_v36_r8 = _metile_vector_load__________[0];\n float _metile_v36_r9 = _metile_vector_load__________[1];\n float _metile_v36_r10 = _metile_vector_load__________[2];\n float _metile_v36_r11 = _metile_vector_load__________[3];\n float4 _metile_vector_load___________;\n if ((_metile_v34_r12) && (_metile_v34_r13) && (_metile_v34_r14) && (_metile_v34_r15) && (long(_metile_register_index_____________) == long(_metile_register_index____________) + 1) && (long(_metile_register_index______________) == long(_metile_register_index____________) + 2) && (long(_metile_register_index_______________) == long(_metile_register_index____________) + 3)) {\n _metile_vector_load___________ = float4(*reinterpret_cast(W + _metile_register_index____________));\n } else {\n _metile_vector_load___________[0] = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n _metile_vector_load___________[1] = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n _metile_vector_load___________[2] = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n _metile_vector_load___________[3] = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n }\n float _metile_v36_r12 = _metile_vector_load___________[0];\n float _metile_v36_r13 = _metile_vector_load___________[1];\n float _metile_v36_r14 = _metile_vector_load___________[2];\n float _metile_v36_r15 = _metile_vector_load___________[3];\n float4 _metile_vector_load____________;\n if ((_metile_v34_r16) && (_metile_v34_r17) && (_metile_v34_r18) && (_metile_v34_r19) && (long(_metile_register_index_________________) == long(_metile_register_index________________) + 1) && (long(_metile_register_index__________________) == long(_metile_register_index________________) + 2) && (long(_metile_register_index___________________) == long(_metile_register_index________________) + 3)) {\n _metile_vector_load____________ = float4(*reinterpret_cast(W + _metile_register_index________________));\n } else {\n _metile_vector_load____________[0] = _metile_v34_r16 ? W[_metile_register_index________________] : static_cast(0);\n _metile_vector_load____________[1] = _metile_v34_r17 ? W[_metile_register_index_________________] : static_cast(0);\n _metile_vector_load____________[2] = _metile_v34_r18 ? W[_metile_register_index__________________] : static_cast(0);\n _metile_vector_load____________[3] = _metile_v34_r19 ? W[_metile_register_index___________________] : static_cast(0);\n }\n float _metile_v36_r16 = _metile_vector_load____________[0];\n float _metile_v36_r17 = _metile_vector_load____________[1];\n float _metile_v36_r18 = _metile_vector_load____________[2];\n float _metile_v36_r19 = _metile_vector_load____________[3];\n float4 _metile_vector_load_____________;\n if ((_metile_v34_r20) && (_metile_v34_r21) && (_metile_v34_r22) && (_metile_v34_r23) && (long(_metile_register_index_____________________) == long(_metile_register_index____________________) + 1) && (long(_metile_register_index______________________) == long(_metile_register_index____________________) + 2) && (long(_metile_register_index_______________________) == long(_metile_register_index____________________) + 3)) {\n _metile_vector_load_____________ = float4(*reinterpret_cast(W + _metile_register_index____________________));\n } else {\n _metile_vector_load_____________[0] = _metile_v34_r20 ? W[_metile_register_index____________________] : static_cast(0);\n _metile_vector_load_____________[1] = _metile_v34_r21 ? W[_metile_register_index_____________________] : static_cast(0);\n _metile_vector_load_____________[2] = _metile_v34_r22 ? W[_metile_register_index______________________] : static_cast(0);\n _metile_vector_load_____________[3] = _metile_v34_r23 ? W[_metile_register_index_______________________] : static_cast(0);\n }\n float _metile_v36_r20 = _metile_vector_load_____________[0];\n float _metile_v36_r21 = _metile_vector_load_____________[1];\n float _metile_v36_r22 = _metile_vector_load_____________[2];\n float _metile_v36_r23 = _metile_vector_load_____________[3];\n float4 _metile_vector_load______________;\n if ((_metile_v34_r24) && (_metile_v34_r25) && (_metile_v34_r26) && (_metile_v34_r27) && (long(_metile_register_index_________________________) == long(_metile_register_index________________________) + 1) && (long(_metile_register_index__________________________) == long(_metile_register_index________________________) + 2) && (long(_metile_register_index___________________________) == long(_metile_register_index________________________) + 3)) {\n _metile_vector_load______________ = float4(*reinterpret_cast(W + _metile_register_index________________________));\n } else {\n _metile_vector_load______________[0] = _metile_v34_r24 ? W[_metile_register_index________________________] : static_cast(0);\n _metile_vector_load______________[1] = _metile_v34_r25 ? W[_metile_register_index_________________________] : static_cast(0);\n _metile_vector_load______________[2] = _metile_v34_r26 ? W[_metile_register_index__________________________] : static_cast(0);\n _metile_vector_load______________[3] = _metile_v34_r27 ? W[_metile_register_index___________________________] : static_cast(0);\n }\n float _metile_v36_r24 = _metile_vector_load______________[0];\n float _metile_v36_r25 = _metile_vector_load______________[1];\n float _metile_v36_r26 = _metile_vector_load______________[2];\n float _metile_v36_r27 = _metile_vector_load______________[3];\n float4 _metile_vector_load_______________;\n if ((_metile_v34_r28) && (_metile_v34_r29) && (_metile_v34_r30) && (_metile_v34_r31) && (long(_metile_register_index_____________________________) == long(_metile_register_index____________________________) + 1) && (long(_metile_register_index______________________________) == long(_metile_register_index____________________________) + 2) && (long(_metile_register_index_______________________________) == long(_metile_register_index____________________________) + 3)) {\n _metile_vector_load_______________ = float4(*reinterpret_cast(W + _metile_register_index____________________________));\n } else {\n _metile_vector_load_______________[0] = _metile_v34_r28 ? W[_metile_register_index____________________________] : static_cast(0);\n _metile_vector_load_______________[1] = _metile_v34_r29 ? W[_metile_register_index_____________________________] : static_cast(0);\n _metile_vector_load_______________[2] = _metile_v34_r30 ? W[_metile_register_index______________________________] : static_cast(0);\n _metile_vector_load_______________[3] = _metile_v34_r31 ? W[_metile_register_index_______________________________] : static_cast(0);\n }\n float _metile_v36_r28 = _metile_vector_load_______________[0];\n float _metile_v36_r29 = _metile_vector_load_______________[1];\n float _metile_v36_r30 = _metile_vector_load_______________[2];\n float _metile_v36_r31 = _metile_vector_load_______________[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v37_r16 = static_cast(_metile_v36_r16);\n float _metile_v37_r17 = static_cast(_metile_v36_r17);\n float _metile_v37_r18 = static_cast(_metile_v36_r18);\n float _metile_v37_r19 = static_cast(_metile_v36_r19);\n float _metile_v37_r20 = static_cast(_metile_v36_r20);\n float _metile_v37_r21 = static_cast(_metile_v36_r21);\n float _metile_v37_r22 = static_cast(_metile_v36_r22);\n float _metile_v37_r23 = static_cast(_metile_v36_r23);\n float _metile_v37_r24 = static_cast(_metile_v36_r24);\n float _metile_v37_r25 = static_cast(_metile_v36_r25);\n float _metile_v37_r26 = static_cast(_metile_v36_r26);\n float _metile_v37_r27 = static_cast(_metile_v36_r27);\n float _metile_v37_r28 = static_cast(_metile_v36_r28);\n float _metile_v37_r29 = static_cast(_metile_v36_r29);\n float _metile_v37_r30 = static_cast(_metile_v36_r30);\n float _metile_v37_r31 = static_cast(_metile_v36_r31);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v38_r16 = _metile_v21_r16 * v29;\n float _metile_v38_r17 = _metile_v21_r17 * v29;\n float _metile_v38_r18 = _metile_v21_r18 * v29;\n float _metile_v38_r19 = _metile_v21_r19 * v29;\n float _metile_v38_r20 = _metile_v21_r20 * v29;\n float _metile_v38_r21 = _metile_v21_r21 * v29;\n float _metile_v38_r22 = _metile_v21_r22 * v29;\n float _metile_v38_r23 = _metile_v21_r23 * v29;\n float _metile_v38_r24 = _metile_v21_r24 * v29;\n float _metile_v38_r25 = _metile_v21_r25 * v29;\n float _metile_v38_r26 = _metile_v21_r26 * v29;\n float _metile_v38_r27 = _metile_v21_r27 * v29;\n float _metile_v38_r28 = _metile_v21_r28 * v29;\n float _metile_v38_r29 = _metile_v21_r29 * v29;\n float _metile_v38_r30 = _metile_v21_r30 * v29;\n float _metile_v38_r31 = _metile_v21_r31 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n float _metile_v39_r16 = _metile_v38_r16 * _metile_v37_r16;\n float _metile_v39_r17 = _metile_v38_r17 * _metile_v37_r17;\n float _metile_v39_r18 = _metile_v38_r18 * _metile_v37_r18;\n float _metile_v39_r19 = _metile_v38_r19 * _metile_v37_r19;\n float _metile_v39_r20 = _metile_v38_r20 * _metile_v37_r20;\n float _metile_v39_r21 = _metile_v38_r21 * _metile_v37_r21;\n float _metile_v39_r22 = _metile_v38_r22 * _metile_v37_r22;\n float _metile_v39_r23 = _metile_v38_r23 * _metile_v37_r23;\n float _metile_v39_r24 = _metile_v38_r24 * _metile_v37_r24;\n float _metile_v39_r25 = _metile_v38_r25 * _metile_v37_r25;\n float _metile_v39_r26 = _metile_v38_r26 * _metile_v37_r26;\n float _metile_v39_r27 = _metile_v38_r27 * _metile_v37_r27;\n float _metile_v39_r28 = _metile_v38_r28 * _metile_v37_r28;\n float _metile_v39_r29 = _metile_v38_r29 * _metile_v37_r29;\n float _metile_v39_r30 = _metile_v38_r30 * _metile_v37_r30;\n float _metile_v39_r31 = _metile_v38_r31 * _metile_v37_r31;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v41_r16 = _metile_register_index________________ >= 0;\n bool _metile_v41_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v41_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v41_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v41_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v41_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v41_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v41_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v41_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v41_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v41_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v41_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v41_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v41_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v41_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v41_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v42_r8 = _metile_register_index________ < 1024;\n bool _metile_v42_r9 = _metile_register_index_________ < 1024;\n bool _metile_v42_r10 = _metile_register_index__________ < 1024;\n bool _metile_v42_r11 = _metile_register_index___________ < 1024;\n bool _metile_v42_r12 = _metile_register_index____________ < 1024;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v42_r14 = _metile_register_index______________ < 1024;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v42_r16 = _metile_register_index________________ < 1024;\n bool _metile_v42_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v42_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v42_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v42_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v42_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v42_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v42_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v42_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v42_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v42_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v42_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v42_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v42_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v42_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v42_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n bool _metile_v43_r16 = _metile_v41_r16 & _metile_v42_r16;\n bool _metile_v43_r17 = _metile_v41_r17 & _metile_v42_r17;\n bool _metile_v43_r18 = _metile_v41_r18 & _metile_v42_r18;\n bool _metile_v43_r19 = _metile_v41_r19 & _metile_v42_r19;\n bool _metile_v43_r20 = _metile_v41_r20 & _metile_v42_r20;\n bool _metile_v43_r21 = _metile_v41_r21 & _metile_v42_r21;\n bool _metile_v43_r22 = _metile_v41_r22 & _metile_v42_r22;\n bool _metile_v43_r23 = _metile_v41_r23 & _metile_v42_r23;\n bool _metile_v43_r24 = _metile_v41_r24 & _metile_v42_r24;\n bool _metile_v43_r25 = _metile_v41_r25 & _metile_v42_r25;\n bool _metile_v43_r26 = _metile_v41_r26 & _metile_v42_r26;\n bool _metile_v43_r27 = _metile_v41_r27 & _metile_v42_r27;\n bool _metile_v43_r28 = _metile_v41_r28 & _metile_v42_r28;\n bool _metile_v43_r29 = _metile_v41_r29 & _metile_v42_r29;\n bool _metile_v43_r30 = _metile_v41_r30 & _metile_v42_r30;\n bool _metile_v43_r31 = _metile_v41_r31 & _metile_v42_r31;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n int _off__metile_v44_r16 = v9 + _metile_register_index________________;\n int _off__metile_v44_r17 = v9 + _metile_register_index_________________;\n int _off__metile_v44_r18 = v9 + _metile_register_index__________________;\n int _off__metile_v44_r19 = v9 + _metile_register_index___________________;\n int _off__metile_v44_r20 = v9 + _metile_register_index____________________;\n int _off__metile_v44_r21 = v9 + _metile_register_index_____________________;\n int _off__metile_v44_r22 = v9 + _metile_register_index______________________;\n int _off__metile_v44_r23 = v9 + _metile_register_index_______________________;\n int _off__metile_v44_r24 = v9 + _metile_register_index________________________;\n int _off__metile_v44_r25 = v9 + _metile_register_index_________________________;\n int _off__metile_v44_r26 = v9 + _metile_register_index__________________________;\n int _off__metile_v44_r27 = v9 + _metile_register_index___________________________;\n int _off__metile_v44_r28 = v9 + _metile_register_index____________________________;\n int _off__metile_v44_r29 = v9 + _metile_register_index_____________________________;\n int _off__metile_v44_r30 = v9 + _metile_register_index______________________________;\n int _off__metile_v44_r31 = v9 + _metile_register_index_______________________________;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_float4(float4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_float4(float4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n if ((_metile_v43_r8) && (_metile_v43_r9) && (_metile_v43_r10) && (_metile_v43_r11) && (long(_off__metile_v44_r9) == long(_off__metile_v44_r8) + 1) && (long(_off__metile_v44_r10) == long(_off__metile_v44_r8) + 2) && (long(_off__metile_v44_r11) == long(_off__metile_v44_r8) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r8) = packed_float4(float4(static_cast(_metile_v39_r8), static_cast(_metile_v39_r9), static_cast(_metile_v39_r10), static_cast(_metile_v39_r11)));\n } else {\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = static_cast(_metile_v39_r8); }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = static_cast(_metile_v39_r9); }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = static_cast(_metile_v39_r10); }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = static_cast(_metile_v39_r11); }\n }\n if ((_metile_v43_r12) && (_metile_v43_r13) && (_metile_v43_r14) && (_metile_v43_r15) && (long(_off__metile_v44_r13) == long(_off__metile_v44_r12) + 1) && (long(_off__metile_v44_r14) == long(_off__metile_v44_r12) + 2) && (long(_off__metile_v44_r15) == long(_off__metile_v44_r12) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r12) = packed_float4(float4(static_cast(_metile_v39_r12), static_cast(_metile_v39_r13), static_cast(_metile_v39_r14), static_cast(_metile_v39_r15)));\n } else {\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = static_cast(_metile_v39_r12); }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = static_cast(_metile_v39_r13); }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = static_cast(_metile_v39_r14); }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = static_cast(_metile_v39_r15); }\n }\n if ((_metile_v43_r16) && (_metile_v43_r17) && (_metile_v43_r18) && (_metile_v43_r19) && (long(_off__metile_v44_r17) == long(_off__metile_v44_r16) + 1) && (long(_off__metile_v44_r18) == long(_off__metile_v44_r16) + 2) && (long(_off__metile_v44_r19) == long(_off__metile_v44_r16) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r16) = packed_float4(float4(static_cast(_metile_v39_r16), static_cast(_metile_v39_r17), static_cast(_metile_v39_r18), static_cast(_metile_v39_r19)));\n } else {\n if (_metile_v43_r16) { Out[_off__metile_v44_r16] = static_cast(_metile_v39_r16); }\n if (_metile_v43_r17) { Out[_off__metile_v44_r17] = static_cast(_metile_v39_r17); }\n if (_metile_v43_r18) { Out[_off__metile_v44_r18] = static_cast(_metile_v39_r18); }\n if (_metile_v43_r19) { Out[_off__metile_v44_r19] = static_cast(_metile_v39_r19); }\n }\n if ((_metile_v43_r20) && (_metile_v43_r21) && (_metile_v43_r22) && (_metile_v43_r23) && (long(_off__metile_v44_r21) == long(_off__metile_v44_r20) + 1) && (long(_off__metile_v44_r22) == long(_off__metile_v44_r20) + 2) && (long(_off__metile_v44_r23) == long(_off__metile_v44_r20) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r20) = packed_float4(float4(static_cast(_metile_v39_r20), static_cast(_metile_v39_r21), static_cast(_metile_v39_r22), static_cast(_metile_v39_r23)));\n } else {\n if (_metile_v43_r20) { Out[_off__metile_v44_r20] = static_cast(_metile_v39_r20); }\n if (_metile_v43_r21) { Out[_off__metile_v44_r21] = static_cast(_metile_v39_r21); }\n if (_metile_v43_r22) { Out[_off__metile_v44_r22] = static_cast(_metile_v39_r22); }\n if (_metile_v43_r23) { Out[_off__metile_v44_r23] = static_cast(_metile_v39_r23); }\n }\n if ((_metile_v43_r24) && (_metile_v43_r25) && (_metile_v43_r26) && (_metile_v43_r27) && (long(_off__metile_v44_r25) == long(_off__metile_v44_r24) + 1) && (long(_off__metile_v44_r26) == long(_off__metile_v44_r24) + 2) && (long(_off__metile_v44_r27) == long(_off__metile_v44_r24) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r24) = packed_float4(float4(static_cast(_metile_v39_r24), static_cast(_metile_v39_r25), static_cast(_metile_v39_r26), static_cast(_metile_v39_r27)));\n } else {\n if (_metile_v43_r24) { Out[_off__metile_v44_r24] = static_cast(_metile_v39_r24); }\n if (_metile_v43_r25) { Out[_off__metile_v44_r25] = static_cast(_metile_v39_r25); }\n if (_metile_v43_r26) { Out[_off__metile_v44_r26] = static_cast(_metile_v39_r26); }\n if (_metile_v43_r27) { Out[_off__metile_v44_r27] = static_cast(_metile_v39_r27); }\n }\n if ((_metile_v43_r28) && (_metile_v43_r29) && (_metile_v43_r30) && (_metile_v43_r31) && (long(_off__metile_v44_r29) == long(_off__metile_v44_r28) + 1) && (long(_off__metile_v44_r30) == long(_off__metile_v44_r28) + 2) && (long(_off__metile_v44_r31) == long(_off__metile_v44_r28) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r28) = packed_float4(float4(static_cast(_metile_v39_r28), static_cast(_metile_v39_r29), static_cast(_metile_v39_r30), static_cast(_metile_v39_r31)));\n } else {\n if (_metile_v43_r28) { Out[_off__metile_v44_r28] = static_cast(_metile_v39_r28); }\n if (_metile_v43_r29) { Out[_off__metile_v44_r29] = static_cast(_metile_v39_r29); }\n if (_metile_v43_r30) { Out[_off__metile_v44_r30] = static_cast(_metile_v39_r30); }\n if (_metile_v43_r31) { Out[_off__metile_v44_r31] = static_cast(_metile_v39_r31); }\n }\n}", "source_sha256": "c8101f914e715ded38108b0b5ca87ac0fdc945815a7e8480038b36c36f05e689", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 32, 1, 1 ], "is_gemm": false, "prefer_ordered": false, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 32, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 32 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [], "double_buffered": false, "vectorized_loads": 16, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 32, "threads": 32, "scratch": null, "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 16, "grouped_stores": 8 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 550, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.91649999999998, "control": 198.14600000000002, "speedup": 1.0011595799238568 }, "gpu_us": { "candidate": 3.1249946914613247, "control": 1.625041477382183, "speedup": 0.5200141561271816 } } }, { "frozen_register4": { "pairs": 626, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.375, "control": 196.0625, "speedup": 0.993350221659278 }, "gpu_us": { "candidate": 3.1249946914613247, "control": 1.6249832697212696, "speedup": 0.5199955296440479 } } }, { "frozen_register4": { "pairs": 558, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.79149999999998, "control": 200.0205, "speedup": 1.001146194908192 }, "gpu_us": { "candidate": 3.1666713766753674, "control": 1.625041477382183, "speedup": 0.5131702295829275 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.998545212575237, "round_speedups": [ 1.0011595799238568, 0.993350221659278, 1.001146194908192 ], "candidate": 198.3583030411007, "control": 198.06973387623916 }, "gpu_us": { "speedup": 0.5177165837800052, "round_speedups": [ 0.5200141561271816, 0.5199955296440479, 0.5131702295829275 ], "candidate": 3.138825615227742, "control": 1.6250220745968793 } } } }, { "name": "float32_1x1024", "dtype": "float32", "batches": 1, "width": 1024, "status": "measured", "variant": { "name": "register2_striped", "elements_per_thread": 2, "layout": "striped" }, "input_sha256": "ddb1751346f69e81810fa3e5e4fc2fa3d8214ffaace8e689775a59ca252f7042", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 4.76837158203125e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 511;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 512;\n int _metile_register_index_ = int(_metile_register_packed_);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n threadgroup float _metile_register_reduction[16];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 16u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n}", "source_sha256": "80a3b58c42ac34374f90c87b95d6214a45947a8245bd291ea088e84eea10acdd", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 512, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 512, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 2 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 16, "bytes": 64 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 2, "threads": 512, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 572, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 196.208, "control": 197.8545, "speedup": 1.0083916048275299 }, "gpu_us": { "candidate": 1.500011421740055, "control": 1.6249832697212696, "speedup": 1.083313930927435 } } }, { "frozen_register4": { "pairs": 629, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.292, "control": 195.083, "speedup": 0.9888033980090424 }, "gpu_us": { "candidate": 1.500011421740055, "control": 1.6249832697212696, "speedup": 1.083313930927435 } } }, { "frozen_register4": { "pairs": 625, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.792, "control": 198.167, "speedup": 1.0018959310791133 }, "gpu_us": { "candidate": 1.500011421740055, "control": 1.6249832697212696, "speedup": 1.083313930927435 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9996637136702479, "round_speedups": [ 1.0083916048275299, 0.9888033980090424, 1.0018959310791133 ], "candidate": 197.09622339238928, "control": 197.02994262681665 }, "gpu_us": { "speedup": 1.083313930927435, "round_speedups": [ 1.083313930927435, 1.083313930927435, 1.083313930927435 ], "candidate": 1.500011421740055, "control": 1.6249832697212696 } } } }, { "name": "float32_32x1024", "dtype": "float32", "batches": 32, "width": 1024, "status": "measured", "variant": { "name": "register4_blocked4", "elements_per_thread": 4, "layout": "blocked4" }, "input_sha256": "0fc05dcd6172e2eebffb6471582bea984c5a888fc3b3a095d91b296908e6567b", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int((((_metile_bounded_thread >> 8) & 1u) << 0) | (((_metile_bounded_thread >> 9) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 6) & 1u) << 8) | (((_metile_bounded_thread >> 7) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 8) & 1u) << 0) | (((_metile_register_packed_ >> 9) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 6) & 1u) << 8) | (((_metile_register_packed_ >> 7) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 8) & 1u) << 0) | (((_metile_register_packed__ >> 9) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 6) & 1u) << 8) | (((_metile_register_packed__ >> 7) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 8) & 1u) << 0) | (((_metile_register_packed___ >> 9) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 6) & 1u) << 8) | (((_metile_register_packed___ >> 7) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = float4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n float _metile_v20_r0 = _metile_vector_load[0];\n float _metile_v20_r1 = _metile_vector_load[1];\n float _metile_v20_r2 = _metile_vector_load[2];\n float _metile_v20_r3 = _metile_vector_load[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float4 _metile_vector_load_;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load_ = float4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load_[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load_[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load_[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load_[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n float _metile_v36_r0 = _metile_vector_load_[0];\n float _metile_v36_r1 = _metile_vector_load_[1];\n float _metile_v36_r2 = _metile_vector_load_[2];\n float _metile_v36_r3 = _metile_vector_load_[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_float4(float4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n}", "source_sha256": "90092f2d024ec05aca53dadb1c2ad4b583c721cc8dccc7ae0562e9412f81c900", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 2, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 2, "grouped_stores": 1 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 591, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.458, "control": 198.708, "speedup": 1.0063304601484873 }, "gpu_us": { "candidate": 2.41666566580534, "control": 2.3333122953772545, "speedup": 0.9655089358832314 } } }, { "frozen_register4": { "pairs": 349, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 214.75, "control": 217.0, "speedup": 1.010477299185099 }, "gpu_us": { "candidate": 2.4583423510193825, "control": 2.374988980591297, "speedup": 0.9660936686082303 } } }, { "frozen_register4": { "pairs": 452, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 210.1245, "control": 209.5205, "speedup": 0.9971255136835542 }, "gpu_us": { "candidate": 2.9583461582660675, "control": 2.4999608285725117, "speedup": 0.8450535180229812 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.004628905114736, "round_speedups": [ 1.0063304601484873, 1.010477299185099, 0.9971255136835542 ], "candidate": 207.31379407843886, "control": 208.2734299602038 }, "gpu_us": { "speedup": 0.9237474428973753, "round_speedups": [ 0.9655089358832314, 0.9660936686082303, 0.8450535180229812 ], "candidate": 2.5999758154336825, "control": 2.4017210111018823 } } } }, { "name": "float32_32x1024", "dtype": "float32", "batches": 32, "width": 1024, "status": "measured", "variant": { "name": "register8_striped", "elements_per_thread": 8, "layout": "striped" }, "input_sha256": "0fc05dcd6172e2eebffb6471582bea984c5a888fc3b3a095d91b296908e6567b", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 127;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 128;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 256;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 384;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 512;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 640;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 768;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 896;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n float _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n float _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n float _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_____ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum______ = _metile_register_sum____ + _metile_register_sum_____;\n threadgroup float _metile_register_reduction[4];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 4u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n float _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n float _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n float _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n}", "source_sha256": "34702ecd3ed2337fb2f6ddd5e80d06f362dc722ce7e9d0c31a768733f59fa7cf", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 128, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 128, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 8 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 4, "bytes": 16 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 8, "threads": 128, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 582, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.85399999999998, "control": 200.16649999999998, "speedup": 1.006600319832641 }, "gpu_us": { "candidate": 2.374988980591297, "control": 2.374988980591297, "speedup": 1.0 } } }, { "frozen_register4": { "pairs": 621, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 196.792, "control": 198.792, "speedup": 1.0101630147566973 }, "gpu_us": { "candidate": 2.374988980591297, "control": 2.333370503038168, "speedup": 0.9824763491985687 } } }, { "frozen_register4": { "pairs": 617, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.833, "control": 197.708, "speedup": 0.9993681539480269 }, "gpu_us": { "candidate": 2.374988980591297, "control": 2.333370503038168, "speedup": 0.9824763491985687 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.005367120302851, "round_speedups": [ 1.006600319832641, 1.0101630147566973, 0.9993681539480269 ], "candidate": 197.82454213300522, "control": 198.88629024948952 }, "gpu_us": { "speedup": 0.9882831778336025, "round_speedups": [ 1.0, 0.9824763491985687, 0.9824763491985687 ], "candidate": 2.374988980591297, "control": 2.3471616570585554 } } } }, { "name": "float32_32x1024", "dtype": "float32", "batches": 32, "width": 1024, "status": "measured", "variant": { "name": "register8_blocked4", "elements_per_thread": 8, "layout": "blocked4" }, "input_sha256": "0fc05dcd6172e2eebffb6471582bea984c5a888fc3b3a095d91b296908e6567b", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 127;\n int _metile_register_index = int((((_metile_bounded_thread >> 7) & 1u) << 0) | (((_metile_bounded_thread >> 8) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 6) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 128;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 7) & 1u) << 0) | (((_metile_register_packed_ >> 8) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 6) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 256;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 7) & 1u) << 0) | (((_metile_register_packed__ >> 8) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 6) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 384;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 7) & 1u) << 0) | (((_metile_register_packed___ >> 8) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 6) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 512;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 7) & 1u) << 0) | (((_metile_register_packed____ >> 8) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 5) & 1u) << 7) | (((_metile_register_packed____ >> 6) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 640;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 7) & 1u) << 0) | (((_metile_register_packed_____ >> 8) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 5) & 1u) << 7) | (((_metile_register_packed_____ >> 6) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 768;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 7) & 1u) << 0) | (((_metile_register_packed______ >> 8) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 5) & 1u) << 7) | (((_metile_register_packed______ >> 6) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 896;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 7) & 1u) << 0) | (((_metile_register_packed_______ >> 8) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 5) & 1u) << 7) | (((_metile_register_packed_______ >> 6) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n float4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = float4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n float _metile_v20_r0 = _metile_vector_load[0];\n float _metile_v20_r1 = _metile_vector_load[1];\n float _metile_v20_r2 = _metile_vector_load[2];\n float _metile_v20_r3 = _metile_vector_load[3];\n float4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = float4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n float _metile_v20_r4 = _metile_vector_load_[0];\n float _metile_v20_r5 = _metile_vector_load_[1];\n float _metile_v20_r6 = _metile_vector_load_[2];\n float _metile_v20_r7 = _metile_vector_load_[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_____ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum______ = _metile_register_sum____ + _metile_register_sum_____;\n threadgroup float _metile_register_reduction[4];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 4u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n float4 _metile_vector_load__;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load__ = float4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load__[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load__[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load__[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load__[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n float _metile_v36_r0 = _metile_vector_load__[0];\n float _metile_v36_r1 = _metile_vector_load__[1];\n float _metile_v36_r2 = _metile_vector_load__[2];\n float _metile_v36_r3 = _metile_vector_load__[3];\n float4 _metile_vector_load___;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load___ = float4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load___[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load___[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load___[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load___[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n float _metile_v36_r4 = _metile_vector_load___[0];\n float _metile_v36_r5 = _metile_vector_load___[1];\n float _metile_v36_r6 = _metile_vector_load___[2];\n float _metile_v36_r7 = _metile_vector_load___[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_float4(float4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_float4(float4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n}", "source_sha256": "6d76f908be757e95d29fcc3112125422c90cd6abc0b258ca9347b3c9175af34b", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 128, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 128, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 8 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 4, "bytes": 16 } ], "double_buffered": false, "vectorized_loads": 4, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 8, "threads": 128, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 4, "grouped_stores": 2 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 599, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.625, "control": 200.875, "speedup": 1.0012461059190032 }, "gpu_us": { "candidate": 2.708344254642725, "control": 2.374988980591297, "speedup": 0.8769154720711814 } } }, { "frozen_register4": { "pairs": 580, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.35399999999998, "control": 197.4375, "speedup": 1.0004230975809967 }, "gpu_us": { "candidate": 2.6666675694286823, "control": 2.374988980591297, "speedup": 0.8906205662148299 } } }, { "frozen_register4": { "pairs": 569, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.75, "control": 197.875, "speedup": 0.9856787048567871 }, "gpu_us": { "candidate": 2.708344254642725, "control": 2.374988980591297, "speedup": 0.8769154720711814 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9957568622046673, "round_speedups": [ 1.0012461059190032, 1.0004230975809967, 0.9856787048567871 ], "candidate": 199.57011716314548, "control": 198.7233136561917 }, "gpu_us": { "speedup": 0.8814602420184451, "round_speedups": [ 0.8769154720711814, 0.8906205662148299, 0.8769154720711814 ], "candidate": 2.6943801516819845, "control": 2.374988980591297 } } } }, { "name": "float32_32x1024", "dtype": "float32", "batches": 32, "width": 1024, "status": "measured", "variant": { "name": "register16_striped", "elements_per_thread": 16, "layout": "striped" }, "input_sha256": "0fc05dcd6172e2eebffb6471582bea984c5a888fc3b3a095d91b296908e6567b", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 63;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 64;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 128;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 192;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 256;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 320;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 384;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 448;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n int _metile_register_packed________ = _metile_bounded_thread + 512;\n int _metile_register_index________ = int(_metile_register_packed________);\n int _metile_register_packed_________ = _metile_bounded_thread + 576;\n int _metile_register_index_________ = int(_metile_register_packed_________);\n int _metile_register_packed__________ = _metile_bounded_thread + 640;\n int _metile_register_index__________ = int(_metile_register_packed__________);\n int _metile_register_packed___________ = _metile_bounded_thread + 704;\n int _metile_register_index___________ = int(_metile_register_packed___________);\n int _metile_register_packed____________ = _metile_bounded_thread + 768;\n int _metile_register_index____________ = int(_metile_register_packed____________);\n int _metile_register_packed_____________ = _metile_bounded_thread + 832;\n int _metile_register_index_____________ = int(_metile_register_packed_____________);\n int _metile_register_packed______________ = _metile_bounded_thread + 896;\n int _metile_register_index______________ = int(_metile_register_packed______________);\n int _metile_register_packed_______________ = _metile_bounded_thread + 960;\n int _metile_register_index_______________ = int(_metile_register_packed_______________);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v17_r8 = _metile_register_index________ < 1024;\n bool _metile_v17_r9 = _metile_register_index_________ < 1024;\n bool _metile_v17_r10 = _metile_register_index__________ < 1024;\n bool _metile_v17_r11 = _metile_register_index___________ < 1024;\n bool _metile_v17_r12 = _metile_register_index____________ < 1024;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v17_r14 = _metile_register_index______________ < 1024;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n float _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n float _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n float _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n float _metile_v20_r8 = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n float _metile_v20_r9 = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n float _metile_v20_r10 = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n float _metile_v20_r11 = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n float _metile_v20_r12 = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n float _metile_v20_r13 = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n float _metile_v20_r14 = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n float _metile_v20_r15 = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________ = _metile_register_sum____________ + _metile_register_sum_____________;\n threadgroup float _metile_register_reduction[2];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______________);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 2u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v33_r8 = _metile_register_index________ < 1024;\n bool _metile_v33_r9 = _metile_register_index_________ < 1024;\n bool _metile_v33_r10 = _metile_register_index__________ < 1024;\n bool _metile_v33_r11 = _metile_register_index___________ < 1024;\n bool _metile_v33_r12 = _metile_register_index____________ < 1024;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v33_r14 = _metile_register_index______________ < 1024;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n float _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n float _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n float _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n float _metile_v36_r8 = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n float _metile_v36_r9 = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n float _metile_v36_r10 = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n float _metile_v36_r11 = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n float _metile_v36_r12 = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n float _metile_v36_r13 = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n float _metile_v36_r14 = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n float _metile_v36_r15 = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v42_r8 = _metile_register_index________ < 1024;\n bool _metile_v42_r9 = _metile_register_index_________ < 1024;\n bool _metile_v42_r10 = _metile_register_index__________ < 1024;\n bool _metile_v42_r11 = _metile_register_index___________ < 1024;\n bool _metile_v42_r12 = _metile_register_index____________ < 1024;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v42_r14 = _metile_register_index______________ < 1024;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = _metile_v39_r8; }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = _metile_v39_r9; }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = _metile_v39_r10; }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = _metile_v39_r11; }\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = _metile_v39_r12; }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = _metile_v39_r13; }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = _metile_v39_r14; }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = _metile_v39_r15; }\n}", "source_sha256": "8d0e0811f88b35d004a56a9d076dee253811a6b9bdd8f46462f1664bdcec06df", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 64, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 64, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 16 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 2, "bytes": 8 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 16, "threads": 64, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 616, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.83350000000002, "control": 198.64600000000002, "speedup": 0.9940575529128 }, "gpu_us": { "candidate": 2.41666566580534, "control": 2.3333122953772545, "speedup": 0.9655089358832314 } } }, { "frozen_register4": { "pairs": 614, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.1245, "control": 199.9375, "speedup": 1.004082872775575 }, "gpu_us": { "candidate": 2.41666566580534, "control": 2.3333122953772545, "speedup": 0.9655089358832314 } } }, { "frozen_register4": { "pairs": 616, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.438, "control": 197.8125, "speedup": 0.9918495973686059 }, "gpu_us": { "candidate": 2.4583423510193825, "control": 2.2916938178241253, "speedup": 0.9322110148221812 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9966491559950744, "round_speedups": [ 0.9940575529128, 1.004082872775575, 0.9918495973686059 ], "candidate": 199.46512241360557, "control": 198.79674590397428 }, "gpu_us": { "speedup": 0.9542795309833677, "round_speedups": [ 0.9655089358832314, 0.9655089358832314, 0.9322110148221812 ], "candidate": 2.430478791022886, "control": 2.3193561607623425 } } } }, { "name": "float32_32x1024", "dtype": "float32", "batches": 32, "width": 1024, "status": "measured", "variant": { "name": "register16_blocked4", "elements_per_thread": 16, "layout": "blocked4" }, "input_sha256": "0fc05dcd6172e2eebffb6471582bea984c5a888fc3b3a095d91b296908e6567b", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 63;\n int _metile_register_index = int((((_metile_bounded_thread >> 6) & 1u) << 0) | (((_metile_bounded_thread >> 7) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 8) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 64;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 6) & 1u) << 0) | (((_metile_register_packed_ >> 7) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 8) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 128;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 6) & 1u) << 0) | (((_metile_register_packed__ >> 7) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 8) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 192;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 6) & 1u) << 0) | (((_metile_register_packed___ >> 7) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 8) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 256;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 6) & 1u) << 0) | (((_metile_register_packed____ >> 7) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 5) & 1u) << 7) | (((_metile_register_packed____ >> 8) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 320;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 6) & 1u) << 0) | (((_metile_register_packed_____ >> 7) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 5) & 1u) << 7) | (((_metile_register_packed_____ >> 8) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 384;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 6) & 1u) << 0) | (((_metile_register_packed______ >> 7) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 5) & 1u) << 7) | (((_metile_register_packed______ >> 8) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 448;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 6) & 1u) << 0) | (((_metile_register_packed_______ >> 7) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 5) & 1u) << 7) | (((_metile_register_packed_______ >> 8) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n int _metile_register_packed________ = _metile_bounded_thread + 512;\n int _metile_register_index________ = int((((_metile_register_packed________ >> 6) & 1u) << 0) | (((_metile_register_packed________ >> 7) & 1u) << 1) | (((_metile_register_packed________ >> 0) & 1u) << 2) | (((_metile_register_packed________ >> 1) & 1u) << 3) | (((_metile_register_packed________ >> 2) & 1u) << 4) | (((_metile_register_packed________ >> 3) & 1u) << 5) | (((_metile_register_packed________ >> 4) & 1u) << 6) | (((_metile_register_packed________ >> 5) & 1u) << 7) | (((_metile_register_packed________ >> 8) & 1u) << 8) | (((_metile_register_packed________ >> 9) & 1u) << 9));\n int _metile_register_packed_________ = _metile_bounded_thread + 576;\n int _metile_register_index_________ = int((((_metile_register_packed_________ >> 6) & 1u) << 0) | (((_metile_register_packed_________ >> 7) & 1u) << 1) | (((_metile_register_packed_________ >> 0) & 1u) << 2) | (((_metile_register_packed_________ >> 1) & 1u) << 3) | (((_metile_register_packed_________ >> 2) & 1u) << 4) | (((_metile_register_packed_________ >> 3) & 1u) << 5) | (((_metile_register_packed_________ >> 4) & 1u) << 6) | (((_metile_register_packed_________ >> 5) & 1u) << 7) | (((_metile_register_packed_________ >> 8) & 1u) << 8) | (((_metile_register_packed_________ >> 9) & 1u) << 9));\n int _metile_register_packed__________ = _metile_bounded_thread + 640;\n int _metile_register_index__________ = int((((_metile_register_packed__________ >> 6) & 1u) << 0) | (((_metile_register_packed__________ >> 7) & 1u) << 1) | (((_metile_register_packed__________ >> 0) & 1u) << 2) | (((_metile_register_packed__________ >> 1) & 1u) << 3) | (((_metile_register_packed__________ >> 2) & 1u) << 4) | (((_metile_register_packed__________ >> 3) & 1u) << 5) | (((_metile_register_packed__________ >> 4) & 1u) << 6) | (((_metile_register_packed__________ >> 5) & 1u) << 7) | (((_metile_register_packed__________ >> 8) & 1u) << 8) | (((_metile_register_packed__________ >> 9) & 1u) << 9));\n int _metile_register_packed___________ = _metile_bounded_thread + 704;\n int _metile_register_index___________ = int((((_metile_register_packed___________ >> 6) & 1u) << 0) | (((_metile_register_packed___________ >> 7) & 1u) << 1) | (((_metile_register_packed___________ >> 0) & 1u) << 2) | (((_metile_register_packed___________ >> 1) & 1u) << 3) | (((_metile_register_packed___________ >> 2) & 1u) << 4) | (((_metile_register_packed___________ >> 3) & 1u) << 5) | (((_metile_register_packed___________ >> 4) & 1u) << 6) | (((_metile_register_packed___________ >> 5) & 1u) << 7) | (((_metile_register_packed___________ >> 8) & 1u) << 8) | (((_metile_register_packed___________ >> 9) & 1u) << 9));\n int _metile_register_packed____________ = _metile_bounded_thread + 768;\n int _metile_register_index____________ = int((((_metile_register_packed____________ >> 6) & 1u) << 0) | (((_metile_register_packed____________ >> 7) & 1u) << 1) | (((_metile_register_packed____________ >> 0) & 1u) << 2) | (((_metile_register_packed____________ >> 1) & 1u) << 3) | (((_metile_register_packed____________ >> 2) & 1u) << 4) | (((_metile_register_packed____________ >> 3) & 1u) << 5) | (((_metile_register_packed____________ >> 4) & 1u) << 6) | (((_metile_register_packed____________ >> 5) & 1u) << 7) | (((_metile_register_packed____________ >> 8) & 1u) << 8) | (((_metile_register_packed____________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________ = _metile_bounded_thread + 832;\n int _metile_register_index_____________ = int((((_metile_register_packed_____________ >> 6) & 1u) << 0) | (((_metile_register_packed_____________ >> 7) & 1u) << 1) | (((_metile_register_packed_____________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________ >> 5) & 1u) << 7) | (((_metile_register_packed_____________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________ >> 9) & 1u) << 9));\n int _metile_register_packed______________ = _metile_bounded_thread + 896;\n int _metile_register_index______________ = int((((_metile_register_packed______________ >> 6) & 1u) << 0) | (((_metile_register_packed______________ >> 7) & 1u) << 1) | (((_metile_register_packed______________ >> 0) & 1u) << 2) | (((_metile_register_packed______________ >> 1) & 1u) << 3) | (((_metile_register_packed______________ >> 2) & 1u) << 4) | (((_metile_register_packed______________ >> 3) & 1u) << 5) | (((_metile_register_packed______________ >> 4) & 1u) << 6) | (((_metile_register_packed______________ >> 5) & 1u) << 7) | (((_metile_register_packed______________ >> 8) & 1u) << 8) | (((_metile_register_packed______________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________ = _metile_bounded_thread + 960;\n int _metile_register_index_______________ = int((((_metile_register_packed_______________ >> 6) & 1u) << 0) | (((_metile_register_packed_______________ >> 7) & 1u) << 1) | (((_metile_register_packed_______________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________ >> 5) & 1u) << 7) | (((_metile_register_packed_______________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v17_r8 = _metile_register_index________ < 1024;\n bool _metile_v17_r9 = _metile_register_index_________ < 1024;\n bool _metile_v17_r10 = _metile_register_index__________ < 1024;\n bool _metile_v17_r11 = _metile_register_index___________ < 1024;\n bool _metile_v17_r12 = _metile_register_index____________ < 1024;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v17_r14 = _metile_register_index______________ < 1024;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n float4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = float4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n float _metile_v20_r0 = _metile_vector_load[0];\n float _metile_v20_r1 = _metile_vector_load[1];\n float _metile_v20_r2 = _metile_vector_load[2];\n float _metile_v20_r3 = _metile_vector_load[3];\n float4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = float4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n float _metile_v20_r4 = _metile_vector_load_[0];\n float _metile_v20_r5 = _metile_vector_load_[1];\n float _metile_v20_r6 = _metile_vector_load_[2];\n float _metile_v20_r7 = _metile_vector_load_[3];\n float4 _metile_vector_load__;\n if ((_metile_v18_r8) && (_metile_v18_r9) && (_metile_v18_r10) && (_metile_v18_r11) && (long(_off__metile_v19_r9) == long(_off__metile_v19_r8) + 1) && (long(_off__metile_v19_r10) == long(_off__metile_v19_r8) + 2) && (long(_off__metile_v19_r11) == long(_off__metile_v19_r8) + 3)) {\n _metile_vector_load__ = float4(*reinterpret_cast(X + _off__metile_v19_r8));\n } else {\n _metile_vector_load__[0] = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n _metile_vector_load__[1] = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n _metile_vector_load__[2] = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n _metile_vector_load__[3] = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n }\n float _metile_v20_r8 = _metile_vector_load__[0];\n float _metile_v20_r9 = _metile_vector_load__[1];\n float _metile_v20_r10 = _metile_vector_load__[2];\n float _metile_v20_r11 = _metile_vector_load__[3];\n float4 _metile_vector_load___;\n if ((_metile_v18_r12) && (_metile_v18_r13) && (_metile_v18_r14) && (_metile_v18_r15) && (long(_off__metile_v19_r13) == long(_off__metile_v19_r12) + 1) && (long(_off__metile_v19_r14) == long(_off__metile_v19_r12) + 2) && (long(_off__metile_v19_r15) == long(_off__metile_v19_r12) + 3)) {\n _metile_vector_load___ = float4(*reinterpret_cast(X + _off__metile_v19_r12));\n } else {\n _metile_vector_load___[0] = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n _metile_vector_load___[1] = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n _metile_vector_load___[2] = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n _metile_vector_load___[3] = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n }\n float _metile_v20_r12 = _metile_vector_load___[0];\n float _metile_v20_r13 = _metile_vector_load___[1];\n float _metile_v20_r14 = _metile_vector_load___[2];\n float _metile_v20_r15 = _metile_vector_load___[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________ = _metile_register_sum____________ + _metile_register_sum_____________;\n threadgroup float _metile_register_reduction[2];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______________);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 2u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v33_r8 = _metile_register_index________ < 1024;\n bool _metile_v33_r9 = _metile_register_index_________ < 1024;\n bool _metile_v33_r10 = _metile_register_index__________ < 1024;\n bool _metile_v33_r11 = _metile_register_index___________ < 1024;\n bool _metile_v33_r12 = _metile_register_index____________ < 1024;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v33_r14 = _metile_register_index______________ < 1024;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n float4 _metile_vector_load____;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load____ = float4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load____[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load____[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load____[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load____[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n float _metile_v36_r0 = _metile_vector_load____[0];\n float _metile_v36_r1 = _metile_vector_load____[1];\n float _metile_v36_r2 = _metile_vector_load____[2];\n float _metile_v36_r3 = _metile_vector_load____[3];\n float4 _metile_vector_load_____;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load_____ = float4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load_____[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load_____[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load_____[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load_____[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n float _metile_v36_r4 = _metile_vector_load_____[0];\n float _metile_v36_r5 = _metile_vector_load_____[1];\n float _metile_v36_r6 = _metile_vector_load_____[2];\n float _metile_v36_r7 = _metile_vector_load_____[3];\n float4 _metile_vector_load______;\n if ((_metile_v34_r8) && (_metile_v34_r9) && (_metile_v34_r10) && (_metile_v34_r11) && (long(_metile_register_index_________) == long(_metile_register_index________) + 1) && (long(_metile_register_index__________) == long(_metile_register_index________) + 2) && (long(_metile_register_index___________) == long(_metile_register_index________) + 3)) {\n _metile_vector_load______ = float4(*reinterpret_cast(W + _metile_register_index________));\n } else {\n _metile_vector_load______[0] = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n _metile_vector_load______[1] = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n _metile_vector_load______[2] = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n _metile_vector_load______[3] = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n }\n float _metile_v36_r8 = _metile_vector_load______[0];\n float _metile_v36_r9 = _metile_vector_load______[1];\n float _metile_v36_r10 = _metile_vector_load______[2];\n float _metile_v36_r11 = _metile_vector_load______[3];\n float4 _metile_vector_load_______;\n if ((_metile_v34_r12) && (_metile_v34_r13) && (_metile_v34_r14) && (_metile_v34_r15) && (long(_metile_register_index_____________) == long(_metile_register_index____________) + 1) && (long(_metile_register_index______________) == long(_metile_register_index____________) + 2) && (long(_metile_register_index_______________) == long(_metile_register_index____________) + 3)) {\n _metile_vector_load_______ = float4(*reinterpret_cast(W + _metile_register_index____________));\n } else {\n _metile_vector_load_______[0] = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n _metile_vector_load_______[1] = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n _metile_vector_load_______[2] = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n _metile_vector_load_______[3] = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n }\n float _metile_v36_r12 = _metile_vector_load_______[0];\n float _metile_v36_r13 = _metile_vector_load_______[1];\n float _metile_v36_r14 = _metile_vector_load_______[2];\n float _metile_v36_r15 = _metile_vector_load_______[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v42_r8 = _metile_register_index________ < 1024;\n bool _metile_v42_r9 = _metile_register_index_________ < 1024;\n bool _metile_v42_r10 = _metile_register_index__________ < 1024;\n bool _metile_v42_r11 = _metile_register_index___________ < 1024;\n bool _metile_v42_r12 = _metile_register_index____________ < 1024;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v42_r14 = _metile_register_index______________ < 1024;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_float4(float4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_float4(float4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n if ((_metile_v43_r8) && (_metile_v43_r9) && (_metile_v43_r10) && (_metile_v43_r11) && (long(_off__metile_v44_r9) == long(_off__metile_v44_r8) + 1) && (long(_off__metile_v44_r10) == long(_off__metile_v44_r8) + 2) && (long(_off__metile_v44_r11) == long(_off__metile_v44_r8) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r8) = packed_float4(float4(static_cast(_metile_v39_r8), static_cast(_metile_v39_r9), static_cast(_metile_v39_r10), static_cast(_metile_v39_r11)));\n } else {\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = static_cast(_metile_v39_r8); }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = static_cast(_metile_v39_r9); }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = static_cast(_metile_v39_r10); }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = static_cast(_metile_v39_r11); }\n }\n if ((_metile_v43_r12) && (_metile_v43_r13) && (_metile_v43_r14) && (_metile_v43_r15) && (long(_off__metile_v44_r13) == long(_off__metile_v44_r12) + 1) && (long(_off__metile_v44_r14) == long(_off__metile_v44_r12) + 2) && (long(_off__metile_v44_r15) == long(_off__metile_v44_r12) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r12) = packed_float4(float4(static_cast(_metile_v39_r12), static_cast(_metile_v39_r13), static_cast(_metile_v39_r14), static_cast(_metile_v39_r15)));\n } else {\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = static_cast(_metile_v39_r12); }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = static_cast(_metile_v39_r13); }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = static_cast(_metile_v39_r14); }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = static_cast(_metile_v39_r15); }\n }\n}", "source_sha256": "638bb86de40e605f8a6ccd7a4a97089454fbe67cb9c226a6b7a7e2134cb962f6", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 64, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 64, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 16 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 2, "bytes": 8 } ], "double_buffered": false, "vectorized_loads": 8, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 16, "threads": 64, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 8, "grouped_stores": 4 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 532, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.958, "control": 200.83350000000002, "speedup": 0.98953231703111 }, "gpu_us": { "candidate": 2.7916976250708103, "control": 2.333341399207711, "speedup": 0.8358145159608849 } } }, { "frozen_register4": { "pairs": 199, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 208.959, "control": 204.791, "speedup": 0.9800535033188329 }, "gpu_us": { "candidate": 2.833374310284853, "control": 2.374988980591297, "speedup": 0.8382192822072025 } } }, { "frozen_register4": { "pairs": 486, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 225.8545, "control": 221.25, "speedup": 0.9796129809235592 }, "gpu_us": { "candidate": 4.62500611320138, "control": 3.2708339858800173, "speedup": 0.7072064135318474 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9830556412310473, "round_speedups": [ 0.98953231703111, 0.9800535033188329, 0.9796129809235592 ], "candidate": 212.37268995378892, "control": 208.77417090248443 }, "gpu_us": { "speedup": 0.7912940783239772, "round_speedups": [ 0.8358145159608849, 0.8382192822072025, 0.7072064135318474 ], "candidate": 3.3196697424817843, "control": 2.6268350092171184 } } } }, { "name": "float32_32x1024", "dtype": "float32", "batches": 32, "width": 1024, "status": "measured", "variant": { "name": "register32_striped", "elements_per_thread": 32, "layout": "striped" }, "input_sha256": "0fc05dcd6172e2eebffb6471582bea984c5a888fc3b3a095d91b296908e6567b", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 31;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 32;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 64;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 96;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 128;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 160;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 192;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 224;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n int _metile_register_packed________ = _metile_bounded_thread + 256;\n int _metile_register_index________ = int(_metile_register_packed________);\n int _metile_register_packed_________ = _metile_bounded_thread + 288;\n int _metile_register_index_________ = int(_metile_register_packed_________);\n int _metile_register_packed__________ = _metile_bounded_thread + 320;\n int _metile_register_index__________ = int(_metile_register_packed__________);\n int _metile_register_packed___________ = _metile_bounded_thread + 352;\n int _metile_register_index___________ = int(_metile_register_packed___________);\n int _metile_register_packed____________ = _metile_bounded_thread + 384;\n int _metile_register_index____________ = int(_metile_register_packed____________);\n int _metile_register_packed_____________ = _metile_bounded_thread + 416;\n int _metile_register_index_____________ = int(_metile_register_packed_____________);\n int _metile_register_packed______________ = _metile_bounded_thread + 448;\n int _metile_register_index______________ = int(_metile_register_packed______________);\n int _metile_register_packed_______________ = _metile_bounded_thread + 480;\n int _metile_register_index_______________ = int(_metile_register_packed_______________);\n int _metile_register_packed________________ = _metile_bounded_thread + 512;\n int _metile_register_index________________ = int(_metile_register_packed________________);\n int _metile_register_packed_________________ = _metile_bounded_thread + 544;\n int _metile_register_index_________________ = int(_metile_register_packed_________________);\n int _metile_register_packed__________________ = _metile_bounded_thread + 576;\n int _metile_register_index__________________ = int(_metile_register_packed__________________);\n int _metile_register_packed___________________ = _metile_bounded_thread + 608;\n int _metile_register_index___________________ = int(_metile_register_packed___________________);\n int _metile_register_packed____________________ = _metile_bounded_thread + 640;\n int _metile_register_index____________________ = int(_metile_register_packed____________________);\n int _metile_register_packed_____________________ = _metile_bounded_thread + 672;\n int _metile_register_index_____________________ = int(_metile_register_packed_____________________);\n int _metile_register_packed______________________ = _metile_bounded_thread + 704;\n int _metile_register_index______________________ = int(_metile_register_packed______________________);\n int _metile_register_packed_______________________ = _metile_bounded_thread + 736;\n int _metile_register_index_______________________ = int(_metile_register_packed_______________________);\n int _metile_register_packed________________________ = _metile_bounded_thread + 768;\n int _metile_register_index________________________ = int(_metile_register_packed________________________);\n int _metile_register_packed_________________________ = _metile_bounded_thread + 800;\n int _metile_register_index_________________________ = int(_metile_register_packed_________________________);\n int _metile_register_packed__________________________ = _metile_bounded_thread + 832;\n int _metile_register_index__________________________ = int(_metile_register_packed__________________________);\n int _metile_register_packed___________________________ = _metile_bounded_thread + 864;\n int _metile_register_index___________________________ = int(_metile_register_packed___________________________);\n int _metile_register_packed____________________________ = _metile_bounded_thread + 896;\n int _metile_register_index____________________________ = int(_metile_register_packed____________________________);\n int _metile_register_packed_____________________________ = _metile_bounded_thread + 928;\n int _metile_register_index_____________________________ = int(_metile_register_packed_____________________________);\n int _metile_register_packed______________________________ = _metile_bounded_thread + 960;\n int _metile_register_index______________________________ = int(_metile_register_packed______________________________);\n int _metile_register_packed_______________________________ = _metile_bounded_thread + 992;\n int _metile_register_index_______________________________ = int(_metile_register_packed_______________________________);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v16_r16 = _metile_register_index________________ >= 0;\n bool _metile_v16_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v16_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v16_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v16_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v16_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v16_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v16_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v16_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v16_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v16_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v16_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v16_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v16_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v16_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v16_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v17_r8 = _metile_register_index________ < 1024;\n bool _metile_v17_r9 = _metile_register_index_________ < 1024;\n bool _metile_v17_r10 = _metile_register_index__________ < 1024;\n bool _metile_v17_r11 = _metile_register_index___________ < 1024;\n bool _metile_v17_r12 = _metile_register_index____________ < 1024;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v17_r14 = _metile_register_index______________ < 1024;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v17_r16 = _metile_register_index________________ < 1024;\n bool _metile_v17_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v17_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v17_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v17_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v17_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v17_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v17_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v17_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v17_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v17_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v17_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v17_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v17_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v17_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v17_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n bool _metile_v18_r16 = _metile_v16_r16 & _metile_v17_r16;\n bool _metile_v18_r17 = _metile_v16_r17 & _metile_v17_r17;\n bool _metile_v18_r18 = _metile_v16_r18 & _metile_v17_r18;\n bool _metile_v18_r19 = _metile_v16_r19 & _metile_v17_r19;\n bool _metile_v18_r20 = _metile_v16_r20 & _metile_v17_r20;\n bool _metile_v18_r21 = _metile_v16_r21 & _metile_v17_r21;\n bool _metile_v18_r22 = _metile_v16_r22 & _metile_v17_r22;\n bool _metile_v18_r23 = _metile_v16_r23 & _metile_v17_r23;\n bool _metile_v18_r24 = _metile_v16_r24 & _metile_v17_r24;\n bool _metile_v18_r25 = _metile_v16_r25 & _metile_v17_r25;\n bool _metile_v18_r26 = _metile_v16_r26 & _metile_v17_r26;\n bool _metile_v18_r27 = _metile_v16_r27 & _metile_v17_r27;\n bool _metile_v18_r28 = _metile_v16_r28 & _metile_v17_r28;\n bool _metile_v18_r29 = _metile_v16_r29 & _metile_v17_r29;\n bool _metile_v18_r30 = _metile_v16_r30 & _metile_v17_r30;\n bool _metile_v18_r31 = _metile_v16_r31 & _metile_v17_r31;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n int _off__metile_v19_r16 = v2 + _metile_register_index________________;\n int _off__metile_v19_r17 = v2 + _metile_register_index_________________;\n int _off__metile_v19_r18 = v2 + _metile_register_index__________________;\n int _off__metile_v19_r19 = v2 + _metile_register_index___________________;\n int _off__metile_v19_r20 = v2 + _metile_register_index____________________;\n int _off__metile_v19_r21 = v2 + _metile_register_index_____________________;\n int _off__metile_v19_r22 = v2 + _metile_register_index______________________;\n int _off__metile_v19_r23 = v2 + _metile_register_index_______________________;\n int _off__metile_v19_r24 = v2 + _metile_register_index________________________;\n int _off__metile_v19_r25 = v2 + _metile_register_index_________________________;\n int _off__metile_v19_r26 = v2 + _metile_register_index__________________________;\n int _off__metile_v19_r27 = v2 + _metile_register_index___________________________;\n int _off__metile_v19_r28 = v2 + _metile_register_index____________________________;\n int _off__metile_v19_r29 = v2 + _metile_register_index_____________________________;\n int _off__metile_v19_r30 = v2 + _metile_register_index______________________________;\n int _off__metile_v19_r31 = v2 + _metile_register_index_______________________________;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n float _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n float _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n float _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n float _metile_v20_r8 = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n float _metile_v20_r9 = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n float _metile_v20_r10 = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n float _metile_v20_r11 = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n float _metile_v20_r12 = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n float _metile_v20_r13 = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n float _metile_v20_r14 = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n float _metile_v20_r15 = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n float _metile_v20_r16 = _metile_v18_r16 ? X[_off__metile_v19_r16] : static_cast(0);\n float _metile_v20_r17 = _metile_v18_r17 ? X[_off__metile_v19_r17] : static_cast(0);\n float _metile_v20_r18 = _metile_v18_r18 ? X[_off__metile_v19_r18] : static_cast(0);\n float _metile_v20_r19 = _metile_v18_r19 ? X[_off__metile_v19_r19] : static_cast(0);\n float _metile_v20_r20 = _metile_v18_r20 ? X[_off__metile_v19_r20] : static_cast(0);\n float _metile_v20_r21 = _metile_v18_r21 ? X[_off__metile_v19_r21] : static_cast(0);\n float _metile_v20_r22 = _metile_v18_r22 ? X[_off__metile_v19_r22] : static_cast(0);\n float _metile_v20_r23 = _metile_v18_r23 ? X[_off__metile_v19_r23] : static_cast(0);\n float _metile_v20_r24 = _metile_v18_r24 ? X[_off__metile_v19_r24] : static_cast(0);\n float _metile_v20_r25 = _metile_v18_r25 ? X[_off__metile_v19_r25] : static_cast(0);\n float _metile_v20_r26 = _metile_v18_r26 ? X[_off__metile_v19_r26] : static_cast(0);\n float _metile_v20_r27 = _metile_v18_r27 ? X[_off__metile_v19_r27] : static_cast(0);\n float _metile_v20_r28 = _metile_v18_r28 ? X[_off__metile_v19_r28] : static_cast(0);\n float _metile_v20_r29 = _metile_v18_r29 ? X[_off__metile_v19_r29] : static_cast(0);\n float _metile_v20_r30 = _metile_v18_r30 ? X[_off__metile_v19_r30] : static_cast(0);\n float _metile_v20_r31 = _metile_v18_r31 ? X[_off__metile_v19_r31] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v21_r16 = static_cast(_metile_v20_r16);\n float _metile_v21_r17 = static_cast(_metile_v20_r17);\n float _metile_v21_r18 = static_cast(_metile_v20_r18);\n float _metile_v21_r19 = static_cast(_metile_v20_r19);\n float _metile_v21_r20 = static_cast(_metile_v20_r20);\n float _metile_v21_r21 = static_cast(_metile_v20_r21);\n float _metile_v21_r22 = static_cast(_metile_v20_r22);\n float _metile_v21_r23 = static_cast(_metile_v20_r23);\n float _metile_v21_r24 = static_cast(_metile_v20_r24);\n float _metile_v21_r25 = static_cast(_metile_v20_r25);\n float _metile_v21_r26 = static_cast(_metile_v20_r26);\n float _metile_v21_r27 = static_cast(_metile_v20_r27);\n float _metile_v21_r28 = static_cast(_metile_v20_r28);\n float _metile_v21_r29 = static_cast(_metile_v20_r29);\n float _metile_v21_r30 = static_cast(_metile_v20_r30);\n float _metile_v21_r31 = static_cast(_metile_v20_r31);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_v22_r16 = _metile_v21_r16 * _metile_v21_r16;\n float _metile_v22_r17 = _metile_v21_r17 * _metile_v21_r17;\n float _metile_v22_r18 = _metile_v21_r18 * _metile_v21_r18;\n float _metile_v22_r19 = _metile_v21_r19 * _metile_v21_r19;\n float _metile_v22_r20 = _metile_v21_r20 * _metile_v21_r20;\n float _metile_v22_r21 = _metile_v21_r21 * _metile_v21_r21;\n float _metile_v22_r22 = _metile_v21_r22 * _metile_v21_r22;\n float _metile_v22_r23 = _metile_v21_r23 * _metile_v21_r23;\n float _metile_v22_r24 = _metile_v21_r24 * _metile_v21_r24;\n float _metile_v22_r25 = _metile_v21_r25 * _metile_v21_r25;\n float _metile_v22_r26 = _metile_v21_r26 * _metile_v21_r26;\n float _metile_v22_r27 = _metile_v21_r27 * _metile_v21_r27;\n float _metile_v22_r28 = _metile_v21_r28 * _metile_v21_r28;\n float _metile_v22_r29 = _metile_v21_r29 * _metile_v21_r29;\n float _metile_v22_r30 = _metile_v21_r30 * _metile_v21_r30;\n float _metile_v22_r31 = _metile_v21_r31 * _metile_v21_r31;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_v22_r16 + _metile_v22_r17;\n float _metile_register_sum_________ = _metile_v22_r18 + _metile_v22_r19;\n float _metile_register_sum__________ = _metile_v22_r20 + _metile_v22_r21;\n float _metile_register_sum___________ = _metile_v22_r22 + _metile_v22_r23;\n float _metile_register_sum____________ = _metile_v22_r24 + _metile_v22_r25;\n float _metile_register_sum_____________ = _metile_v22_r26 + _metile_v22_r27;\n float _metile_register_sum______________ = _metile_v22_r28 + _metile_v22_r29;\n float _metile_register_sum_______________ = _metile_v22_r30 + _metile_v22_r31;\n float _metile_register_sum________________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________________ = _metile_register_sum____________ + _metile_register_sum_____________;\n float _metile_register_sum_______________________ = _metile_register_sum______________ + _metile_register_sum_______________;\n float _metile_register_sum________________________ = _metile_register_sum________________ + _metile_register_sum_________________;\n float _metile_register_sum_________________________ = _metile_register_sum__________________ + _metile_register_sum___________________;\n float _metile_register_sum__________________________ = _metile_register_sum____________________ + _metile_register_sum_____________________;\n float _metile_register_sum___________________________ = _metile_register_sum______________________ + _metile_register_sum_______________________;\n float _metile_register_sum____________________________ = _metile_register_sum________________________ + _metile_register_sum_________________________;\n float _metile_register_sum_____________________________ = _metile_register_sum__________________________ + _metile_register_sum___________________________;\n float _metile_register_sum______________________________ = _metile_register_sum____________________________ + _metile_register_sum_____________________________;\n float v23 = simd_sum(_metile_register_sum______________________________);\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v32_r16 = _metile_register_index________________ >= 0;\n bool _metile_v32_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v32_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v32_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v32_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v32_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v32_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v32_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v32_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v32_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v32_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v32_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v32_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v32_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v32_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v32_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v33_r8 = _metile_register_index________ < 1024;\n bool _metile_v33_r9 = _metile_register_index_________ < 1024;\n bool _metile_v33_r10 = _metile_register_index__________ < 1024;\n bool _metile_v33_r11 = _metile_register_index___________ < 1024;\n bool _metile_v33_r12 = _metile_register_index____________ < 1024;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v33_r14 = _metile_register_index______________ < 1024;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v33_r16 = _metile_register_index________________ < 1024;\n bool _metile_v33_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v33_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v33_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v33_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v33_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v33_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v33_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v33_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v33_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v33_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v33_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v33_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v33_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v33_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v33_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n bool _metile_v34_r16 = _metile_v32_r16 & _metile_v33_r16;\n bool _metile_v34_r17 = _metile_v32_r17 & _metile_v33_r17;\n bool _metile_v34_r18 = _metile_v32_r18 & _metile_v33_r18;\n bool _metile_v34_r19 = _metile_v32_r19 & _metile_v33_r19;\n bool _metile_v34_r20 = _metile_v32_r20 & _metile_v33_r20;\n bool _metile_v34_r21 = _metile_v32_r21 & _metile_v33_r21;\n bool _metile_v34_r22 = _metile_v32_r22 & _metile_v33_r22;\n bool _metile_v34_r23 = _metile_v32_r23 & _metile_v33_r23;\n bool _metile_v34_r24 = _metile_v32_r24 & _metile_v33_r24;\n bool _metile_v34_r25 = _metile_v32_r25 & _metile_v33_r25;\n bool _metile_v34_r26 = _metile_v32_r26 & _metile_v33_r26;\n bool _metile_v34_r27 = _metile_v32_r27 & _metile_v33_r27;\n bool _metile_v34_r28 = _metile_v32_r28 & _metile_v33_r28;\n bool _metile_v34_r29 = _metile_v32_r29 & _metile_v33_r29;\n bool _metile_v34_r30 = _metile_v32_r30 & _metile_v33_r30;\n bool _metile_v34_r31 = _metile_v32_r31 & _metile_v33_r31;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n float _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n float _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n float _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n float _metile_v36_r8 = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n float _metile_v36_r9 = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n float _metile_v36_r10 = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n float _metile_v36_r11 = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n float _metile_v36_r12 = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n float _metile_v36_r13 = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n float _metile_v36_r14 = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n float _metile_v36_r15 = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n float _metile_v36_r16 = _metile_v34_r16 ? W[_metile_register_index________________] : static_cast(0);\n float _metile_v36_r17 = _metile_v34_r17 ? W[_metile_register_index_________________] : static_cast(0);\n float _metile_v36_r18 = _metile_v34_r18 ? W[_metile_register_index__________________] : static_cast(0);\n float _metile_v36_r19 = _metile_v34_r19 ? W[_metile_register_index___________________] : static_cast(0);\n float _metile_v36_r20 = _metile_v34_r20 ? W[_metile_register_index____________________] : static_cast(0);\n float _metile_v36_r21 = _metile_v34_r21 ? W[_metile_register_index_____________________] : static_cast(0);\n float _metile_v36_r22 = _metile_v34_r22 ? W[_metile_register_index______________________] : static_cast(0);\n float _metile_v36_r23 = _metile_v34_r23 ? W[_metile_register_index_______________________] : static_cast(0);\n float _metile_v36_r24 = _metile_v34_r24 ? W[_metile_register_index________________________] : static_cast(0);\n float _metile_v36_r25 = _metile_v34_r25 ? W[_metile_register_index_________________________] : static_cast(0);\n float _metile_v36_r26 = _metile_v34_r26 ? W[_metile_register_index__________________________] : static_cast(0);\n float _metile_v36_r27 = _metile_v34_r27 ? W[_metile_register_index___________________________] : static_cast(0);\n float _metile_v36_r28 = _metile_v34_r28 ? W[_metile_register_index____________________________] : static_cast(0);\n float _metile_v36_r29 = _metile_v34_r29 ? W[_metile_register_index_____________________________] : static_cast(0);\n float _metile_v36_r30 = _metile_v34_r30 ? W[_metile_register_index______________________________] : static_cast(0);\n float _metile_v36_r31 = _metile_v34_r31 ? W[_metile_register_index_______________________________] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v37_r16 = static_cast(_metile_v36_r16);\n float _metile_v37_r17 = static_cast(_metile_v36_r17);\n float _metile_v37_r18 = static_cast(_metile_v36_r18);\n float _metile_v37_r19 = static_cast(_metile_v36_r19);\n float _metile_v37_r20 = static_cast(_metile_v36_r20);\n float _metile_v37_r21 = static_cast(_metile_v36_r21);\n float _metile_v37_r22 = static_cast(_metile_v36_r22);\n float _metile_v37_r23 = static_cast(_metile_v36_r23);\n float _metile_v37_r24 = static_cast(_metile_v36_r24);\n float _metile_v37_r25 = static_cast(_metile_v36_r25);\n float _metile_v37_r26 = static_cast(_metile_v36_r26);\n float _metile_v37_r27 = static_cast(_metile_v36_r27);\n float _metile_v37_r28 = static_cast(_metile_v36_r28);\n float _metile_v37_r29 = static_cast(_metile_v36_r29);\n float _metile_v37_r30 = static_cast(_metile_v36_r30);\n float _metile_v37_r31 = static_cast(_metile_v36_r31);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v38_r16 = _metile_v21_r16 * v29;\n float _metile_v38_r17 = _metile_v21_r17 * v29;\n float _metile_v38_r18 = _metile_v21_r18 * v29;\n float _metile_v38_r19 = _metile_v21_r19 * v29;\n float _metile_v38_r20 = _metile_v21_r20 * v29;\n float _metile_v38_r21 = _metile_v21_r21 * v29;\n float _metile_v38_r22 = _metile_v21_r22 * v29;\n float _metile_v38_r23 = _metile_v21_r23 * v29;\n float _metile_v38_r24 = _metile_v21_r24 * v29;\n float _metile_v38_r25 = _metile_v21_r25 * v29;\n float _metile_v38_r26 = _metile_v21_r26 * v29;\n float _metile_v38_r27 = _metile_v21_r27 * v29;\n float _metile_v38_r28 = _metile_v21_r28 * v29;\n float _metile_v38_r29 = _metile_v21_r29 * v29;\n float _metile_v38_r30 = _metile_v21_r30 * v29;\n float _metile_v38_r31 = _metile_v21_r31 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n float _metile_v39_r16 = _metile_v38_r16 * _metile_v37_r16;\n float _metile_v39_r17 = _metile_v38_r17 * _metile_v37_r17;\n float _metile_v39_r18 = _metile_v38_r18 * _metile_v37_r18;\n float _metile_v39_r19 = _metile_v38_r19 * _metile_v37_r19;\n float _metile_v39_r20 = _metile_v38_r20 * _metile_v37_r20;\n float _metile_v39_r21 = _metile_v38_r21 * _metile_v37_r21;\n float _metile_v39_r22 = _metile_v38_r22 * _metile_v37_r22;\n float _metile_v39_r23 = _metile_v38_r23 * _metile_v37_r23;\n float _metile_v39_r24 = _metile_v38_r24 * _metile_v37_r24;\n float _metile_v39_r25 = _metile_v38_r25 * _metile_v37_r25;\n float _metile_v39_r26 = _metile_v38_r26 * _metile_v37_r26;\n float _metile_v39_r27 = _metile_v38_r27 * _metile_v37_r27;\n float _metile_v39_r28 = _metile_v38_r28 * _metile_v37_r28;\n float _metile_v39_r29 = _metile_v38_r29 * _metile_v37_r29;\n float _metile_v39_r30 = _metile_v38_r30 * _metile_v37_r30;\n float _metile_v39_r31 = _metile_v38_r31 * _metile_v37_r31;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v41_r16 = _metile_register_index________________ >= 0;\n bool _metile_v41_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v41_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v41_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v41_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v41_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v41_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v41_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v41_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v41_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v41_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v41_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v41_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v41_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v41_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v41_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v42_r8 = _metile_register_index________ < 1024;\n bool _metile_v42_r9 = _metile_register_index_________ < 1024;\n bool _metile_v42_r10 = _metile_register_index__________ < 1024;\n bool _metile_v42_r11 = _metile_register_index___________ < 1024;\n bool _metile_v42_r12 = _metile_register_index____________ < 1024;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v42_r14 = _metile_register_index______________ < 1024;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v42_r16 = _metile_register_index________________ < 1024;\n bool _metile_v42_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v42_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v42_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v42_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v42_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v42_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v42_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v42_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v42_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v42_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v42_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v42_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v42_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v42_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v42_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n bool _metile_v43_r16 = _metile_v41_r16 & _metile_v42_r16;\n bool _metile_v43_r17 = _metile_v41_r17 & _metile_v42_r17;\n bool _metile_v43_r18 = _metile_v41_r18 & _metile_v42_r18;\n bool _metile_v43_r19 = _metile_v41_r19 & _metile_v42_r19;\n bool _metile_v43_r20 = _metile_v41_r20 & _metile_v42_r20;\n bool _metile_v43_r21 = _metile_v41_r21 & _metile_v42_r21;\n bool _metile_v43_r22 = _metile_v41_r22 & _metile_v42_r22;\n bool _metile_v43_r23 = _metile_v41_r23 & _metile_v42_r23;\n bool _metile_v43_r24 = _metile_v41_r24 & _metile_v42_r24;\n bool _metile_v43_r25 = _metile_v41_r25 & _metile_v42_r25;\n bool _metile_v43_r26 = _metile_v41_r26 & _metile_v42_r26;\n bool _metile_v43_r27 = _metile_v41_r27 & _metile_v42_r27;\n bool _metile_v43_r28 = _metile_v41_r28 & _metile_v42_r28;\n bool _metile_v43_r29 = _metile_v41_r29 & _metile_v42_r29;\n bool _metile_v43_r30 = _metile_v41_r30 & _metile_v42_r30;\n bool _metile_v43_r31 = _metile_v41_r31 & _metile_v42_r31;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n int _off__metile_v44_r16 = v9 + _metile_register_index________________;\n int _off__metile_v44_r17 = v9 + _metile_register_index_________________;\n int _off__metile_v44_r18 = v9 + _metile_register_index__________________;\n int _off__metile_v44_r19 = v9 + _metile_register_index___________________;\n int _off__metile_v44_r20 = v9 + _metile_register_index____________________;\n int _off__metile_v44_r21 = v9 + _metile_register_index_____________________;\n int _off__metile_v44_r22 = v9 + _metile_register_index______________________;\n int _off__metile_v44_r23 = v9 + _metile_register_index_______________________;\n int _off__metile_v44_r24 = v9 + _metile_register_index________________________;\n int _off__metile_v44_r25 = v9 + _metile_register_index_________________________;\n int _off__metile_v44_r26 = v9 + _metile_register_index__________________________;\n int _off__metile_v44_r27 = v9 + _metile_register_index___________________________;\n int _off__metile_v44_r28 = v9 + _metile_register_index____________________________;\n int _off__metile_v44_r29 = v9 + _metile_register_index_____________________________;\n int _off__metile_v44_r30 = v9 + _metile_register_index______________________________;\n int _off__metile_v44_r31 = v9 + _metile_register_index_______________________________;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = _metile_v39_r8; }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = _metile_v39_r9; }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = _metile_v39_r10; }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = _metile_v39_r11; }\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = _metile_v39_r12; }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = _metile_v39_r13; }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = _metile_v39_r14; }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = _metile_v39_r15; }\n if (_metile_v43_r16) { Out[_off__metile_v44_r16] = _metile_v39_r16; }\n if (_metile_v43_r17) { Out[_off__metile_v44_r17] = _metile_v39_r17; }\n if (_metile_v43_r18) { Out[_off__metile_v44_r18] = _metile_v39_r18; }\n if (_metile_v43_r19) { Out[_off__metile_v44_r19] = _metile_v39_r19; }\n if (_metile_v43_r20) { Out[_off__metile_v44_r20] = _metile_v39_r20; }\n if (_metile_v43_r21) { Out[_off__metile_v44_r21] = _metile_v39_r21; }\n if (_metile_v43_r22) { Out[_off__metile_v44_r22] = _metile_v39_r22; }\n if (_metile_v43_r23) { Out[_off__metile_v44_r23] = _metile_v39_r23; }\n if (_metile_v43_r24) { Out[_off__metile_v44_r24] = _metile_v39_r24; }\n if (_metile_v43_r25) { Out[_off__metile_v44_r25] = _metile_v39_r25; }\n if (_metile_v43_r26) { Out[_off__metile_v44_r26] = _metile_v39_r26; }\n if (_metile_v43_r27) { Out[_off__metile_v44_r27] = _metile_v39_r27; }\n if (_metile_v43_r28) { Out[_off__metile_v44_r28] = _metile_v39_r28; }\n if (_metile_v43_r29) { Out[_off__metile_v44_r29] = _metile_v39_r29; }\n if (_metile_v43_r30) { Out[_off__metile_v44_r30] = _metile_v39_r30; }\n if (_metile_v43_r31) { Out[_off__metile_v44_r31] = _metile_v39_r31; }\n}", "source_sha256": "ad4bf6c168b8be3158fdb141b4692d160c0a3ff22ae8336b2fe017e3812a192f", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 32, 1, 1 ], "is_gemm": false, "prefer_ordered": false, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 32, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 32 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 32, "threads": 32, "scratch": null, "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 615, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.417, "control": 199.125, "speedup": 1.008651737185754 }, "gpu_us": { "candidate": 2.6249908842146397, "control": 2.2916938178241253, "speedup": 0.8730292480652815 } } }, { "frozen_register4": { "pairs": 615, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.083, "control": 200.125, "speedup": 1.0103088099433066 }, "gpu_us": { "candidate": 2.6249908842146397, "control": 2.3333122953772545, "speedup": 0.8888839612391068 } } }, { "frozen_register4": { "pairs": 525, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.125, "control": 200.875, "speedup": 0.9938157081014224 }, "gpu_us": { "candidate": 2.6249908842146397, "control": 2.3333122953772545, "speedup": 0.8888839612391068 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0042312827329165, "round_speedups": [ 1.008651737185754, 1.0103088099433066, 0.9938157081014224 ], "candidate": 199.1975206439868, "control": 200.04038167352743 }, "gpu_us": { "speedup": 0.8835673200656701, "round_speedups": [ 0.8730292480652815, 0.8888839612391068, 0.8888839612391068 ], "candidate": 2.6249908842146397, "control": 2.3193561607623425 } } } }, { "name": "float32_32x1024", "dtype": "float32", "batches": 32, "width": 1024, "status": "measured", "variant": { "name": "register32_blocked4", "elements_per_thread": 32, "layout": "blocked4" }, "input_sha256": "0fc05dcd6172e2eebffb6471582bea984c5a888fc3b3a095d91b296908e6567b", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 31;\n int _metile_register_index = int((((_metile_bounded_thread >> 5) & 1u) << 0) | (((_metile_bounded_thread >> 6) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 7) & 1u) << 7) | (((_metile_bounded_thread >> 8) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 32;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 5) & 1u) << 0) | (((_metile_register_packed_ >> 6) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 7) & 1u) << 7) | (((_metile_register_packed_ >> 8) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 64;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 5) & 1u) << 0) | (((_metile_register_packed__ >> 6) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 7) & 1u) << 7) | (((_metile_register_packed__ >> 8) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 96;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 5) & 1u) << 0) | (((_metile_register_packed___ >> 6) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 7) & 1u) << 7) | (((_metile_register_packed___ >> 8) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 128;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 5) & 1u) << 0) | (((_metile_register_packed____ >> 6) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 7) & 1u) << 7) | (((_metile_register_packed____ >> 8) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 160;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 5) & 1u) << 0) | (((_metile_register_packed_____ >> 6) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 7) & 1u) << 7) | (((_metile_register_packed_____ >> 8) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 192;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 5) & 1u) << 0) | (((_metile_register_packed______ >> 6) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 7) & 1u) << 7) | (((_metile_register_packed______ >> 8) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 224;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 5) & 1u) << 0) | (((_metile_register_packed_______ >> 6) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 7) & 1u) << 7) | (((_metile_register_packed_______ >> 8) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n int _metile_register_packed________ = _metile_bounded_thread + 256;\n int _metile_register_index________ = int((((_metile_register_packed________ >> 5) & 1u) << 0) | (((_metile_register_packed________ >> 6) & 1u) << 1) | (((_metile_register_packed________ >> 0) & 1u) << 2) | (((_metile_register_packed________ >> 1) & 1u) << 3) | (((_metile_register_packed________ >> 2) & 1u) << 4) | (((_metile_register_packed________ >> 3) & 1u) << 5) | (((_metile_register_packed________ >> 4) & 1u) << 6) | (((_metile_register_packed________ >> 7) & 1u) << 7) | (((_metile_register_packed________ >> 8) & 1u) << 8) | (((_metile_register_packed________ >> 9) & 1u) << 9));\n int _metile_register_packed_________ = _metile_bounded_thread + 288;\n int _metile_register_index_________ = int((((_metile_register_packed_________ >> 5) & 1u) << 0) | (((_metile_register_packed_________ >> 6) & 1u) << 1) | (((_metile_register_packed_________ >> 0) & 1u) << 2) | (((_metile_register_packed_________ >> 1) & 1u) << 3) | (((_metile_register_packed_________ >> 2) & 1u) << 4) | (((_metile_register_packed_________ >> 3) & 1u) << 5) | (((_metile_register_packed_________ >> 4) & 1u) << 6) | (((_metile_register_packed_________ >> 7) & 1u) << 7) | (((_metile_register_packed_________ >> 8) & 1u) << 8) | (((_metile_register_packed_________ >> 9) & 1u) << 9));\n int _metile_register_packed__________ = _metile_bounded_thread + 320;\n int _metile_register_index__________ = int((((_metile_register_packed__________ >> 5) & 1u) << 0) | (((_metile_register_packed__________ >> 6) & 1u) << 1) | (((_metile_register_packed__________ >> 0) & 1u) << 2) | (((_metile_register_packed__________ >> 1) & 1u) << 3) | (((_metile_register_packed__________ >> 2) & 1u) << 4) | (((_metile_register_packed__________ >> 3) & 1u) << 5) | (((_metile_register_packed__________ >> 4) & 1u) << 6) | (((_metile_register_packed__________ >> 7) & 1u) << 7) | (((_metile_register_packed__________ >> 8) & 1u) << 8) | (((_metile_register_packed__________ >> 9) & 1u) << 9));\n int _metile_register_packed___________ = _metile_bounded_thread + 352;\n int _metile_register_index___________ = int((((_metile_register_packed___________ >> 5) & 1u) << 0) | (((_metile_register_packed___________ >> 6) & 1u) << 1) | (((_metile_register_packed___________ >> 0) & 1u) << 2) | (((_metile_register_packed___________ >> 1) & 1u) << 3) | (((_metile_register_packed___________ >> 2) & 1u) << 4) | (((_metile_register_packed___________ >> 3) & 1u) << 5) | (((_metile_register_packed___________ >> 4) & 1u) << 6) | (((_metile_register_packed___________ >> 7) & 1u) << 7) | (((_metile_register_packed___________ >> 8) & 1u) << 8) | (((_metile_register_packed___________ >> 9) & 1u) << 9));\n int _metile_register_packed____________ = _metile_bounded_thread + 384;\n int _metile_register_index____________ = int((((_metile_register_packed____________ >> 5) & 1u) << 0) | (((_metile_register_packed____________ >> 6) & 1u) << 1) | (((_metile_register_packed____________ >> 0) & 1u) << 2) | (((_metile_register_packed____________ >> 1) & 1u) << 3) | (((_metile_register_packed____________ >> 2) & 1u) << 4) | (((_metile_register_packed____________ >> 3) & 1u) << 5) | (((_metile_register_packed____________ >> 4) & 1u) << 6) | (((_metile_register_packed____________ >> 7) & 1u) << 7) | (((_metile_register_packed____________ >> 8) & 1u) << 8) | (((_metile_register_packed____________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________ = _metile_bounded_thread + 416;\n int _metile_register_index_____________ = int((((_metile_register_packed_____________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________ >> 9) & 1u) << 9));\n int _metile_register_packed______________ = _metile_bounded_thread + 448;\n int _metile_register_index______________ = int((((_metile_register_packed______________ >> 5) & 1u) << 0) | (((_metile_register_packed______________ >> 6) & 1u) << 1) | (((_metile_register_packed______________ >> 0) & 1u) << 2) | (((_metile_register_packed______________ >> 1) & 1u) << 3) | (((_metile_register_packed______________ >> 2) & 1u) << 4) | (((_metile_register_packed______________ >> 3) & 1u) << 5) | (((_metile_register_packed______________ >> 4) & 1u) << 6) | (((_metile_register_packed______________ >> 7) & 1u) << 7) | (((_metile_register_packed______________ >> 8) & 1u) << 8) | (((_metile_register_packed______________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________ = _metile_bounded_thread + 480;\n int _metile_register_index_______________ = int((((_metile_register_packed_______________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________ >> 9) & 1u) << 9));\n int _metile_register_packed________________ = _metile_bounded_thread + 512;\n int _metile_register_index________________ = int((((_metile_register_packed________________ >> 5) & 1u) << 0) | (((_metile_register_packed________________ >> 6) & 1u) << 1) | (((_metile_register_packed________________ >> 0) & 1u) << 2) | (((_metile_register_packed________________ >> 1) & 1u) << 3) | (((_metile_register_packed________________ >> 2) & 1u) << 4) | (((_metile_register_packed________________ >> 3) & 1u) << 5) | (((_metile_register_packed________________ >> 4) & 1u) << 6) | (((_metile_register_packed________________ >> 7) & 1u) << 7) | (((_metile_register_packed________________ >> 8) & 1u) << 8) | (((_metile_register_packed________________ >> 9) & 1u) << 9));\n int _metile_register_packed_________________ = _metile_bounded_thread + 544;\n int _metile_register_index_________________ = int((((_metile_register_packed_________________ >> 5) & 1u) << 0) | (((_metile_register_packed_________________ >> 6) & 1u) << 1) | (((_metile_register_packed_________________ >> 0) & 1u) << 2) | (((_metile_register_packed_________________ >> 1) & 1u) << 3) | (((_metile_register_packed_________________ >> 2) & 1u) << 4) | (((_metile_register_packed_________________ >> 3) & 1u) << 5) | (((_metile_register_packed_________________ >> 4) & 1u) << 6) | (((_metile_register_packed_________________ >> 7) & 1u) << 7) | (((_metile_register_packed_________________ >> 8) & 1u) << 8) | (((_metile_register_packed_________________ >> 9) & 1u) << 9));\n int _metile_register_packed__________________ = _metile_bounded_thread + 576;\n int _metile_register_index__________________ = int((((_metile_register_packed__________________ >> 5) & 1u) << 0) | (((_metile_register_packed__________________ >> 6) & 1u) << 1) | (((_metile_register_packed__________________ >> 0) & 1u) << 2) | (((_metile_register_packed__________________ >> 1) & 1u) << 3) | (((_metile_register_packed__________________ >> 2) & 1u) << 4) | (((_metile_register_packed__________________ >> 3) & 1u) << 5) | (((_metile_register_packed__________________ >> 4) & 1u) << 6) | (((_metile_register_packed__________________ >> 7) & 1u) << 7) | (((_metile_register_packed__________________ >> 8) & 1u) << 8) | (((_metile_register_packed__________________ >> 9) & 1u) << 9));\n int _metile_register_packed___________________ = _metile_bounded_thread + 608;\n int _metile_register_index___________________ = int((((_metile_register_packed___________________ >> 5) & 1u) << 0) | (((_metile_register_packed___________________ >> 6) & 1u) << 1) | (((_metile_register_packed___________________ >> 0) & 1u) << 2) | (((_metile_register_packed___________________ >> 1) & 1u) << 3) | (((_metile_register_packed___________________ >> 2) & 1u) << 4) | (((_metile_register_packed___________________ >> 3) & 1u) << 5) | (((_metile_register_packed___________________ >> 4) & 1u) << 6) | (((_metile_register_packed___________________ >> 7) & 1u) << 7) | (((_metile_register_packed___________________ >> 8) & 1u) << 8) | (((_metile_register_packed___________________ >> 9) & 1u) << 9));\n int _metile_register_packed____________________ = _metile_bounded_thread + 640;\n int _metile_register_index____________________ = int((((_metile_register_packed____________________ >> 5) & 1u) << 0) | (((_metile_register_packed____________________ >> 6) & 1u) << 1) | (((_metile_register_packed____________________ >> 0) & 1u) << 2) | (((_metile_register_packed____________________ >> 1) & 1u) << 3) | (((_metile_register_packed____________________ >> 2) & 1u) << 4) | (((_metile_register_packed____________________ >> 3) & 1u) << 5) | (((_metile_register_packed____________________ >> 4) & 1u) << 6) | (((_metile_register_packed____________________ >> 7) & 1u) << 7) | (((_metile_register_packed____________________ >> 8) & 1u) << 8) | (((_metile_register_packed____________________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________________ = _metile_bounded_thread + 672;\n int _metile_register_index_____________________ = int((((_metile_register_packed_____________________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________________ >> 9) & 1u) << 9));\n int _metile_register_packed______________________ = _metile_bounded_thread + 704;\n int _metile_register_index______________________ = int((((_metile_register_packed______________________ >> 5) & 1u) << 0) | (((_metile_register_packed______________________ >> 6) & 1u) << 1) | (((_metile_register_packed______________________ >> 0) & 1u) << 2) | (((_metile_register_packed______________________ >> 1) & 1u) << 3) | (((_metile_register_packed______________________ >> 2) & 1u) << 4) | (((_metile_register_packed______________________ >> 3) & 1u) << 5) | (((_metile_register_packed______________________ >> 4) & 1u) << 6) | (((_metile_register_packed______________________ >> 7) & 1u) << 7) | (((_metile_register_packed______________________ >> 8) & 1u) << 8) | (((_metile_register_packed______________________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________________ = _metile_bounded_thread + 736;\n int _metile_register_index_______________________ = int((((_metile_register_packed_______________________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________________ >> 9) & 1u) << 9));\n int _metile_register_packed________________________ = _metile_bounded_thread + 768;\n int _metile_register_index________________________ = int((((_metile_register_packed________________________ >> 5) & 1u) << 0) | (((_metile_register_packed________________________ >> 6) & 1u) << 1) | (((_metile_register_packed________________________ >> 0) & 1u) << 2) | (((_metile_register_packed________________________ >> 1) & 1u) << 3) | (((_metile_register_packed________________________ >> 2) & 1u) << 4) | (((_metile_register_packed________________________ >> 3) & 1u) << 5) | (((_metile_register_packed________________________ >> 4) & 1u) << 6) | (((_metile_register_packed________________________ >> 7) & 1u) << 7) | (((_metile_register_packed________________________ >> 8) & 1u) << 8) | (((_metile_register_packed________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_________________________ = _metile_bounded_thread + 800;\n int _metile_register_index_________________________ = int((((_metile_register_packed_________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_________________________ >> 9) & 1u) << 9));\n int _metile_register_packed__________________________ = _metile_bounded_thread + 832;\n int _metile_register_index__________________________ = int((((_metile_register_packed__________________________ >> 5) & 1u) << 0) | (((_metile_register_packed__________________________ >> 6) & 1u) << 1) | (((_metile_register_packed__________________________ >> 0) & 1u) << 2) | (((_metile_register_packed__________________________ >> 1) & 1u) << 3) | (((_metile_register_packed__________________________ >> 2) & 1u) << 4) | (((_metile_register_packed__________________________ >> 3) & 1u) << 5) | (((_metile_register_packed__________________________ >> 4) & 1u) << 6) | (((_metile_register_packed__________________________ >> 7) & 1u) << 7) | (((_metile_register_packed__________________________ >> 8) & 1u) << 8) | (((_metile_register_packed__________________________ >> 9) & 1u) << 9));\n int _metile_register_packed___________________________ = _metile_bounded_thread + 864;\n int _metile_register_index___________________________ = int((((_metile_register_packed___________________________ >> 5) & 1u) << 0) | (((_metile_register_packed___________________________ >> 6) & 1u) << 1) | (((_metile_register_packed___________________________ >> 0) & 1u) << 2) | (((_metile_register_packed___________________________ >> 1) & 1u) << 3) | (((_metile_register_packed___________________________ >> 2) & 1u) << 4) | (((_metile_register_packed___________________________ >> 3) & 1u) << 5) | (((_metile_register_packed___________________________ >> 4) & 1u) << 6) | (((_metile_register_packed___________________________ >> 7) & 1u) << 7) | (((_metile_register_packed___________________________ >> 8) & 1u) << 8) | (((_metile_register_packed___________________________ >> 9) & 1u) << 9));\n int _metile_register_packed____________________________ = _metile_bounded_thread + 896;\n int _metile_register_index____________________________ = int((((_metile_register_packed____________________________ >> 5) & 1u) << 0) | (((_metile_register_packed____________________________ >> 6) & 1u) << 1) | (((_metile_register_packed____________________________ >> 0) & 1u) << 2) | (((_metile_register_packed____________________________ >> 1) & 1u) << 3) | (((_metile_register_packed____________________________ >> 2) & 1u) << 4) | (((_metile_register_packed____________________________ >> 3) & 1u) << 5) | (((_metile_register_packed____________________________ >> 4) & 1u) << 6) | (((_metile_register_packed____________________________ >> 7) & 1u) << 7) | (((_metile_register_packed____________________________ >> 8) & 1u) << 8) | (((_metile_register_packed____________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________________________ = _metile_bounded_thread + 928;\n int _metile_register_index_____________________________ = int((((_metile_register_packed_____________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________________________ >> 9) & 1u) << 9));\n int _metile_register_packed______________________________ = _metile_bounded_thread + 960;\n int _metile_register_index______________________________ = int((((_metile_register_packed______________________________ >> 5) & 1u) << 0) | (((_metile_register_packed______________________________ >> 6) & 1u) << 1) | (((_metile_register_packed______________________________ >> 0) & 1u) << 2) | (((_metile_register_packed______________________________ >> 1) & 1u) << 3) | (((_metile_register_packed______________________________ >> 2) & 1u) << 4) | (((_metile_register_packed______________________________ >> 3) & 1u) << 5) | (((_metile_register_packed______________________________ >> 4) & 1u) << 6) | (((_metile_register_packed______________________________ >> 7) & 1u) << 7) | (((_metile_register_packed______________________________ >> 8) & 1u) << 8) | (((_metile_register_packed______________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________________________ = _metile_bounded_thread + 992;\n int _metile_register_index_______________________________ = int((((_metile_register_packed_______________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________________________ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v16_r16 = _metile_register_index________________ >= 0;\n bool _metile_v16_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v16_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v16_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v16_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v16_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v16_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v16_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v16_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v16_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v16_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v16_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v16_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v16_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v16_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v16_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v17_r8 = _metile_register_index________ < 1024;\n bool _metile_v17_r9 = _metile_register_index_________ < 1024;\n bool _metile_v17_r10 = _metile_register_index__________ < 1024;\n bool _metile_v17_r11 = _metile_register_index___________ < 1024;\n bool _metile_v17_r12 = _metile_register_index____________ < 1024;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v17_r14 = _metile_register_index______________ < 1024;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v17_r16 = _metile_register_index________________ < 1024;\n bool _metile_v17_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v17_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v17_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v17_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v17_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v17_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v17_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v17_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v17_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v17_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v17_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v17_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v17_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v17_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v17_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n bool _metile_v18_r16 = _metile_v16_r16 & _metile_v17_r16;\n bool _metile_v18_r17 = _metile_v16_r17 & _metile_v17_r17;\n bool _metile_v18_r18 = _metile_v16_r18 & _metile_v17_r18;\n bool _metile_v18_r19 = _metile_v16_r19 & _metile_v17_r19;\n bool _metile_v18_r20 = _metile_v16_r20 & _metile_v17_r20;\n bool _metile_v18_r21 = _metile_v16_r21 & _metile_v17_r21;\n bool _metile_v18_r22 = _metile_v16_r22 & _metile_v17_r22;\n bool _metile_v18_r23 = _metile_v16_r23 & _metile_v17_r23;\n bool _metile_v18_r24 = _metile_v16_r24 & _metile_v17_r24;\n bool _metile_v18_r25 = _metile_v16_r25 & _metile_v17_r25;\n bool _metile_v18_r26 = _metile_v16_r26 & _metile_v17_r26;\n bool _metile_v18_r27 = _metile_v16_r27 & _metile_v17_r27;\n bool _metile_v18_r28 = _metile_v16_r28 & _metile_v17_r28;\n bool _metile_v18_r29 = _metile_v16_r29 & _metile_v17_r29;\n bool _metile_v18_r30 = _metile_v16_r30 & _metile_v17_r30;\n bool _metile_v18_r31 = _metile_v16_r31 & _metile_v17_r31;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n int _off__metile_v19_r16 = v2 + _metile_register_index________________;\n int _off__metile_v19_r17 = v2 + _metile_register_index_________________;\n int _off__metile_v19_r18 = v2 + _metile_register_index__________________;\n int _off__metile_v19_r19 = v2 + _metile_register_index___________________;\n int _off__metile_v19_r20 = v2 + _metile_register_index____________________;\n int _off__metile_v19_r21 = v2 + _metile_register_index_____________________;\n int _off__metile_v19_r22 = v2 + _metile_register_index______________________;\n int _off__metile_v19_r23 = v2 + _metile_register_index_______________________;\n int _off__metile_v19_r24 = v2 + _metile_register_index________________________;\n int _off__metile_v19_r25 = v2 + _metile_register_index_________________________;\n int _off__metile_v19_r26 = v2 + _metile_register_index__________________________;\n int _off__metile_v19_r27 = v2 + _metile_register_index___________________________;\n int _off__metile_v19_r28 = v2 + _metile_register_index____________________________;\n int _off__metile_v19_r29 = v2 + _metile_register_index_____________________________;\n int _off__metile_v19_r30 = v2 + _metile_register_index______________________________;\n int _off__metile_v19_r31 = v2 + _metile_register_index_______________________________;\n float4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = float4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n float _metile_v20_r0 = _metile_vector_load[0];\n float _metile_v20_r1 = _metile_vector_load[1];\n float _metile_v20_r2 = _metile_vector_load[2];\n float _metile_v20_r3 = _metile_vector_load[3];\n float4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = float4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n float _metile_v20_r4 = _metile_vector_load_[0];\n float _metile_v20_r5 = _metile_vector_load_[1];\n float _metile_v20_r6 = _metile_vector_load_[2];\n float _metile_v20_r7 = _metile_vector_load_[3];\n float4 _metile_vector_load__;\n if ((_metile_v18_r8) && (_metile_v18_r9) && (_metile_v18_r10) && (_metile_v18_r11) && (long(_off__metile_v19_r9) == long(_off__metile_v19_r8) + 1) && (long(_off__metile_v19_r10) == long(_off__metile_v19_r8) + 2) && (long(_off__metile_v19_r11) == long(_off__metile_v19_r8) + 3)) {\n _metile_vector_load__ = float4(*reinterpret_cast(X + _off__metile_v19_r8));\n } else {\n _metile_vector_load__[0] = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n _metile_vector_load__[1] = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n _metile_vector_load__[2] = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n _metile_vector_load__[3] = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n }\n float _metile_v20_r8 = _metile_vector_load__[0];\n float _metile_v20_r9 = _metile_vector_load__[1];\n float _metile_v20_r10 = _metile_vector_load__[2];\n float _metile_v20_r11 = _metile_vector_load__[3];\n float4 _metile_vector_load___;\n if ((_metile_v18_r12) && (_metile_v18_r13) && (_metile_v18_r14) && (_metile_v18_r15) && (long(_off__metile_v19_r13) == long(_off__metile_v19_r12) + 1) && (long(_off__metile_v19_r14) == long(_off__metile_v19_r12) + 2) && (long(_off__metile_v19_r15) == long(_off__metile_v19_r12) + 3)) {\n _metile_vector_load___ = float4(*reinterpret_cast(X + _off__metile_v19_r12));\n } else {\n _metile_vector_load___[0] = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n _metile_vector_load___[1] = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n _metile_vector_load___[2] = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n _metile_vector_load___[3] = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n }\n float _metile_v20_r12 = _metile_vector_load___[0];\n float _metile_v20_r13 = _metile_vector_load___[1];\n float _metile_v20_r14 = _metile_vector_load___[2];\n float _metile_v20_r15 = _metile_vector_load___[3];\n float4 _metile_vector_load____;\n if ((_metile_v18_r16) && (_metile_v18_r17) && (_metile_v18_r18) && (_metile_v18_r19) && (long(_off__metile_v19_r17) == long(_off__metile_v19_r16) + 1) && (long(_off__metile_v19_r18) == long(_off__metile_v19_r16) + 2) && (long(_off__metile_v19_r19) == long(_off__metile_v19_r16) + 3)) {\n _metile_vector_load____ = float4(*reinterpret_cast(X + _off__metile_v19_r16));\n } else {\n _metile_vector_load____[0] = _metile_v18_r16 ? X[_off__metile_v19_r16] : static_cast(0);\n _metile_vector_load____[1] = _metile_v18_r17 ? X[_off__metile_v19_r17] : static_cast(0);\n _metile_vector_load____[2] = _metile_v18_r18 ? X[_off__metile_v19_r18] : static_cast(0);\n _metile_vector_load____[3] = _metile_v18_r19 ? X[_off__metile_v19_r19] : static_cast(0);\n }\n float _metile_v20_r16 = _metile_vector_load____[0];\n float _metile_v20_r17 = _metile_vector_load____[1];\n float _metile_v20_r18 = _metile_vector_load____[2];\n float _metile_v20_r19 = _metile_vector_load____[3];\n float4 _metile_vector_load_____;\n if ((_metile_v18_r20) && (_metile_v18_r21) && (_metile_v18_r22) && (_metile_v18_r23) && (long(_off__metile_v19_r21) == long(_off__metile_v19_r20) + 1) && (long(_off__metile_v19_r22) == long(_off__metile_v19_r20) + 2) && (long(_off__metile_v19_r23) == long(_off__metile_v19_r20) + 3)) {\n _metile_vector_load_____ = float4(*reinterpret_cast(X + _off__metile_v19_r20));\n } else {\n _metile_vector_load_____[0] = _metile_v18_r20 ? X[_off__metile_v19_r20] : static_cast(0);\n _metile_vector_load_____[1] = _metile_v18_r21 ? X[_off__metile_v19_r21] : static_cast(0);\n _metile_vector_load_____[2] = _metile_v18_r22 ? X[_off__metile_v19_r22] : static_cast(0);\n _metile_vector_load_____[3] = _metile_v18_r23 ? X[_off__metile_v19_r23] : static_cast(0);\n }\n float _metile_v20_r20 = _metile_vector_load_____[0];\n float _metile_v20_r21 = _metile_vector_load_____[1];\n float _metile_v20_r22 = _metile_vector_load_____[2];\n float _metile_v20_r23 = _metile_vector_load_____[3];\n float4 _metile_vector_load______;\n if ((_metile_v18_r24) && (_metile_v18_r25) && (_metile_v18_r26) && (_metile_v18_r27) && (long(_off__metile_v19_r25) == long(_off__metile_v19_r24) + 1) && (long(_off__metile_v19_r26) == long(_off__metile_v19_r24) + 2) && (long(_off__metile_v19_r27) == long(_off__metile_v19_r24) + 3)) {\n _metile_vector_load______ = float4(*reinterpret_cast(X + _off__metile_v19_r24));\n } else {\n _metile_vector_load______[0] = _metile_v18_r24 ? X[_off__metile_v19_r24] : static_cast(0);\n _metile_vector_load______[1] = _metile_v18_r25 ? X[_off__metile_v19_r25] : static_cast(0);\n _metile_vector_load______[2] = _metile_v18_r26 ? X[_off__metile_v19_r26] : static_cast(0);\n _metile_vector_load______[3] = _metile_v18_r27 ? X[_off__metile_v19_r27] : static_cast(0);\n }\n float _metile_v20_r24 = _metile_vector_load______[0];\n float _metile_v20_r25 = _metile_vector_load______[1];\n float _metile_v20_r26 = _metile_vector_load______[2];\n float _metile_v20_r27 = _metile_vector_load______[3];\n float4 _metile_vector_load_______;\n if ((_metile_v18_r28) && (_metile_v18_r29) && (_metile_v18_r30) && (_metile_v18_r31) && (long(_off__metile_v19_r29) == long(_off__metile_v19_r28) + 1) && (long(_off__metile_v19_r30) == long(_off__metile_v19_r28) + 2) && (long(_off__metile_v19_r31) == long(_off__metile_v19_r28) + 3)) {\n _metile_vector_load_______ = float4(*reinterpret_cast(X + _off__metile_v19_r28));\n } else {\n _metile_vector_load_______[0] = _metile_v18_r28 ? X[_off__metile_v19_r28] : static_cast(0);\n _metile_vector_load_______[1] = _metile_v18_r29 ? X[_off__metile_v19_r29] : static_cast(0);\n _metile_vector_load_______[2] = _metile_v18_r30 ? X[_off__metile_v19_r30] : static_cast(0);\n _metile_vector_load_______[3] = _metile_v18_r31 ? X[_off__metile_v19_r31] : static_cast(0);\n }\n float _metile_v20_r28 = _metile_vector_load_______[0];\n float _metile_v20_r29 = _metile_vector_load_______[1];\n float _metile_v20_r30 = _metile_vector_load_______[2];\n float _metile_v20_r31 = _metile_vector_load_______[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v21_r16 = static_cast(_metile_v20_r16);\n float _metile_v21_r17 = static_cast(_metile_v20_r17);\n float _metile_v21_r18 = static_cast(_metile_v20_r18);\n float _metile_v21_r19 = static_cast(_metile_v20_r19);\n float _metile_v21_r20 = static_cast(_metile_v20_r20);\n float _metile_v21_r21 = static_cast(_metile_v20_r21);\n float _metile_v21_r22 = static_cast(_metile_v20_r22);\n float _metile_v21_r23 = static_cast(_metile_v20_r23);\n float _metile_v21_r24 = static_cast(_metile_v20_r24);\n float _metile_v21_r25 = static_cast(_metile_v20_r25);\n float _metile_v21_r26 = static_cast(_metile_v20_r26);\n float _metile_v21_r27 = static_cast(_metile_v20_r27);\n float _metile_v21_r28 = static_cast(_metile_v20_r28);\n float _metile_v21_r29 = static_cast(_metile_v20_r29);\n float _metile_v21_r30 = static_cast(_metile_v20_r30);\n float _metile_v21_r31 = static_cast(_metile_v20_r31);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_v22_r16 = _metile_v21_r16 * _metile_v21_r16;\n float _metile_v22_r17 = _metile_v21_r17 * _metile_v21_r17;\n float _metile_v22_r18 = _metile_v21_r18 * _metile_v21_r18;\n float _metile_v22_r19 = _metile_v21_r19 * _metile_v21_r19;\n float _metile_v22_r20 = _metile_v21_r20 * _metile_v21_r20;\n float _metile_v22_r21 = _metile_v21_r21 * _metile_v21_r21;\n float _metile_v22_r22 = _metile_v21_r22 * _metile_v21_r22;\n float _metile_v22_r23 = _metile_v21_r23 * _metile_v21_r23;\n float _metile_v22_r24 = _metile_v21_r24 * _metile_v21_r24;\n float _metile_v22_r25 = _metile_v21_r25 * _metile_v21_r25;\n float _metile_v22_r26 = _metile_v21_r26 * _metile_v21_r26;\n float _metile_v22_r27 = _metile_v21_r27 * _metile_v21_r27;\n float _metile_v22_r28 = _metile_v21_r28 * _metile_v21_r28;\n float _metile_v22_r29 = _metile_v21_r29 * _metile_v21_r29;\n float _metile_v22_r30 = _metile_v21_r30 * _metile_v21_r30;\n float _metile_v22_r31 = _metile_v21_r31 * _metile_v21_r31;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_v22_r16 + _metile_v22_r17;\n float _metile_register_sum_________ = _metile_v22_r18 + _metile_v22_r19;\n float _metile_register_sum__________ = _metile_v22_r20 + _metile_v22_r21;\n float _metile_register_sum___________ = _metile_v22_r22 + _metile_v22_r23;\n float _metile_register_sum____________ = _metile_v22_r24 + _metile_v22_r25;\n float _metile_register_sum_____________ = _metile_v22_r26 + _metile_v22_r27;\n float _metile_register_sum______________ = _metile_v22_r28 + _metile_v22_r29;\n float _metile_register_sum_______________ = _metile_v22_r30 + _metile_v22_r31;\n float _metile_register_sum________________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________________ = _metile_register_sum____________ + _metile_register_sum_____________;\n float _metile_register_sum_______________________ = _metile_register_sum______________ + _metile_register_sum_______________;\n float _metile_register_sum________________________ = _metile_register_sum________________ + _metile_register_sum_________________;\n float _metile_register_sum_________________________ = _metile_register_sum__________________ + _metile_register_sum___________________;\n float _metile_register_sum__________________________ = _metile_register_sum____________________ + _metile_register_sum_____________________;\n float _metile_register_sum___________________________ = _metile_register_sum______________________ + _metile_register_sum_______________________;\n float _metile_register_sum____________________________ = _metile_register_sum________________________ + _metile_register_sum_________________________;\n float _metile_register_sum_____________________________ = _metile_register_sum__________________________ + _metile_register_sum___________________________;\n float _metile_register_sum______________________________ = _metile_register_sum____________________________ + _metile_register_sum_____________________________;\n float v23 = simd_sum(_metile_register_sum______________________________);\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v32_r16 = _metile_register_index________________ >= 0;\n bool _metile_v32_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v32_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v32_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v32_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v32_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v32_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v32_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v32_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v32_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v32_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v32_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v32_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v32_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v32_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v32_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v33_r8 = _metile_register_index________ < 1024;\n bool _metile_v33_r9 = _metile_register_index_________ < 1024;\n bool _metile_v33_r10 = _metile_register_index__________ < 1024;\n bool _metile_v33_r11 = _metile_register_index___________ < 1024;\n bool _metile_v33_r12 = _metile_register_index____________ < 1024;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v33_r14 = _metile_register_index______________ < 1024;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v33_r16 = _metile_register_index________________ < 1024;\n bool _metile_v33_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v33_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v33_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v33_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v33_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v33_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v33_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v33_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v33_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v33_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v33_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v33_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v33_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v33_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v33_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n bool _metile_v34_r16 = _metile_v32_r16 & _metile_v33_r16;\n bool _metile_v34_r17 = _metile_v32_r17 & _metile_v33_r17;\n bool _metile_v34_r18 = _metile_v32_r18 & _metile_v33_r18;\n bool _metile_v34_r19 = _metile_v32_r19 & _metile_v33_r19;\n bool _metile_v34_r20 = _metile_v32_r20 & _metile_v33_r20;\n bool _metile_v34_r21 = _metile_v32_r21 & _metile_v33_r21;\n bool _metile_v34_r22 = _metile_v32_r22 & _metile_v33_r22;\n bool _metile_v34_r23 = _metile_v32_r23 & _metile_v33_r23;\n bool _metile_v34_r24 = _metile_v32_r24 & _metile_v33_r24;\n bool _metile_v34_r25 = _metile_v32_r25 & _metile_v33_r25;\n bool _metile_v34_r26 = _metile_v32_r26 & _metile_v33_r26;\n bool _metile_v34_r27 = _metile_v32_r27 & _metile_v33_r27;\n bool _metile_v34_r28 = _metile_v32_r28 & _metile_v33_r28;\n bool _metile_v34_r29 = _metile_v32_r29 & _metile_v33_r29;\n bool _metile_v34_r30 = _metile_v32_r30 & _metile_v33_r30;\n bool _metile_v34_r31 = _metile_v32_r31 & _metile_v33_r31;\n float4 _metile_vector_load________;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load________ = float4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load________[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load________[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load________[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load________[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n float _metile_v36_r0 = _metile_vector_load________[0];\n float _metile_v36_r1 = _metile_vector_load________[1];\n float _metile_v36_r2 = _metile_vector_load________[2];\n float _metile_v36_r3 = _metile_vector_load________[3];\n float4 _metile_vector_load_________;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load_________ = float4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load_________[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load_________[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load_________[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load_________[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n float _metile_v36_r4 = _metile_vector_load_________[0];\n float _metile_v36_r5 = _metile_vector_load_________[1];\n float _metile_v36_r6 = _metile_vector_load_________[2];\n float _metile_v36_r7 = _metile_vector_load_________[3];\n float4 _metile_vector_load__________;\n if ((_metile_v34_r8) && (_metile_v34_r9) && (_metile_v34_r10) && (_metile_v34_r11) && (long(_metile_register_index_________) == long(_metile_register_index________) + 1) && (long(_metile_register_index__________) == long(_metile_register_index________) + 2) && (long(_metile_register_index___________) == long(_metile_register_index________) + 3)) {\n _metile_vector_load__________ = float4(*reinterpret_cast(W + _metile_register_index________));\n } else {\n _metile_vector_load__________[0] = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n _metile_vector_load__________[1] = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n _metile_vector_load__________[2] = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n _metile_vector_load__________[3] = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n }\n float _metile_v36_r8 = _metile_vector_load__________[0];\n float _metile_v36_r9 = _metile_vector_load__________[1];\n float _metile_v36_r10 = _metile_vector_load__________[2];\n float _metile_v36_r11 = _metile_vector_load__________[3];\n float4 _metile_vector_load___________;\n if ((_metile_v34_r12) && (_metile_v34_r13) && (_metile_v34_r14) && (_metile_v34_r15) && (long(_metile_register_index_____________) == long(_metile_register_index____________) + 1) && (long(_metile_register_index______________) == long(_metile_register_index____________) + 2) && (long(_metile_register_index_______________) == long(_metile_register_index____________) + 3)) {\n _metile_vector_load___________ = float4(*reinterpret_cast(W + _metile_register_index____________));\n } else {\n _metile_vector_load___________[0] = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n _metile_vector_load___________[1] = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n _metile_vector_load___________[2] = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n _metile_vector_load___________[3] = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n }\n float _metile_v36_r12 = _metile_vector_load___________[0];\n float _metile_v36_r13 = _metile_vector_load___________[1];\n float _metile_v36_r14 = _metile_vector_load___________[2];\n float _metile_v36_r15 = _metile_vector_load___________[3];\n float4 _metile_vector_load____________;\n if ((_metile_v34_r16) && (_metile_v34_r17) && (_metile_v34_r18) && (_metile_v34_r19) && (long(_metile_register_index_________________) == long(_metile_register_index________________) + 1) && (long(_metile_register_index__________________) == long(_metile_register_index________________) + 2) && (long(_metile_register_index___________________) == long(_metile_register_index________________) + 3)) {\n _metile_vector_load____________ = float4(*reinterpret_cast(W + _metile_register_index________________));\n } else {\n _metile_vector_load____________[0] = _metile_v34_r16 ? W[_metile_register_index________________] : static_cast(0);\n _metile_vector_load____________[1] = _metile_v34_r17 ? W[_metile_register_index_________________] : static_cast(0);\n _metile_vector_load____________[2] = _metile_v34_r18 ? W[_metile_register_index__________________] : static_cast(0);\n _metile_vector_load____________[3] = _metile_v34_r19 ? W[_metile_register_index___________________] : static_cast(0);\n }\n float _metile_v36_r16 = _metile_vector_load____________[0];\n float _metile_v36_r17 = _metile_vector_load____________[1];\n float _metile_v36_r18 = _metile_vector_load____________[2];\n float _metile_v36_r19 = _metile_vector_load____________[3];\n float4 _metile_vector_load_____________;\n if ((_metile_v34_r20) && (_metile_v34_r21) && (_metile_v34_r22) && (_metile_v34_r23) && (long(_metile_register_index_____________________) == long(_metile_register_index____________________) + 1) && (long(_metile_register_index______________________) == long(_metile_register_index____________________) + 2) && (long(_metile_register_index_______________________) == long(_metile_register_index____________________) + 3)) {\n _metile_vector_load_____________ = float4(*reinterpret_cast(W + _metile_register_index____________________));\n } else {\n _metile_vector_load_____________[0] = _metile_v34_r20 ? W[_metile_register_index____________________] : static_cast(0);\n _metile_vector_load_____________[1] = _metile_v34_r21 ? W[_metile_register_index_____________________] : static_cast(0);\n _metile_vector_load_____________[2] = _metile_v34_r22 ? W[_metile_register_index______________________] : static_cast(0);\n _metile_vector_load_____________[3] = _metile_v34_r23 ? W[_metile_register_index_______________________] : static_cast(0);\n }\n float _metile_v36_r20 = _metile_vector_load_____________[0];\n float _metile_v36_r21 = _metile_vector_load_____________[1];\n float _metile_v36_r22 = _metile_vector_load_____________[2];\n float _metile_v36_r23 = _metile_vector_load_____________[3];\n float4 _metile_vector_load______________;\n if ((_metile_v34_r24) && (_metile_v34_r25) && (_metile_v34_r26) && (_metile_v34_r27) && (long(_metile_register_index_________________________) == long(_metile_register_index________________________) + 1) && (long(_metile_register_index__________________________) == long(_metile_register_index________________________) + 2) && (long(_metile_register_index___________________________) == long(_metile_register_index________________________) + 3)) {\n _metile_vector_load______________ = float4(*reinterpret_cast(W + _metile_register_index________________________));\n } else {\n _metile_vector_load______________[0] = _metile_v34_r24 ? W[_metile_register_index________________________] : static_cast(0);\n _metile_vector_load______________[1] = _metile_v34_r25 ? W[_metile_register_index_________________________] : static_cast(0);\n _metile_vector_load______________[2] = _metile_v34_r26 ? W[_metile_register_index__________________________] : static_cast(0);\n _metile_vector_load______________[3] = _metile_v34_r27 ? W[_metile_register_index___________________________] : static_cast(0);\n }\n float _metile_v36_r24 = _metile_vector_load______________[0];\n float _metile_v36_r25 = _metile_vector_load______________[1];\n float _metile_v36_r26 = _metile_vector_load______________[2];\n float _metile_v36_r27 = _metile_vector_load______________[3];\n float4 _metile_vector_load_______________;\n if ((_metile_v34_r28) && (_metile_v34_r29) && (_metile_v34_r30) && (_metile_v34_r31) && (long(_metile_register_index_____________________________) == long(_metile_register_index____________________________) + 1) && (long(_metile_register_index______________________________) == long(_metile_register_index____________________________) + 2) && (long(_metile_register_index_______________________________) == long(_metile_register_index____________________________) + 3)) {\n _metile_vector_load_______________ = float4(*reinterpret_cast(W + _metile_register_index____________________________));\n } else {\n _metile_vector_load_______________[0] = _metile_v34_r28 ? W[_metile_register_index____________________________] : static_cast(0);\n _metile_vector_load_______________[1] = _metile_v34_r29 ? W[_metile_register_index_____________________________] : static_cast(0);\n _metile_vector_load_______________[2] = _metile_v34_r30 ? W[_metile_register_index______________________________] : static_cast(0);\n _metile_vector_load_______________[3] = _metile_v34_r31 ? W[_metile_register_index_______________________________] : static_cast(0);\n }\n float _metile_v36_r28 = _metile_vector_load_______________[0];\n float _metile_v36_r29 = _metile_vector_load_______________[1];\n float _metile_v36_r30 = _metile_vector_load_______________[2];\n float _metile_v36_r31 = _metile_vector_load_______________[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v37_r16 = static_cast(_metile_v36_r16);\n float _metile_v37_r17 = static_cast(_metile_v36_r17);\n float _metile_v37_r18 = static_cast(_metile_v36_r18);\n float _metile_v37_r19 = static_cast(_metile_v36_r19);\n float _metile_v37_r20 = static_cast(_metile_v36_r20);\n float _metile_v37_r21 = static_cast(_metile_v36_r21);\n float _metile_v37_r22 = static_cast(_metile_v36_r22);\n float _metile_v37_r23 = static_cast(_metile_v36_r23);\n float _metile_v37_r24 = static_cast(_metile_v36_r24);\n float _metile_v37_r25 = static_cast(_metile_v36_r25);\n float _metile_v37_r26 = static_cast(_metile_v36_r26);\n float _metile_v37_r27 = static_cast(_metile_v36_r27);\n float _metile_v37_r28 = static_cast(_metile_v36_r28);\n float _metile_v37_r29 = static_cast(_metile_v36_r29);\n float _metile_v37_r30 = static_cast(_metile_v36_r30);\n float _metile_v37_r31 = static_cast(_metile_v36_r31);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v38_r16 = _metile_v21_r16 * v29;\n float _metile_v38_r17 = _metile_v21_r17 * v29;\n float _metile_v38_r18 = _metile_v21_r18 * v29;\n float _metile_v38_r19 = _metile_v21_r19 * v29;\n float _metile_v38_r20 = _metile_v21_r20 * v29;\n float _metile_v38_r21 = _metile_v21_r21 * v29;\n float _metile_v38_r22 = _metile_v21_r22 * v29;\n float _metile_v38_r23 = _metile_v21_r23 * v29;\n float _metile_v38_r24 = _metile_v21_r24 * v29;\n float _metile_v38_r25 = _metile_v21_r25 * v29;\n float _metile_v38_r26 = _metile_v21_r26 * v29;\n float _metile_v38_r27 = _metile_v21_r27 * v29;\n float _metile_v38_r28 = _metile_v21_r28 * v29;\n float _metile_v38_r29 = _metile_v21_r29 * v29;\n float _metile_v38_r30 = _metile_v21_r30 * v29;\n float _metile_v38_r31 = _metile_v21_r31 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n float _metile_v39_r16 = _metile_v38_r16 * _metile_v37_r16;\n float _metile_v39_r17 = _metile_v38_r17 * _metile_v37_r17;\n float _metile_v39_r18 = _metile_v38_r18 * _metile_v37_r18;\n float _metile_v39_r19 = _metile_v38_r19 * _metile_v37_r19;\n float _metile_v39_r20 = _metile_v38_r20 * _metile_v37_r20;\n float _metile_v39_r21 = _metile_v38_r21 * _metile_v37_r21;\n float _metile_v39_r22 = _metile_v38_r22 * _metile_v37_r22;\n float _metile_v39_r23 = _metile_v38_r23 * _metile_v37_r23;\n float _metile_v39_r24 = _metile_v38_r24 * _metile_v37_r24;\n float _metile_v39_r25 = _metile_v38_r25 * _metile_v37_r25;\n float _metile_v39_r26 = _metile_v38_r26 * _metile_v37_r26;\n float _metile_v39_r27 = _metile_v38_r27 * _metile_v37_r27;\n float _metile_v39_r28 = _metile_v38_r28 * _metile_v37_r28;\n float _metile_v39_r29 = _metile_v38_r29 * _metile_v37_r29;\n float _metile_v39_r30 = _metile_v38_r30 * _metile_v37_r30;\n float _metile_v39_r31 = _metile_v38_r31 * _metile_v37_r31;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v41_r16 = _metile_register_index________________ >= 0;\n bool _metile_v41_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v41_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v41_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v41_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v41_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v41_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v41_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v41_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v41_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v41_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v41_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v41_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v41_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v41_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v41_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v42_r8 = _metile_register_index________ < 1024;\n bool _metile_v42_r9 = _metile_register_index_________ < 1024;\n bool _metile_v42_r10 = _metile_register_index__________ < 1024;\n bool _metile_v42_r11 = _metile_register_index___________ < 1024;\n bool _metile_v42_r12 = _metile_register_index____________ < 1024;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v42_r14 = _metile_register_index______________ < 1024;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v42_r16 = _metile_register_index________________ < 1024;\n bool _metile_v42_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v42_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v42_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v42_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v42_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v42_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v42_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v42_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v42_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v42_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v42_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v42_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v42_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v42_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v42_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n bool _metile_v43_r16 = _metile_v41_r16 & _metile_v42_r16;\n bool _metile_v43_r17 = _metile_v41_r17 & _metile_v42_r17;\n bool _metile_v43_r18 = _metile_v41_r18 & _metile_v42_r18;\n bool _metile_v43_r19 = _metile_v41_r19 & _metile_v42_r19;\n bool _metile_v43_r20 = _metile_v41_r20 & _metile_v42_r20;\n bool _metile_v43_r21 = _metile_v41_r21 & _metile_v42_r21;\n bool _metile_v43_r22 = _metile_v41_r22 & _metile_v42_r22;\n bool _metile_v43_r23 = _metile_v41_r23 & _metile_v42_r23;\n bool _metile_v43_r24 = _metile_v41_r24 & _metile_v42_r24;\n bool _metile_v43_r25 = _metile_v41_r25 & _metile_v42_r25;\n bool _metile_v43_r26 = _metile_v41_r26 & _metile_v42_r26;\n bool _metile_v43_r27 = _metile_v41_r27 & _metile_v42_r27;\n bool _metile_v43_r28 = _metile_v41_r28 & _metile_v42_r28;\n bool _metile_v43_r29 = _metile_v41_r29 & _metile_v42_r29;\n bool _metile_v43_r30 = _metile_v41_r30 & _metile_v42_r30;\n bool _metile_v43_r31 = _metile_v41_r31 & _metile_v42_r31;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n int _off__metile_v44_r16 = v9 + _metile_register_index________________;\n int _off__metile_v44_r17 = v9 + _metile_register_index_________________;\n int _off__metile_v44_r18 = v9 + _metile_register_index__________________;\n int _off__metile_v44_r19 = v9 + _metile_register_index___________________;\n int _off__metile_v44_r20 = v9 + _metile_register_index____________________;\n int _off__metile_v44_r21 = v9 + _metile_register_index_____________________;\n int _off__metile_v44_r22 = v9 + _metile_register_index______________________;\n int _off__metile_v44_r23 = v9 + _metile_register_index_______________________;\n int _off__metile_v44_r24 = v9 + _metile_register_index________________________;\n int _off__metile_v44_r25 = v9 + _metile_register_index_________________________;\n int _off__metile_v44_r26 = v9 + _metile_register_index__________________________;\n int _off__metile_v44_r27 = v9 + _metile_register_index___________________________;\n int _off__metile_v44_r28 = v9 + _metile_register_index____________________________;\n int _off__metile_v44_r29 = v9 + _metile_register_index_____________________________;\n int _off__metile_v44_r30 = v9 + _metile_register_index______________________________;\n int _off__metile_v44_r31 = v9 + _metile_register_index_______________________________;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_float4(float4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_float4(float4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n if ((_metile_v43_r8) && (_metile_v43_r9) && (_metile_v43_r10) && (_metile_v43_r11) && (long(_off__metile_v44_r9) == long(_off__metile_v44_r8) + 1) && (long(_off__metile_v44_r10) == long(_off__metile_v44_r8) + 2) && (long(_off__metile_v44_r11) == long(_off__metile_v44_r8) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r8) = packed_float4(float4(static_cast(_metile_v39_r8), static_cast(_metile_v39_r9), static_cast(_metile_v39_r10), static_cast(_metile_v39_r11)));\n } else {\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = static_cast(_metile_v39_r8); }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = static_cast(_metile_v39_r9); }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = static_cast(_metile_v39_r10); }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = static_cast(_metile_v39_r11); }\n }\n if ((_metile_v43_r12) && (_metile_v43_r13) && (_metile_v43_r14) && (_metile_v43_r15) && (long(_off__metile_v44_r13) == long(_off__metile_v44_r12) + 1) && (long(_off__metile_v44_r14) == long(_off__metile_v44_r12) + 2) && (long(_off__metile_v44_r15) == long(_off__metile_v44_r12) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r12) = packed_float4(float4(static_cast(_metile_v39_r12), static_cast(_metile_v39_r13), static_cast(_metile_v39_r14), static_cast(_metile_v39_r15)));\n } else {\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = static_cast(_metile_v39_r12); }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = static_cast(_metile_v39_r13); }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = static_cast(_metile_v39_r14); }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = static_cast(_metile_v39_r15); }\n }\n if ((_metile_v43_r16) && (_metile_v43_r17) && (_metile_v43_r18) && (_metile_v43_r19) && (long(_off__metile_v44_r17) == long(_off__metile_v44_r16) + 1) && (long(_off__metile_v44_r18) == long(_off__metile_v44_r16) + 2) && (long(_off__metile_v44_r19) == long(_off__metile_v44_r16) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r16) = packed_float4(float4(static_cast(_metile_v39_r16), static_cast(_metile_v39_r17), static_cast(_metile_v39_r18), static_cast(_metile_v39_r19)));\n } else {\n if (_metile_v43_r16) { Out[_off__metile_v44_r16] = static_cast(_metile_v39_r16); }\n if (_metile_v43_r17) { Out[_off__metile_v44_r17] = static_cast(_metile_v39_r17); }\n if (_metile_v43_r18) { Out[_off__metile_v44_r18] = static_cast(_metile_v39_r18); }\n if (_metile_v43_r19) { Out[_off__metile_v44_r19] = static_cast(_metile_v39_r19); }\n }\n if ((_metile_v43_r20) && (_metile_v43_r21) && (_metile_v43_r22) && (_metile_v43_r23) && (long(_off__metile_v44_r21) == long(_off__metile_v44_r20) + 1) && (long(_off__metile_v44_r22) == long(_off__metile_v44_r20) + 2) && (long(_off__metile_v44_r23) == long(_off__metile_v44_r20) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r20) = packed_float4(float4(static_cast(_metile_v39_r20), static_cast(_metile_v39_r21), static_cast(_metile_v39_r22), static_cast(_metile_v39_r23)));\n } else {\n if (_metile_v43_r20) { Out[_off__metile_v44_r20] = static_cast(_metile_v39_r20); }\n if (_metile_v43_r21) { Out[_off__metile_v44_r21] = static_cast(_metile_v39_r21); }\n if (_metile_v43_r22) { Out[_off__metile_v44_r22] = static_cast(_metile_v39_r22); }\n if (_metile_v43_r23) { Out[_off__metile_v44_r23] = static_cast(_metile_v39_r23); }\n }\n if ((_metile_v43_r24) && (_metile_v43_r25) && (_metile_v43_r26) && (_metile_v43_r27) && (long(_off__metile_v44_r25) == long(_off__metile_v44_r24) + 1) && (long(_off__metile_v44_r26) == long(_off__metile_v44_r24) + 2) && (long(_off__metile_v44_r27) == long(_off__metile_v44_r24) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r24) = packed_float4(float4(static_cast(_metile_v39_r24), static_cast(_metile_v39_r25), static_cast(_metile_v39_r26), static_cast(_metile_v39_r27)));\n } else {\n if (_metile_v43_r24) { Out[_off__metile_v44_r24] = static_cast(_metile_v39_r24); }\n if (_metile_v43_r25) { Out[_off__metile_v44_r25] = static_cast(_metile_v39_r25); }\n if (_metile_v43_r26) { Out[_off__metile_v44_r26] = static_cast(_metile_v39_r26); }\n if (_metile_v43_r27) { Out[_off__metile_v44_r27] = static_cast(_metile_v39_r27); }\n }\n if ((_metile_v43_r28) && (_metile_v43_r29) && (_metile_v43_r30) && (_metile_v43_r31) && (long(_off__metile_v44_r29) == long(_off__metile_v44_r28) + 1) && (long(_off__metile_v44_r30) == long(_off__metile_v44_r28) + 2) && (long(_off__metile_v44_r31) == long(_off__metile_v44_r28) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r28) = packed_float4(float4(static_cast(_metile_v39_r28), static_cast(_metile_v39_r29), static_cast(_metile_v39_r30), static_cast(_metile_v39_r31)));\n } else {\n if (_metile_v43_r28) { Out[_off__metile_v44_r28] = static_cast(_metile_v39_r28); }\n if (_metile_v43_r29) { Out[_off__metile_v44_r29] = static_cast(_metile_v39_r29); }\n if (_metile_v43_r30) { Out[_off__metile_v44_r30] = static_cast(_metile_v39_r30); }\n if (_metile_v43_r31) { Out[_off__metile_v44_r31] = static_cast(_metile_v39_r31); }\n }\n}", "source_sha256": "c8101f914e715ded38108b0b5ca87ac0fdc945815a7e8480038b36c36f05e689", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 32, 1, 1 ], "is_gemm": false, "prefer_ordered": false, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 32, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 32 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [], "double_buffered": false, "vectorized_loads": 16, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 32, "threads": 32, "scratch": null, "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 16, "grouped_stores": 8 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 617, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.209, "control": 199.958, "speedup": 1.003759870286985 }, "gpu_us": { "candidate": 3.41667328029871, "control": 2.333370503038168, "speedup": 0.6829363862482538 } } }, { "frozen_register4": { "pairs": 619, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.458, "control": 198.042, "speedup": 1.0029575909813733 }, "gpu_us": { "candidate": 3.41667328029871, "control": 2.3333122953772545, "speedup": 0.682919349892671 } } }, { "frozen_register4": { "pairs": 613, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.167, "control": 199.25, "speedup": 0.9954188252808904 }, "gpu_us": { "candidate": 3.41667328029871, "control": 2.333370503038168, "speedup": 0.6829363862482538 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0007050301159106, "round_speedups": [ 1.003759870286985, 1.0029575909813733, 0.9954188252808904 ], "candidate": 198.94150076311882, "control": 199.08176051246153 }, "gpu_us": { "speedup": 0.6829307074158384, "round_speedups": [ 0.6829363862482538, 0.682919349892671, 0.6829363862482538 ], "candidate": 3.41667328029871, "control": 2.333351100323191 } } } }, { "name": "float32_32x1024", "dtype": "float32", "batches": 32, "width": 1024, "status": "measured", "variant": { "name": "register2_striped", "elements_per_thread": 2, "layout": "striped" }, "input_sha256": "0fc05dcd6172e2eebffb6471582bea984c5a888fc3b3a095d91b296908e6567b", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 511;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 512;\n int _metile_register_index_ = int(_metile_register_packed_);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n threadgroup float _metile_register_reduction[16];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 16u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n}", "source_sha256": "80a3b58c42ac34374f90c87b95d6214a45947a8245bd291ea088e84eea10acdd", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 512, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 512, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 2 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 16, "bytes": 64 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 2, "threads": 512, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 613, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.75, "control": 200.333, "speedup": 1.0079647798742137 }, "gpu_us": { "candidate": 2.2500171326100826, "control": 2.2916938178241253, "speedup": 1.0185228301642737 } } }, { "frozen_register4": { "pairs": 547, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.917, "control": 201.0, "speedup": 1.0004131059094055 }, "gpu_us": { "candidate": 2.2500171326100826, "control": 2.3333122953772545, "speedup": 1.0370197904540164 } } }, { "frozen_register4": { "pairs": 614, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.85399999999998, "control": 197.77100000000002, "speedup": 0.9945537932352381 }, "gpu_us": { "candidate": 2.2500171326100826, "control": 2.3333122953772545, "speedup": 1.0370197904540164 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0009621818087795, "round_speedups": [ 1.0079647798742137, 1.0004131059094055, 0.9945537932352381 ], "candidate": 199.5045100221626, "control": 199.69646963247547 }, "gpu_us": { "speedup": 1.03081711118876, "round_speedups": [ 1.0185228301642737, 1.0370197904540164, 1.0370197904540164 ], "candidate": 2.2500171326100826, "control": 2.3193561607623425 } } } }, { "name": "float32_32x1024", "dtype": "float32", "batches": 32, "width": 1024, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "0fc05dcd6172e2eebffb6471582bea984c5a888fc3b3a095d91b296908e6567b", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "26dcd97c409e667a170eb1ec796096fa645431253522d88e56e53edb0819b727", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 615, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.375, "control": 200.042, "speedup": 1.0084032766225584 }, "gpu_us": { "candidate": 2.2916938178241253, "control": 2.3333122953772545, "speedup": 1.018160575042544 } } }, { "frozen_register4": { "pairs": 602, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.3545, "control": 199.875, "speedup": 1.007665568464542 }, "gpu_us": { "candidate": 2.2916938178241253, "control": 2.333370503038168, "speedup": 1.0181859744481978 } } }, { "frozen_register4": { "pairs": 526, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.45850000000002, "control": 199.52100000000002, "speedup": 1.0053537641370867 }, "gpu_us": { "candidate": 2.3333122953772545, "control": 2.374988980591297, "speedup": 1.0178615975652348 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0071400315466268, "round_speedups": [ 1.0084032766225584, 1.007665568464542, 1.0053537641370867 ], "candidate": 198.39599490165205, "control": 199.8125485639742 }, "gpu_us": { "speedup": 1.0180693716964182, "round_speedups": [ 1.018160575042544, 1.0181859744481978, 1.0178615975652348 ], "candidate": 2.3054835013400896, "control": 2.3471421396657637 } } } }, { "name": "float32_256x1024", "dtype": "float32", "batches": 256, "width": 1024, "status": "measured", "variant": { "name": "register8_striped", "elements_per_thread": 8, "layout": "striped" }, "input_sha256": "d91bbc8e56d1e705bcdef1e433ae3b5ce1d9e73a225cd6afc919bf59342546a9", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 127;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 128;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 256;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 384;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 512;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 640;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 768;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 896;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n float _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n float _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n float _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_____ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum______ = _metile_register_sum____ + _metile_register_sum_____;\n threadgroup float _metile_register_reduction[4];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 4u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n float _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n float _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n float _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n}", "source_sha256": "34702ecd3ed2337fb2f6ddd5e80d06f362dc722ce7e9d0c31a768733f59fa7cf", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 128, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 128, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 8 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 4, "bytes": 16 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 8, "threads": 128, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 553, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 212.708, "control": 211.417, "speedup": 0.9939306467081633 }, "gpu_us": { "candidate": 8.000002708286047, "control": 8.125032763928175, "speedup": 1.0156287516643747 } } }, { "frozen_register4": { "pairs": 562, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 215.9795, "control": 217.70850000000002, "speedup": 1.0080053894003829 }, "gpu_us": { "candidate": 7.958326023072004, "control": 8.083356078714132, "speedup": 1.0157105973391456 } } }, { "frozen_register4": { "pairs": 465, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 218.292, "control": 217.875, "speedup": 0.9980897146940795 }, "gpu_us": { "candidate": 7.958326023072004, "control": 8.083356078714132, "speedup": 1.0157105973391456 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9999911858225916, "round_speedups": [ 0.9939306467081633, 1.0080053894003829, 0.9980897146940795 ], "candidate": 215.64764768234366, "control": 215.64574692571924 }, "gpu_us": { "speedup": 1.0156833147147335, "round_speedups": [ 1.0156287516643747, 1.0157105973391456, 1.0157105973391456 ], "candidate": 7.972194071206696, "control": 8.097224499792363 } } } }, { "name": "float32_256x1024", "dtype": "float32", "batches": 256, "width": 1024, "status": "measured", "variant": { "name": "register8_blocked4", "elements_per_thread": 8, "layout": "blocked4" }, "input_sha256": "d91bbc8e56d1e705bcdef1e433ae3b5ce1d9e73a225cd6afc919bf59342546a9", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 127;\n int _metile_register_index = int((((_metile_bounded_thread >> 7) & 1u) << 0) | (((_metile_bounded_thread >> 8) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 6) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 128;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 7) & 1u) << 0) | (((_metile_register_packed_ >> 8) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 6) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 256;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 7) & 1u) << 0) | (((_metile_register_packed__ >> 8) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 6) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 384;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 7) & 1u) << 0) | (((_metile_register_packed___ >> 8) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 6) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 512;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 7) & 1u) << 0) | (((_metile_register_packed____ >> 8) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 5) & 1u) << 7) | (((_metile_register_packed____ >> 6) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 640;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 7) & 1u) << 0) | (((_metile_register_packed_____ >> 8) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 5) & 1u) << 7) | (((_metile_register_packed_____ >> 6) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 768;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 7) & 1u) << 0) | (((_metile_register_packed______ >> 8) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 5) & 1u) << 7) | (((_metile_register_packed______ >> 6) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 896;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 7) & 1u) << 0) | (((_metile_register_packed_______ >> 8) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 5) & 1u) << 7) | (((_metile_register_packed_______ >> 6) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n float4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = float4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n float _metile_v20_r0 = _metile_vector_load[0];\n float _metile_v20_r1 = _metile_vector_load[1];\n float _metile_v20_r2 = _metile_vector_load[2];\n float _metile_v20_r3 = _metile_vector_load[3];\n float4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = float4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n float _metile_v20_r4 = _metile_vector_load_[0];\n float _metile_v20_r5 = _metile_vector_load_[1];\n float _metile_v20_r6 = _metile_vector_load_[2];\n float _metile_v20_r7 = _metile_vector_load_[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_____ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum______ = _metile_register_sum____ + _metile_register_sum_____;\n threadgroup float _metile_register_reduction[4];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 4u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n float4 _metile_vector_load__;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load__ = float4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load__[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load__[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load__[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load__[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n float _metile_v36_r0 = _metile_vector_load__[0];\n float _metile_v36_r1 = _metile_vector_load__[1];\n float _metile_v36_r2 = _metile_vector_load__[2];\n float _metile_v36_r3 = _metile_vector_load__[3];\n float4 _metile_vector_load___;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load___ = float4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load___[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load___[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load___[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load___[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n float _metile_v36_r4 = _metile_vector_load___[0];\n float _metile_v36_r5 = _metile_vector_load___[1];\n float _metile_v36_r6 = _metile_vector_load___[2];\n float _metile_v36_r7 = _metile_vector_load___[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_float4(float4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_float4(float4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n}", "source_sha256": "6d76f908be757e95d29fcc3112125422c90cd6abc0b258ca9347b3c9175af34b", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 128, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 128, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 8 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 4, "bytes": 16 } ], "double_buffered": false, "vectorized_loads": 4, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 7, 8, 0, 1, 2, 3, 4, 5, 6, 9 ], "xor_mask": 0, "elements_per_thread": 8 }, "elements_per_thread": 8 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 8, "threads": 128, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 4, "grouped_stores": 2 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 473, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 218.333, "control": 220.292, "speedup": 1.0089725327824928 }, "gpu_us": { "candidate": 8.750008419156075, "control": 8.166651241481304, "speedup": 0.9333306724142518 } } }, { "frozen_register4": { "pairs": 563, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 218.959, "control": 220.084, "speedup": 1.005137948200348 }, "gpu_us": { "candidate": 8.66665504872799, "control": 8.125032763928175, "speedup": 0.9375050372081778 } } }, { "frozen_register4": { "pairs": 537, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 221.083, "control": 221.708, "speedup": 1.0028269925774482 }, "gpu_us": { "candidate": 8.624978363513947, "control": 8.124974556267262, "speedup": 0.9420283986610517 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0056426323211571, "round_speedups": [ 1.0089725327824928, 1.005137948200348, 1.0028269925774482 ], "candidate": 219.45518391973218, "control": 220.69348883356304 }, "gpu_us": { "speedup": 0.937614642991973, "round_speedups": [ 0.9333306724142518, 0.9375050372081778, 0.9420283986610517 ], "candidate": 8.680391881041231, "control": 8.138862534572894 } } } }, { "name": "float32_256x1024", "dtype": "float32", "batches": 256, "width": 1024, "status": "measured", "variant": { "name": "register16_striped", "elements_per_thread": 16, "layout": "striped" }, "input_sha256": "d91bbc8e56d1e705bcdef1e433ae3b5ce1d9e73a225cd6afc919bf59342546a9", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 63;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 64;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 128;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 192;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 256;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 320;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 384;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 448;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n int _metile_register_packed________ = _metile_bounded_thread + 512;\n int _metile_register_index________ = int(_metile_register_packed________);\n int _metile_register_packed_________ = _metile_bounded_thread + 576;\n int _metile_register_index_________ = int(_metile_register_packed_________);\n int _metile_register_packed__________ = _metile_bounded_thread + 640;\n int _metile_register_index__________ = int(_metile_register_packed__________);\n int _metile_register_packed___________ = _metile_bounded_thread + 704;\n int _metile_register_index___________ = int(_metile_register_packed___________);\n int _metile_register_packed____________ = _metile_bounded_thread + 768;\n int _metile_register_index____________ = int(_metile_register_packed____________);\n int _metile_register_packed_____________ = _metile_bounded_thread + 832;\n int _metile_register_index_____________ = int(_metile_register_packed_____________);\n int _metile_register_packed______________ = _metile_bounded_thread + 896;\n int _metile_register_index______________ = int(_metile_register_packed______________);\n int _metile_register_packed_______________ = _metile_bounded_thread + 960;\n int _metile_register_index_______________ = int(_metile_register_packed_______________);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v17_r8 = _metile_register_index________ < 1024;\n bool _metile_v17_r9 = _metile_register_index_________ < 1024;\n bool _metile_v17_r10 = _metile_register_index__________ < 1024;\n bool _metile_v17_r11 = _metile_register_index___________ < 1024;\n bool _metile_v17_r12 = _metile_register_index____________ < 1024;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v17_r14 = _metile_register_index______________ < 1024;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n float _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n float _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n float _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n float _metile_v20_r8 = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n float _metile_v20_r9 = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n float _metile_v20_r10 = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n float _metile_v20_r11 = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n float _metile_v20_r12 = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n float _metile_v20_r13 = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n float _metile_v20_r14 = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n float _metile_v20_r15 = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________ = _metile_register_sum____________ + _metile_register_sum_____________;\n threadgroup float _metile_register_reduction[2];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______________);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 2u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v33_r8 = _metile_register_index________ < 1024;\n bool _metile_v33_r9 = _metile_register_index_________ < 1024;\n bool _metile_v33_r10 = _metile_register_index__________ < 1024;\n bool _metile_v33_r11 = _metile_register_index___________ < 1024;\n bool _metile_v33_r12 = _metile_register_index____________ < 1024;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v33_r14 = _metile_register_index______________ < 1024;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n float _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n float _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n float _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n float _metile_v36_r8 = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n float _metile_v36_r9 = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n float _metile_v36_r10 = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n float _metile_v36_r11 = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n float _metile_v36_r12 = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n float _metile_v36_r13 = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n float _metile_v36_r14 = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n float _metile_v36_r15 = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v42_r8 = _metile_register_index________ < 1024;\n bool _metile_v42_r9 = _metile_register_index_________ < 1024;\n bool _metile_v42_r10 = _metile_register_index__________ < 1024;\n bool _metile_v42_r11 = _metile_register_index___________ < 1024;\n bool _metile_v42_r12 = _metile_register_index____________ < 1024;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v42_r14 = _metile_register_index______________ < 1024;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = _metile_v39_r8; }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = _metile_v39_r9; }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = _metile_v39_r10; }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = _metile_v39_r11; }\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = _metile_v39_r12; }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = _metile_v39_r13; }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = _metile_v39_r14; }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = _metile_v39_r15; }\n}", "source_sha256": "8d0e0811f88b35d004a56a9d076dee253811a6b9bdd8f46462f1664bdcec06df", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 64, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 64, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 16 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 2, "bytes": 8 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 16, "threads": 64, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 573, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 216.75, "control": 217.625, "speedup": 1.0040369088811996 }, "gpu_us": { "candidate": 8.04167939350009, "control": 8.04167939350009, "speedup": 1.0 } } }, { "frozen_register4": { "pairs": 526, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 215.64600000000002, "control": 216.85399999999998, "speedup": 1.0056017732765734 }, "gpu_us": { "candidate": 8.083326974883676, "control": 8.083297871053219, "speedup": 0.9999963995232969 } } }, { "frozen_register4": { "pairs": 517, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 215.875, "control": 217.417, "speedup": 1.007143022582513 }, "gpu_us": { "candidate": 8.083297871053219, "control": 8.083356078714132, "speedup": 1.0000072009793333 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0055931020350541, "round_speedups": [ 1.0040369088811996, 1.0056017732765734, 1.007143022582513 ], "candidate": 216.08981011222733, "control": 217.29842246892056 }, "gpu_us": { "speedup": 1.0000012001574607, "round_speedups": [ 1.0, 0.9999963995232969, 1.0000072009793333 ], "candidate": 8.069410852444204, "control": 8.06942053700784 } } } }, { "name": "float32_256x1024", "dtype": "float32", "batches": 256, "width": 1024, "status": "measured", "variant": { "name": "register16_blocked4", "elements_per_thread": 16, "layout": "blocked4" }, "input_sha256": "d91bbc8e56d1e705bcdef1e433ae3b5ce1d9e73a225cd6afc919bf59342546a9", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 63;\n int _metile_register_index = int((((_metile_bounded_thread >> 6) & 1u) << 0) | (((_metile_bounded_thread >> 7) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 8) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 64;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 6) & 1u) << 0) | (((_metile_register_packed_ >> 7) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 8) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 128;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 6) & 1u) << 0) | (((_metile_register_packed__ >> 7) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 8) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 192;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 6) & 1u) << 0) | (((_metile_register_packed___ >> 7) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 8) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 256;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 6) & 1u) << 0) | (((_metile_register_packed____ >> 7) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 5) & 1u) << 7) | (((_metile_register_packed____ >> 8) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 320;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 6) & 1u) << 0) | (((_metile_register_packed_____ >> 7) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 5) & 1u) << 7) | (((_metile_register_packed_____ >> 8) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 384;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 6) & 1u) << 0) | (((_metile_register_packed______ >> 7) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 5) & 1u) << 7) | (((_metile_register_packed______ >> 8) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 448;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 6) & 1u) << 0) | (((_metile_register_packed_______ >> 7) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 5) & 1u) << 7) | (((_metile_register_packed_______ >> 8) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n int _metile_register_packed________ = _metile_bounded_thread + 512;\n int _metile_register_index________ = int((((_metile_register_packed________ >> 6) & 1u) << 0) | (((_metile_register_packed________ >> 7) & 1u) << 1) | (((_metile_register_packed________ >> 0) & 1u) << 2) | (((_metile_register_packed________ >> 1) & 1u) << 3) | (((_metile_register_packed________ >> 2) & 1u) << 4) | (((_metile_register_packed________ >> 3) & 1u) << 5) | (((_metile_register_packed________ >> 4) & 1u) << 6) | (((_metile_register_packed________ >> 5) & 1u) << 7) | (((_metile_register_packed________ >> 8) & 1u) << 8) | (((_metile_register_packed________ >> 9) & 1u) << 9));\n int _metile_register_packed_________ = _metile_bounded_thread + 576;\n int _metile_register_index_________ = int((((_metile_register_packed_________ >> 6) & 1u) << 0) | (((_metile_register_packed_________ >> 7) & 1u) << 1) | (((_metile_register_packed_________ >> 0) & 1u) << 2) | (((_metile_register_packed_________ >> 1) & 1u) << 3) | (((_metile_register_packed_________ >> 2) & 1u) << 4) | (((_metile_register_packed_________ >> 3) & 1u) << 5) | (((_metile_register_packed_________ >> 4) & 1u) << 6) | (((_metile_register_packed_________ >> 5) & 1u) << 7) | (((_metile_register_packed_________ >> 8) & 1u) << 8) | (((_metile_register_packed_________ >> 9) & 1u) << 9));\n int _metile_register_packed__________ = _metile_bounded_thread + 640;\n int _metile_register_index__________ = int((((_metile_register_packed__________ >> 6) & 1u) << 0) | (((_metile_register_packed__________ >> 7) & 1u) << 1) | (((_metile_register_packed__________ >> 0) & 1u) << 2) | (((_metile_register_packed__________ >> 1) & 1u) << 3) | (((_metile_register_packed__________ >> 2) & 1u) << 4) | (((_metile_register_packed__________ >> 3) & 1u) << 5) | (((_metile_register_packed__________ >> 4) & 1u) << 6) | (((_metile_register_packed__________ >> 5) & 1u) << 7) | (((_metile_register_packed__________ >> 8) & 1u) << 8) | (((_metile_register_packed__________ >> 9) & 1u) << 9));\n int _metile_register_packed___________ = _metile_bounded_thread + 704;\n int _metile_register_index___________ = int((((_metile_register_packed___________ >> 6) & 1u) << 0) | (((_metile_register_packed___________ >> 7) & 1u) << 1) | (((_metile_register_packed___________ >> 0) & 1u) << 2) | (((_metile_register_packed___________ >> 1) & 1u) << 3) | (((_metile_register_packed___________ >> 2) & 1u) << 4) | (((_metile_register_packed___________ >> 3) & 1u) << 5) | (((_metile_register_packed___________ >> 4) & 1u) << 6) | (((_metile_register_packed___________ >> 5) & 1u) << 7) | (((_metile_register_packed___________ >> 8) & 1u) << 8) | (((_metile_register_packed___________ >> 9) & 1u) << 9));\n int _metile_register_packed____________ = _metile_bounded_thread + 768;\n int _metile_register_index____________ = int((((_metile_register_packed____________ >> 6) & 1u) << 0) | (((_metile_register_packed____________ >> 7) & 1u) << 1) | (((_metile_register_packed____________ >> 0) & 1u) << 2) | (((_metile_register_packed____________ >> 1) & 1u) << 3) | (((_metile_register_packed____________ >> 2) & 1u) << 4) | (((_metile_register_packed____________ >> 3) & 1u) << 5) | (((_metile_register_packed____________ >> 4) & 1u) << 6) | (((_metile_register_packed____________ >> 5) & 1u) << 7) | (((_metile_register_packed____________ >> 8) & 1u) << 8) | (((_metile_register_packed____________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________ = _metile_bounded_thread + 832;\n int _metile_register_index_____________ = int((((_metile_register_packed_____________ >> 6) & 1u) << 0) | (((_metile_register_packed_____________ >> 7) & 1u) << 1) | (((_metile_register_packed_____________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________ >> 5) & 1u) << 7) | (((_metile_register_packed_____________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________ >> 9) & 1u) << 9));\n int _metile_register_packed______________ = _metile_bounded_thread + 896;\n int _metile_register_index______________ = int((((_metile_register_packed______________ >> 6) & 1u) << 0) | (((_metile_register_packed______________ >> 7) & 1u) << 1) | (((_metile_register_packed______________ >> 0) & 1u) << 2) | (((_metile_register_packed______________ >> 1) & 1u) << 3) | (((_metile_register_packed______________ >> 2) & 1u) << 4) | (((_metile_register_packed______________ >> 3) & 1u) << 5) | (((_metile_register_packed______________ >> 4) & 1u) << 6) | (((_metile_register_packed______________ >> 5) & 1u) << 7) | (((_metile_register_packed______________ >> 8) & 1u) << 8) | (((_metile_register_packed______________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________ = _metile_bounded_thread + 960;\n int _metile_register_index_______________ = int((((_metile_register_packed_______________ >> 6) & 1u) << 0) | (((_metile_register_packed_______________ >> 7) & 1u) << 1) | (((_metile_register_packed_______________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________ >> 5) & 1u) << 7) | (((_metile_register_packed_______________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v17_r8 = _metile_register_index________ < 1024;\n bool _metile_v17_r9 = _metile_register_index_________ < 1024;\n bool _metile_v17_r10 = _metile_register_index__________ < 1024;\n bool _metile_v17_r11 = _metile_register_index___________ < 1024;\n bool _metile_v17_r12 = _metile_register_index____________ < 1024;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v17_r14 = _metile_register_index______________ < 1024;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n float4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = float4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n float _metile_v20_r0 = _metile_vector_load[0];\n float _metile_v20_r1 = _metile_vector_load[1];\n float _metile_v20_r2 = _metile_vector_load[2];\n float _metile_v20_r3 = _metile_vector_load[3];\n float4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = float4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n float _metile_v20_r4 = _metile_vector_load_[0];\n float _metile_v20_r5 = _metile_vector_load_[1];\n float _metile_v20_r6 = _metile_vector_load_[2];\n float _metile_v20_r7 = _metile_vector_load_[3];\n float4 _metile_vector_load__;\n if ((_metile_v18_r8) && (_metile_v18_r9) && (_metile_v18_r10) && (_metile_v18_r11) && (long(_off__metile_v19_r9) == long(_off__metile_v19_r8) + 1) && (long(_off__metile_v19_r10) == long(_off__metile_v19_r8) + 2) && (long(_off__metile_v19_r11) == long(_off__metile_v19_r8) + 3)) {\n _metile_vector_load__ = float4(*reinterpret_cast(X + _off__metile_v19_r8));\n } else {\n _metile_vector_load__[0] = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n _metile_vector_load__[1] = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n _metile_vector_load__[2] = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n _metile_vector_load__[3] = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n }\n float _metile_v20_r8 = _metile_vector_load__[0];\n float _metile_v20_r9 = _metile_vector_load__[1];\n float _metile_v20_r10 = _metile_vector_load__[2];\n float _metile_v20_r11 = _metile_vector_load__[3];\n float4 _metile_vector_load___;\n if ((_metile_v18_r12) && (_metile_v18_r13) && (_metile_v18_r14) && (_metile_v18_r15) && (long(_off__metile_v19_r13) == long(_off__metile_v19_r12) + 1) && (long(_off__metile_v19_r14) == long(_off__metile_v19_r12) + 2) && (long(_off__metile_v19_r15) == long(_off__metile_v19_r12) + 3)) {\n _metile_vector_load___ = float4(*reinterpret_cast(X + _off__metile_v19_r12));\n } else {\n _metile_vector_load___[0] = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n _metile_vector_load___[1] = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n _metile_vector_load___[2] = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n _metile_vector_load___[3] = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n }\n float _metile_v20_r12 = _metile_vector_load___[0];\n float _metile_v20_r13 = _metile_vector_load___[1];\n float _metile_v20_r14 = _metile_vector_load___[2];\n float _metile_v20_r15 = _metile_vector_load___[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________ = _metile_register_sum____________ + _metile_register_sum_____________;\n threadgroup float _metile_register_reduction[2];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum______________);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 2u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v33_r8 = _metile_register_index________ < 1024;\n bool _metile_v33_r9 = _metile_register_index_________ < 1024;\n bool _metile_v33_r10 = _metile_register_index__________ < 1024;\n bool _metile_v33_r11 = _metile_register_index___________ < 1024;\n bool _metile_v33_r12 = _metile_register_index____________ < 1024;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v33_r14 = _metile_register_index______________ < 1024;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n float4 _metile_vector_load____;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load____ = float4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load____[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load____[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load____[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load____[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n float _metile_v36_r0 = _metile_vector_load____[0];\n float _metile_v36_r1 = _metile_vector_load____[1];\n float _metile_v36_r2 = _metile_vector_load____[2];\n float _metile_v36_r3 = _metile_vector_load____[3];\n float4 _metile_vector_load_____;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load_____ = float4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load_____[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load_____[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load_____[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load_____[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n float _metile_v36_r4 = _metile_vector_load_____[0];\n float _metile_v36_r5 = _metile_vector_load_____[1];\n float _metile_v36_r6 = _metile_vector_load_____[2];\n float _metile_v36_r7 = _metile_vector_load_____[3];\n float4 _metile_vector_load______;\n if ((_metile_v34_r8) && (_metile_v34_r9) && (_metile_v34_r10) && (_metile_v34_r11) && (long(_metile_register_index_________) == long(_metile_register_index________) + 1) && (long(_metile_register_index__________) == long(_metile_register_index________) + 2) && (long(_metile_register_index___________) == long(_metile_register_index________) + 3)) {\n _metile_vector_load______ = float4(*reinterpret_cast(W + _metile_register_index________));\n } else {\n _metile_vector_load______[0] = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n _metile_vector_load______[1] = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n _metile_vector_load______[2] = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n _metile_vector_load______[3] = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n }\n float _metile_v36_r8 = _metile_vector_load______[0];\n float _metile_v36_r9 = _metile_vector_load______[1];\n float _metile_v36_r10 = _metile_vector_load______[2];\n float _metile_v36_r11 = _metile_vector_load______[3];\n float4 _metile_vector_load_______;\n if ((_metile_v34_r12) && (_metile_v34_r13) && (_metile_v34_r14) && (_metile_v34_r15) && (long(_metile_register_index_____________) == long(_metile_register_index____________) + 1) && (long(_metile_register_index______________) == long(_metile_register_index____________) + 2) && (long(_metile_register_index_______________) == long(_metile_register_index____________) + 3)) {\n _metile_vector_load_______ = float4(*reinterpret_cast(W + _metile_register_index____________));\n } else {\n _metile_vector_load_______[0] = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n _metile_vector_load_______[1] = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n _metile_vector_load_______[2] = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n _metile_vector_load_______[3] = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n }\n float _metile_v36_r12 = _metile_vector_load_______[0];\n float _metile_v36_r13 = _metile_vector_load_______[1];\n float _metile_v36_r14 = _metile_vector_load_______[2];\n float _metile_v36_r15 = _metile_vector_load_______[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v42_r8 = _metile_register_index________ < 1024;\n bool _metile_v42_r9 = _metile_register_index_________ < 1024;\n bool _metile_v42_r10 = _metile_register_index__________ < 1024;\n bool _metile_v42_r11 = _metile_register_index___________ < 1024;\n bool _metile_v42_r12 = _metile_register_index____________ < 1024;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v42_r14 = _metile_register_index______________ < 1024;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_float4(float4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_float4(float4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n if ((_metile_v43_r8) && (_metile_v43_r9) && (_metile_v43_r10) && (_metile_v43_r11) && (long(_off__metile_v44_r9) == long(_off__metile_v44_r8) + 1) && (long(_off__metile_v44_r10) == long(_off__metile_v44_r8) + 2) && (long(_off__metile_v44_r11) == long(_off__metile_v44_r8) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r8) = packed_float4(float4(static_cast(_metile_v39_r8), static_cast(_metile_v39_r9), static_cast(_metile_v39_r10), static_cast(_metile_v39_r11)));\n } else {\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = static_cast(_metile_v39_r8); }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = static_cast(_metile_v39_r9); }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = static_cast(_metile_v39_r10); }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = static_cast(_metile_v39_r11); }\n }\n if ((_metile_v43_r12) && (_metile_v43_r13) && (_metile_v43_r14) && (_metile_v43_r15) && (long(_off__metile_v44_r13) == long(_off__metile_v44_r12) + 1) && (long(_off__metile_v44_r14) == long(_off__metile_v44_r12) + 2) && (long(_off__metile_v44_r15) == long(_off__metile_v44_r12) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r12) = packed_float4(float4(static_cast(_metile_v39_r12), static_cast(_metile_v39_r13), static_cast(_metile_v39_r14), static_cast(_metile_v39_r15)));\n } else {\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = static_cast(_metile_v39_r12); }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = static_cast(_metile_v39_r13); }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = static_cast(_metile_v39_r14); }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = static_cast(_metile_v39_r15); }\n }\n}", "source_sha256": "638bb86de40e605f8a6ccd7a4a97089454fbe67cb9c226a6b7a7e2134cb962f6", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 64, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 64, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 16 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 2, "bytes": 8 } ], "double_buffered": false, "vectorized_loads": 8, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 6, 7, 0, 1, 2, 3, 4, 5, 8, 9 ], "xor_mask": 0, "elements_per_thread": 16 }, "elements_per_thread": 16 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 16, "threads": 64, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 8, "grouped_stores": 4 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 516, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 217.2495, "control": 217.2295, "speedup": 0.9999079399492289 }, "gpu_us": { "candidate": 9.25001222640276, "control": 8.041621185839176, "speedup": 0.8693633034219767 } } }, { "frozen_register4": { "pairs": 563, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 220.5, "control": 219.375, "speedup": 0.9948979591836735 }, "gpu_us": { "candidate": 9.25001222640276, "control": 8.000002708286047, "speedup": 0.864864014498408 } } }, { "frozen_register4": { "pairs": 569, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 219.375, "control": 220.167, "speedup": 1.0036102564102565 }, "gpu_us": { "candidate": 9.249954018741846, "control": 8.000002708286047, "speedup": 0.8648694568726284 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9994656728443622, "round_speedups": [ 0.9999079399492289, 0.9948979591836735, 1.0036102564102565 ], "candidate": 219.03734723237068, "control": 218.92030962964566 }, "gpu_us": { "speedup": 0.8663630014819801, "round_speedups": [ 0.8693633034219767, 0.864864014498408, 0.8648694568726284 ], "candidate": 9.249992823808423, "control": 8.013851546521442 } } } }, { "name": "float32_256x1024", "dtype": "float32", "batches": 256, "width": 1024, "status": "measured", "variant": { "name": "register32_striped", "elements_per_thread": 32, "layout": "striped" }, "input_sha256": "d91bbc8e56d1e705bcdef1e433ae3b5ce1d9e73a225cd6afc919bf59342546a9", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 31;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 32;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 64;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 96;\n int _metile_register_index___ = int(_metile_register_packed___);\n int _metile_register_packed____ = _metile_bounded_thread + 128;\n int _metile_register_index____ = int(_metile_register_packed____);\n int _metile_register_packed_____ = _metile_bounded_thread + 160;\n int _metile_register_index_____ = int(_metile_register_packed_____);\n int _metile_register_packed______ = _metile_bounded_thread + 192;\n int _metile_register_index______ = int(_metile_register_packed______);\n int _metile_register_packed_______ = _metile_bounded_thread + 224;\n int _metile_register_index_______ = int(_metile_register_packed_______);\n int _metile_register_packed________ = _metile_bounded_thread + 256;\n int _metile_register_index________ = int(_metile_register_packed________);\n int _metile_register_packed_________ = _metile_bounded_thread + 288;\n int _metile_register_index_________ = int(_metile_register_packed_________);\n int _metile_register_packed__________ = _metile_bounded_thread + 320;\n int _metile_register_index__________ = int(_metile_register_packed__________);\n int _metile_register_packed___________ = _metile_bounded_thread + 352;\n int _metile_register_index___________ = int(_metile_register_packed___________);\n int _metile_register_packed____________ = _metile_bounded_thread + 384;\n int _metile_register_index____________ = int(_metile_register_packed____________);\n int _metile_register_packed_____________ = _metile_bounded_thread + 416;\n int _metile_register_index_____________ = int(_metile_register_packed_____________);\n int _metile_register_packed______________ = _metile_bounded_thread + 448;\n int _metile_register_index______________ = int(_metile_register_packed______________);\n int _metile_register_packed_______________ = _metile_bounded_thread + 480;\n int _metile_register_index_______________ = int(_metile_register_packed_______________);\n int _metile_register_packed________________ = _metile_bounded_thread + 512;\n int _metile_register_index________________ = int(_metile_register_packed________________);\n int _metile_register_packed_________________ = _metile_bounded_thread + 544;\n int _metile_register_index_________________ = int(_metile_register_packed_________________);\n int _metile_register_packed__________________ = _metile_bounded_thread + 576;\n int _metile_register_index__________________ = int(_metile_register_packed__________________);\n int _metile_register_packed___________________ = _metile_bounded_thread + 608;\n int _metile_register_index___________________ = int(_metile_register_packed___________________);\n int _metile_register_packed____________________ = _metile_bounded_thread + 640;\n int _metile_register_index____________________ = int(_metile_register_packed____________________);\n int _metile_register_packed_____________________ = _metile_bounded_thread + 672;\n int _metile_register_index_____________________ = int(_metile_register_packed_____________________);\n int _metile_register_packed______________________ = _metile_bounded_thread + 704;\n int _metile_register_index______________________ = int(_metile_register_packed______________________);\n int _metile_register_packed_______________________ = _metile_bounded_thread + 736;\n int _metile_register_index_______________________ = int(_metile_register_packed_______________________);\n int _metile_register_packed________________________ = _metile_bounded_thread + 768;\n int _metile_register_index________________________ = int(_metile_register_packed________________________);\n int _metile_register_packed_________________________ = _metile_bounded_thread + 800;\n int _metile_register_index_________________________ = int(_metile_register_packed_________________________);\n int _metile_register_packed__________________________ = _metile_bounded_thread + 832;\n int _metile_register_index__________________________ = int(_metile_register_packed__________________________);\n int _metile_register_packed___________________________ = _metile_bounded_thread + 864;\n int _metile_register_index___________________________ = int(_metile_register_packed___________________________);\n int _metile_register_packed____________________________ = _metile_bounded_thread + 896;\n int _metile_register_index____________________________ = int(_metile_register_packed____________________________);\n int _metile_register_packed_____________________________ = _metile_bounded_thread + 928;\n int _metile_register_index_____________________________ = int(_metile_register_packed_____________________________);\n int _metile_register_packed______________________________ = _metile_bounded_thread + 960;\n int _metile_register_index______________________________ = int(_metile_register_packed______________________________);\n int _metile_register_packed_______________________________ = _metile_bounded_thread + 992;\n int _metile_register_index_______________________________ = int(_metile_register_packed_______________________________);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v16_r16 = _metile_register_index________________ >= 0;\n bool _metile_v16_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v16_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v16_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v16_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v16_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v16_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v16_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v16_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v16_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v16_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v16_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v16_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v16_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v16_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v16_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v17_r8 = _metile_register_index________ < 1024;\n bool _metile_v17_r9 = _metile_register_index_________ < 1024;\n bool _metile_v17_r10 = _metile_register_index__________ < 1024;\n bool _metile_v17_r11 = _metile_register_index___________ < 1024;\n bool _metile_v17_r12 = _metile_register_index____________ < 1024;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v17_r14 = _metile_register_index______________ < 1024;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v17_r16 = _metile_register_index________________ < 1024;\n bool _metile_v17_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v17_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v17_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v17_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v17_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v17_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v17_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v17_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v17_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v17_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v17_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v17_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v17_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v17_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v17_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n bool _metile_v18_r16 = _metile_v16_r16 & _metile_v17_r16;\n bool _metile_v18_r17 = _metile_v16_r17 & _metile_v17_r17;\n bool _metile_v18_r18 = _metile_v16_r18 & _metile_v17_r18;\n bool _metile_v18_r19 = _metile_v16_r19 & _metile_v17_r19;\n bool _metile_v18_r20 = _metile_v16_r20 & _metile_v17_r20;\n bool _metile_v18_r21 = _metile_v16_r21 & _metile_v17_r21;\n bool _metile_v18_r22 = _metile_v16_r22 & _metile_v17_r22;\n bool _metile_v18_r23 = _metile_v16_r23 & _metile_v17_r23;\n bool _metile_v18_r24 = _metile_v16_r24 & _metile_v17_r24;\n bool _metile_v18_r25 = _metile_v16_r25 & _metile_v17_r25;\n bool _metile_v18_r26 = _metile_v16_r26 & _metile_v17_r26;\n bool _metile_v18_r27 = _metile_v16_r27 & _metile_v17_r27;\n bool _metile_v18_r28 = _metile_v16_r28 & _metile_v17_r28;\n bool _metile_v18_r29 = _metile_v16_r29 & _metile_v17_r29;\n bool _metile_v18_r30 = _metile_v16_r30 & _metile_v17_r30;\n bool _metile_v18_r31 = _metile_v16_r31 & _metile_v17_r31;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n int _off__metile_v19_r16 = v2 + _metile_register_index________________;\n int _off__metile_v19_r17 = v2 + _metile_register_index_________________;\n int _off__metile_v19_r18 = v2 + _metile_register_index__________________;\n int _off__metile_v19_r19 = v2 + _metile_register_index___________________;\n int _off__metile_v19_r20 = v2 + _metile_register_index____________________;\n int _off__metile_v19_r21 = v2 + _metile_register_index_____________________;\n int _off__metile_v19_r22 = v2 + _metile_register_index______________________;\n int _off__metile_v19_r23 = v2 + _metile_register_index_______________________;\n int _off__metile_v19_r24 = v2 + _metile_register_index________________________;\n int _off__metile_v19_r25 = v2 + _metile_register_index_________________________;\n int _off__metile_v19_r26 = v2 + _metile_register_index__________________________;\n int _off__metile_v19_r27 = v2 + _metile_register_index___________________________;\n int _off__metile_v19_r28 = v2 + _metile_register_index____________________________;\n int _off__metile_v19_r29 = v2 + _metile_register_index_____________________________;\n int _off__metile_v19_r30 = v2 + _metile_register_index______________________________;\n int _off__metile_v19_r31 = v2 + _metile_register_index_______________________________;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v20_r4 = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n float _metile_v20_r5 = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n float _metile_v20_r6 = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n float _metile_v20_r7 = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n float _metile_v20_r8 = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n float _metile_v20_r9 = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n float _metile_v20_r10 = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n float _metile_v20_r11 = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n float _metile_v20_r12 = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n float _metile_v20_r13 = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n float _metile_v20_r14 = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n float _metile_v20_r15 = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n float _metile_v20_r16 = _metile_v18_r16 ? X[_off__metile_v19_r16] : static_cast(0);\n float _metile_v20_r17 = _metile_v18_r17 ? X[_off__metile_v19_r17] : static_cast(0);\n float _metile_v20_r18 = _metile_v18_r18 ? X[_off__metile_v19_r18] : static_cast(0);\n float _metile_v20_r19 = _metile_v18_r19 ? X[_off__metile_v19_r19] : static_cast(0);\n float _metile_v20_r20 = _metile_v18_r20 ? X[_off__metile_v19_r20] : static_cast(0);\n float _metile_v20_r21 = _metile_v18_r21 ? X[_off__metile_v19_r21] : static_cast(0);\n float _metile_v20_r22 = _metile_v18_r22 ? X[_off__metile_v19_r22] : static_cast(0);\n float _metile_v20_r23 = _metile_v18_r23 ? X[_off__metile_v19_r23] : static_cast(0);\n float _metile_v20_r24 = _metile_v18_r24 ? X[_off__metile_v19_r24] : static_cast(0);\n float _metile_v20_r25 = _metile_v18_r25 ? X[_off__metile_v19_r25] : static_cast(0);\n float _metile_v20_r26 = _metile_v18_r26 ? X[_off__metile_v19_r26] : static_cast(0);\n float _metile_v20_r27 = _metile_v18_r27 ? X[_off__metile_v19_r27] : static_cast(0);\n float _metile_v20_r28 = _metile_v18_r28 ? X[_off__metile_v19_r28] : static_cast(0);\n float _metile_v20_r29 = _metile_v18_r29 ? X[_off__metile_v19_r29] : static_cast(0);\n float _metile_v20_r30 = _metile_v18_r30 ? X[_off__metile_v19_r30] : static_cast(0);\n float _metile_v20_r31 = _metile_v18_r31 ? X[_off__metile_v19_r31] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v21_r16 = static_cast(_metile_v20_r16);\n float _metile_v21_r17 = static_cast(_metile_v20_r17);\n float _metile_v21_r18 = static_cast(_metile_v20_r18);\n float _metile_v21_r19 = static_cast(_metile_v20_r19);\n float _metile_v21_r20 = static_cast(_metile_v20_r20);\n float _metile_v21_r21 = static_cast(_metile_v20_r21);\n float _metile_v21_r22 = static_cast(_metile_v20_r22);\n float _metile_v21_r23 = static_cast(_metile_v20_r23);\n float _metile_v21_r24 = static_cast(_metile_v20_r24);\n float _metile_v21_r25 = static_cast(_metile_v20_r25);\n float _metile_v21_r26 = static_cast(_metile_v20_r26);\n float _metile_v21_r27 = static_cast(_metile_v20_r27);\n float _metile_v21_r28 = static_cast(_metile_v20_r28);\n float _metile_v21_r29 = static_cast(_metile_v20_r29);\n float _metile_v21_r30 = static_cast(_metile_v20_r30);\n float _metile_v21_r31 = static_cast(_metile_v20_r31);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_v22_r16 = _metile_v21_r16 * _metile_v21_r16;\n float _metile_v22_r17 = _metile_v21_r17 * _metile_v21_r17;\n float _metile_v22_r18 = _metile_v21_r18 * _metile_v21_r18;\n float _metile_v22_r19 = _metile_v21_r19 * _metile_v21_r19;\n float _metile_v22_r20 = _metile_v21_r20 * _metile_v21_r20;\n float _metile_v22_r21 = _metile_v21_r21 * _metile_v21_r21;\n float _metile_v22_r22 = _metile_v21_r22 * _metile_v21_r22;\n float _metile_v22_r23 = _metile_v21_r23 * _metile_v21_r23;\n float _metile_v22_r24 = _metile_v21_r24 * _metile_v21_r24;\n float _metile_v22_r25 = _metile_v21_r25 * _metile_v21_r25;\n float _metile_v22_r26 = _metile_v21_r26 * _metile_v21_r26;\n float _metile_v22_r27 = _metile_v21_r27 * _metile_v21_r27;\n float _metile_v22_r28 = _metile_v21_r28 * _metile_v21_r28;\n float _metile_v22_r29 = _metile_v21_r29 * _metile_v21_r29;\n float _metile_v22_r30 = _metile_v21_r30 * _metile_v21_r30;\n float _metile_v22_r31 = _metile_v21_r31 * _metile_v21_r31;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_v22_r16 + _metile_v22_r17;\n float _metile_register_sum_________ = _metile_v22_r18 + _metile_v22_r19;\n float _metile_register_sum__________ = _metile_v22_r20 + _metile_v22_r21;\n float _metile_register_sum___________ = _metile_v22_r22 + _metile_v22_r23;\n float _metile_register_sum____________ = _metile_v22_r24 + _metile_v22_r25;\n float _metile_register_sum_____________ = _metile_v22_r26 + _metile_v22_r27;\n float _metile_register_sum______________ = _metile_v22_r28 + _metile_v22_r29;\n float _metile_register_sum_______________ = _metile_v22_r30 + _metile_v22_r31;\n float _metile_register_sum________________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________________ = _metile_register_sum____________ + _metile_register_sum_____________;\n float _metile_register_sum_______________________ = _metile_register_sum______________ + _metile_register_sum_______________;\n float _metile_register_sum________________________ = _metile_register_sum________________ + _metile_register_sum_________________;\n float _metile_register_sum_________________________ = _metile_register_sum__________________ + _metile_register_sum___________________;\n float _metile_register_sum__________________________ = _metile_register_sum____________________ + _metile_register_sum_____________________;\n float _metile_register_sum___________________________ = _metile_register_sum______________________ + _metile_register_sum_______________________;\n float _metile_register_sum____________________________ = _metile_register_sum________________________ + _metile_register_sum_________________________;\n float _metile_register_sum_____________________________ = _metile_register_sum__________________________ + _metile_register_sum___________________________;\n float _metile_register_sum______________________________ = _metile_register_sum____________________________ + _metile_register_sum_____________________________;\n float v23 = simd_sum(_metile_register_sum______________________________);\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v32_r16 = _metile_register_index________________ >= 0;\n bool _metile_v32_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v32_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v32_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v32_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v32_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v32_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v32_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v32_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v32_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v32_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v32_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v32_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v32_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v32_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v32_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v33_r8 = _metile_register_index________ < 1024;\n bool _metile_v33_r9 = _metile_register_index_________ < 1024;\n bool _metile_v33_r10 = _metile_register_index__________ < 1024;\n bool _metile_v33_r11 = _metile_register_index___________ < 1024;\n bool _metile_v33_r12 = _metile_register_index____________ < 1024;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v33_r14 = _metile_register_index______________ < 1024;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v33_r16 = _metile_register_index________________ < 1024;\n bool _metile_v33_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v33_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v33_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v33_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v33_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v33_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v33_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v33_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v33_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v33_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v33_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v33_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v33_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v33_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v33_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n bool _metile_v34_r16 = _metile_v32_r16 & _metile_v33_r16;\n bool _metile_v34_r17 = _metile_v32_r17 & _metile_v33_r17;\n bool _metile_v34_r18 = _metile_v32_r18 & _metile_v33_r18;\n bool _metile_v34_r19 = _metile_v32_r19 & _metile_v33_r19;\n bool _metile_v34_r20 = _metile_v32_r20 & _metile_v33_r20;\n bool _metile_v34_r21 = _metile_v32_r21 & _metile_v33_r21;\n bool _metile_v34_r22 = _metile_v32_r22 & _metile_v33_r22;\n bool _metile_v34_r23 = _metile_v32_r23 & _metile_v33_r23;\n bool _metile_v34_r24 = _metile_v32_r24 & _metile_v33_r24;\n bool _metile_v34_r25 = _metile_v32_r25 & _metile_v33_r25;\n bool _metile_v34_r26 = _metile_v32_r26 & _metile_v33_r26;\n bool _metile_v34_r27 = _metile_v32_r27 & _metile_v33_r27;\n bool _metile_v34_r28 = _metile_v32_r28 & _metile_v33_r28;\n bool _metile_v34_r29 = _metile_v32_r29 & _metile_v33_r29;\n bool _metile_v34_r30 = _metile_v32_r30 & _metile_v33_r30;\n bool _metile_v34_r31 = _metile_v32_r31 & _metile_v33_r31;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v36_r4 = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n float _metile_v36_r5 = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n float _metile_v36_r6 = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n float _metile_v36_r7 = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n float _metile_v36_r8 = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n float _metile_v36_r9 = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n float _metile_v36_r10 = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n float _metile_v36_r11 = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n float _metile_v36_r12 = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n float _metile_v36_r13 = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n float _metile_v36_r14 = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n float _metile_v36_r15 = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n float _metile_v36_r16 = _metile_v34_r16 ? W[_metile_register_index________________] : static_cast(0);\n float _metile_v36_r17 = _metile_v34_r17 ? W[_metile_register_index_________________] : static_cast(0);\n float _metile_v36_r18 = _metile_v34_r18 ? W[_metile_register_index__________________] : static_cast(0);\n float _metile_v36_r19 = _metile_v34_r19 ? W[_metile_register_index___________________] : static_cast(0);\n float _metile_v36_r20 = _metile_v34_r20 ? W[_metile_register_index____________________] : static_cast(0);\n float _metile_v36_r21 = _metile_v34_r21 ? W[_metile_register_index_____________________] : static_cast(0);\n float _metile_v36_r22 = _metile_v34_r22 ? W[_metile_register_index______________________] : static_cast(0);\n float _metile_v36_r23 = _metile_v34_r23 ? W[_metile_register_index_______________________] : static_cast(0);\n float _metile_v36_r24 = _metile_v34_r24 ? W[_metile_register_index________________________] : static_cast(0);\n float _metile_v36_r25 = _metile_v34_r25 ? W[_metile_register_index_________________________] : static_cast(0);\n float _metile_v36_r26 = _metile_v34_r26 ? W[_metile_register_index__________________________] : static_cast(0);\n float _metile_v36_r27 = _metile_v34_r27 ? W[_metile_register_index___________________________] : static_cast(0);\n float _metile_v36_r28 = _metile_v34_r28 ? W[_metile_register_index____________________________] : static_cast(0);\n float _metile_v36_r29 = _metile_v34_r29 ? W[_metile_register_index_____________________________] : static_cast(0);\n float _metile_v36_r30 = _metile_v34_r30 ? W[_metile_register_index______________________________] : static_cast(0);\n float _metile_v36_r31 = _metile_v34_r31 ? W[_metile_register_index_______________________________] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v37_r16 = static_cast(_metile_v36_r16);\n float _metile_v37_r17 = static_cast(_metile_v36_r17);\n float _metile_v37_r18 = static_cast(_metile_v36_r18);\n float _metile_v37_r19 = static_cast(_metile_v36_r19);\n float _metile_v37_r20 = static_cast(_metile_v36_r20);\n float _metile_v37_r21 = static_cast(_metile_v36_r21);\n float _metile_v37_r22 = static_cast(_metile_v36_r22);\n float _metile_v37_r23 = static_cast(_metile_v36_r23);\n float _metile_v37_r24 = static_cast(_metile_v36_r24);\n float _metile_v37_r25 = static_cast(_metile_v36_r25);\n float _metile_v37_r26 = static_cast(_metile_v36_r26);\n float _metile_v37_r27 = static_cast(_metile_v36_r27);\n float _metile_v37_r28 = static_cast(_metile_v36_r28);\n float _metile_v37_r29 = static_cast(_metile_v36_r29);\n float _metile_v37_r30 = static_cast(_metile_v36_r30);\n float _metile_v37_r31 = static_cast(_metile_v36_r31);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v38_r16 = _metile_v21_r16 * v29;\n float _metile_v38_r17 = _metile_v21_r17 * v29;\n float _metile_v38_r18 = _metile_v21_r18 * v29;\n float _metile_v38_r19 = _metile_v21_r19 * v29;\n float _metile_v38_r20 = _metile_v21_r20 * v29;\n float _metile_v38_r21 = _metile_v21_r21 * v29;\n float _metile_v38_r22 = _metile_v21_r22 * v29;\n float _metile_v38_r23 = _metile_v21_r23 * v29;\n float _metile_v38_r24 = _metile_v21_r24 * v29;\n float _metile_v38_r25 = _metile_v21_r25 * v29;\n float _metile_v38_r26 = _metile_v21_r26 * v29;\n float _metile_v38_r27 = _metile_v21_r27 * v29;\n float _metile_v38_r28 = _metile_v21_r28 * v29;\n float _metile_v38_r29 = _metile_v21_r29 * v29;\n float _metile_v38_r30 = _metile_v21_r30 * v29;\n float _metile_v38_r31 = _metile_v21_r31 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n float _metile_v39_r16 = _metile_v38_r16 * _metile_v37_r16;\n float _metile_v39_r17 = _metile_v38_r17 * _metile_v37_r17;\n float _metile_v39_r18 = _metile_v38_r18 * _metile_v37_r18;\n float _metile_v39_r19 = _metile_v38_r19 * _metile_v37_r19;\n float _metile_v39_r20 = _metile_v38_r20 * _metile_v37_r20;\n float _metile_v39_r21 = _metile_v38_r21 * _metile_v37_r21;\n float _metile_v39_r22 = _metile_v38_r22 * _metile_v37_r22;\n float _metile_v39_r23 = _metile_v38_r23 * _metile_v37_r23;\n float _metile_v39_r24 = _metile_v38_r24 * _metile_v37_r24;\n float _metile_v39_r25 = _metile_v38_r25 * _metile_v37_r25;\n float _metile_v39_r26 = _metile_v38_r26 * _metile_v37_r26;\n float _metile_v39_r27 = _metile_v38_r27 * _metile_v37_r27;\n float _metile_v39_r28 = _metile_v38_r28 * _metile_v37_r28;\n float _metile_v39_r29 = _metile_v38_r29 * _metile_v37_r29;\n float _metile_v39_r30 = _metile_v38_r30 * _metile_v37_r30;\n float _metile_v39_r31 = _metile_v38_r31 * _metile_v37_r31;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v41_r16 = _metile_register_index________________ >= 0;\n bool _metile_v41_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v41_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v41_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v41_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v41_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v41_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v41_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v41_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v41_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v41_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v41_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v41_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v41_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v41_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v41_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v42_r8 = _metile_register_index________ < 1024;\n bool _metile_v42_r9 = _metile_register_index_________ < 1024;\n bool _metile_v42_r10 = _metile_register_index__________ < 1024;\n bool _metile_v42_r11 = _metile_register_index___________ < 1024;\n bool _metile_v42_r12 = _metile_register_index____________ < 1024;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v42_r14 = _metile_register_index______________ < 1024;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v42_r16 = _metile_register_index________________ < 1024;\n bool _metile_v42_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v42_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v42_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v42_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v42_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v42_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v42_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v42_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v42_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v42_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v42_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v42_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v42_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v42_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v42_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n bool _metile_v43_r16 = _metile_v41_r16 & _metile_v42_r16;\n bool _metile_v43_r17 = _metile_v41_r17 & _metile_v42_r17;\n bool _metile_v43_r18 = _metile_v41_r18 & _metile_v42_r18;\n bool _metile_v43_r19 = _metile_v41_r19 & _metile_v42_r19;\n bool _metile_v43_r20 = _metile_v41_r20 & _metile_v42_r20;\n bool _metile_v43_r21 = _metile_v41_r21 & _metile_v42_r21;\n bool _metile_v43_r22 = _metile_v41_r22 & _metile_v42_r22;\n bool _metile_v43_r23 = _metile_v41_r23 & _metile_v42_r23;\n bool _metile_v43_r24 = _metile_v41_r24 & _metile_v42_r24;\n bool _metile_v43_r25 = _metile_v41_r25 & _metile_v42_r25;\n bool _metile_v43_r26 = _metile_v41_r26 & _metile_v42_r26;\n bool _metile_v43_r27 = _metile_v41_r27 & _metile_v42_r27;\n bool _metile_v43_r28 = _metile_v41_r28 & _metile_v42_r28;\n bool _metile_v43_r29 = _metile_v41_r29 & _metile_v42_r29;\n bool _metile_v43_r30 = _metile_v41_r30 & _metile_v42_r30;\n bool _metile_v43_r31 = _metile_v41_r31 & _metile_v42_r31;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n int _off__metile_v44_r16 = v9 + _metile_register_index________________;\n int _off__metile_v44_r17 = v9 + _metile_register_index_________________;\n int _off__metile_v44_r18 = v9 + _metile_register_index__________________;\n int _off__metile_v44_r19 = v9 + _metile_register_index___________________;\n int _off__metile_v44_r20 = v9 + _metile_register_index____________________;\n int _off__metile_v44_r21 = v9 + _metile_register_index_____________________;\n int _off__metile_v44_r22 = v9 + _metile_register_index______________________;\n int _off__metile_v44_r23 = v9 + _metile_register_index_______________________;\n int _off__metile_v44_r24 = v9 + _metile_register_index________________________;\n int _off__metile_v44_r25 = v9 + _metile_register_index_________________________;\n int _off__metile_v44_r26 = v9 + _metile_register_index__________________________;\n int _off__metile_v44_r27 = v9 + _metile_register_index___________________________;\n int _off__metile_v44_r28 = v9 + _metile_register_index____________________________;\n int _off__metile_v44_r29 = v9 + _metile_register_index_____________________________;\n int _off__metile_v44_r30 = v9 + _metile_register_index______________________________;\n int _off__metile_v44_r31 = v9 + _metile_register_index_______________________________;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = _metile_v39_r4; }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = _metile_v39_r5; }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = _metile_v39_r6; }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = _metile_v39_r7; }\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = _metile_v39_r8; }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = _metile_v39_r9; }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = _metile_v39_r10; }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = _metile_v39_r11; }\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = _metile_v39_r12; }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = _metile_v39_r13; }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = _metile_v39_r14; }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = _metile_v39_r15; }\n if (_metile_v43_r16) { Out[_off__metile_v44_r16] = _metile_v39_r16; }\n if (_metile_v43_r17) { Out[_off__metile_v44_r17] = _metile_v39_r17; }\n if (_metile_v43_r18) { Out[_off__metile_v44_r18] = _metile_v39_r18; }\n if (_metile_v43_r19) { Out[_off__metile_v44_r19] = _metile_v39_r19; }\n if (_metile_v43_r20) { Out[_off__metile_v44_r20] = _metile_v39_r20; }\n if (_metile_v43_r21) { Out[_off__metile_v44_r21] = _metile_v39_r21; }\n if (_metile_v43_r22) { Out[_off__metile_v44_r22] = _metile_v39_r22; }\n if (_metile_v43_r23) { Out[_off__metile_v44_r23] = _metile_v39_r23; }\n if (_metile_v43_r24) { Out[_off__metile_v44_r24] = _metile_v39_r24; }\n if (_metile_v43_r25) { Out[_off__metile_v44_r25] = _metile_v39_r25; }\n if (_metile_v43_r26) { Out[_off__metile_v44_r26] = _metile_v39_r26; }\n if (_metile_v43_r27) { Out[_off__metile_v44_r27] = _metile_v39_r27; }\n if (_metile_v43_r28) { Out[_off__metile_v44_r28] = _metile_v39_r28; }\n if (_metile_v43_r29) { Out[_off__metile_v44_r29] = _metile_v39_r29; }\n if (_metile_v43_r30) { Out[_off__metile_v44_r30] = _metile_v39_r30; }\n if (_metile_v43_r31) { Out[_off__metile_v44_r31] = _metile_v39_r31; }\n}", "source_sha256": "ad4bf6c168b8be3158fdb141b4692d160c0a3ff22ae8336b2fe017e3812a192f", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 32, 1, 1 ], "is_gemm": false, "prefer_ordered": false, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 32, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 32 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 32, "threads": 32, "scratch": null, "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 576, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 215.5625, "control": 215.813, "speedup": 1.0011620759640476 }, "gpu_us": { "candidate": 8.124974556267262, "control": 8.000002708286047, "speedup": 0.9846188013124525 } } }, { "frozen_register4": { "pairs": 576, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 217.08350000000002, "control": 217.042, "speedup": 0.9998088293214361 }, "gpu_us": { "candidate": 8.124974556267262, "control": 8.000002708286047, "speedup": 0.9846188013124525 } } }, { "frozen_register4": { "pairs": 579, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 215.916, "control": 217.0, "speedup": 1.005020470923878 }, "gpu_us": { "candidate": 8.083356078714132, "control": 8.04167939350009, "speedup": 0.9948441359247071 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0019946943293472, "round_speedups": [ 1.0011620759640476, 0.9998088293214361, 1.005020470923878 ], "candidate": 216.18635751814583, "control": 216.6175832195698 }, "gpu_us": { "speedup": 0.9880155148105952, "round_speedups": [ 0.9846188013124525, 0.9846188013124525, 0.9948441359247071 ], "candidate": 8.111077975899041, "control": 8.013870882026776 } } } }, { "name": "float32_256x1024", "dtype": "float32", "batches": 256, "width": 1024, "status": "measured", "variant": { "name": "register32_blocked4", "elements_per_thread": 32, "layout": "blocked4" }, "input_sha256": "d91bbc8e56d1e705bcdef1e433ae3b5ce1d9e73a225cd6afc919bf59342546a9", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 31;\n int _metile_register_index = int((((_metile_bounded_thread >> 5) & 1u) << 0) | (((_metile_bounded_thread >> 6) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 7) & 1u) << 7) | (((_metile_bounded_thread >> 8) & 1u) << 8) | (((_metile_bounded_thread >> 9) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 32;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 5) & 1u) << 0) | (((_metile_register_packed_ >> 6) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 7) & 1u) << 7) | (((_metile_register_packed_ >> 8) & 1u) << 8) | (((_metile_register_packed_ >> 9) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 64;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 5) & 1u) << 0) | (((_metile_register_packed__ >> 6) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 7) & 1u) << 7) | (((_metile_register_packed__ >> 8) & 1u) << 8) | (((_metile_register_packed__ >> 9) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 96;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 5) & 1u) << 0) | (((_metile_register_packed___ >> 6) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 7) & 1u) << 7) | (((_metile_register_packed___ >> 8) & 1u) << 8) | (((_metile_register_packed___ >> 9) & 1u) << 9));\n int _metile_register_packed____ = _metile_bounded_thread + 128;\n int _metile_register_index____ = int((((_metile_register_packed____ >> 5) & 1u) << 0) | (((_metile_register_packed____ >> 6) & 1u) << 1) | (((_metile_register_packed____ >> 0) & 1u) << 2) | (((_metile_register_packed____ >> 1) & 1u) << 3) | (((_metile_register_packed____ >> 2) & 1u) << 4) | (((_metile_register_packed____ >> 3) & 1u) << 5) | (((_metile_register_packed____ >> 4) & 1u) << 6) | (((_metile_register_packed____ >> 7) & 1u) << 7) | (((_metile_register_packed____ >> 8) & 1u) << 8) | (((_metile_register_packed____ >> 9) & 1u) << 9));\n int _metile_register_packed_____ = _metile_bounded_thread + 160;\n int _metile_register_index_____ = int((((_metile_register_packed_____ >> 5) & 1u) << 0) | (((_metile_register_packed_____ >> 6) & 1u) << 1) | (((_metile_register_packed_____ >> 0) & 1u) << 2) | (((_metile_register_packed_____ >> 1) & 1u) << 3) | (((_metile_register_packed_____ >> 2) & 1u) << 4) | (((_metile_register_packed_____ >> 3) & 1u) << 5) | (((_metile_register_packed_____ >> 4) & 1u) << 6) | (((_metile_register_packed_____ >> 7) & 1u) << 7) | (((_metile_register_packed_____ >> 8) & 1u) << 8) | (((_metile_register_packed_____ >> 9) & 1u) << 9));\n int _metile_register_packed______ = _metile_bounded_thread + 192;\n int _metile_register_index______ = int((((_metile_register_packed______ >> 5) & 1u) << 0) | (((_metile_register_packed______ >> 6) & 1u) << 1) | (((_metile_register_packed______ >> 0) & 1u) << 2) | (((_metile_register_packed______ >> 1) & 1u) << 3) | (((_metile_register_packed______ >> 2) & 1u) << 4) | (((_metile_register_packed______ >> 3) & 1u) << 5) | (((_metile_register_packed______ >> 4) & 1u) << 6) | (((_metile_register_packed______ >> 7) & 1u) << 7) | (((_metile_register_packed______ >> 8) & 1u) << 8) | (((_metile_register_packed______ >> 9) & 1u) << 9));\n int _metile_register_packed_______ = _metile_bounded_thread + 224;\n int _metile_register_index_______ = int((((_metile_register_packed_______ >> 5) & 1u) << 0) | (((_metile_register_packed_______ >> 6) & 1u) << 1) | (((_metile_register_packed_______ >> 0) & 1u) << 2) | (((_metile_register_packed_______ >> 1) & 1u) << 3) | (((_metile_register_packed_______ >> 2) & 1u) << 4) | (((_metile_register_packed_______ >> 3) & 1u) << 5) | (((_metile_register_packed_______ >> 4) & 1u) << 6) | (((_metile_register_packed_______ >> 7) & 1u) << 7) | (((_metile_register_packed_______ >> 8) & 1u) << 8) | (((_metile_register_packed_______ >> 9) & 1u) << 9));\n int _metile_register_packed________ = _metile_bounded_thread + 256;\n int _metile_register_index________ = int((((_metile_register_packed________ >> 5) & 1u) << 0) | (((_metile_register_packed________ >> 6) & 1u) << 1) | (((_metile_register_packed________ >> 0) & 1u) << 2) | (((_metile_register_packed________ >> 1) & 1u) << 3) | (((_metile_register_packed________ >> 2) & 1u) << 4) | (((_metile_register_packed________ >> 3) & 1u) << 5) | (((_metile_register_packed________ >> 4) & 1u) << 6) | (((_metile_register_packed________ >> 7) & 1u) << 7) | (((_metile_register_packed________ >> 8) & 1u) << 8) | (((_metile_register_packed________ >> 9) & 1u) << 9));\n int _metile_register_packed_________ = _metile_bounded_thread + 288;\n int _metile_register_index_________ = int((((_metile_register_packed_________ >> 5) & 1u) << 0) | (((_metile_register_packed_________ >> 6) & 1u) << 1) | (((_metile_register_packed_________ >> 0) & 1u) << 2) | (((_metile_register_packed_________ >> 1) & 1u) << 3) | (((_metile_register_packed_________ >> 2) & 1u) << 4) | (((_metile_register_packed_________ >> 3) & 1u) << 5) | (((_metile_register_packed_________ >> 4) & 1u) << 6) | (((_metile_register_packed_________ >> 7) & 1u) << 7) | (((_metile_register_packed_________ >> 8) & 1u) << 8) | (((_metile_register_packed_________ >> 9) & 1u) << 9));\n int _metile_register_packed__________ = _metile_bounded_thread + 320;\n int _metile_register_index__________ = int((((_metile_register_packed__________ >> 5) & 1u) << 0) | (((_metile_register_packed__________ >> 6) & 1u) << 1) | (((_metile_register_packed__________ >> 0) & 1u) << 2) | (((_metile_register_packed__________ >> 1) & 1u) << 3) | (((_metile_register_packed__________ >> 2) & 1u) << 4) | (((_metile_register_packed__________ >> 3) & 1u) << 5) | (((_metile_register_packed__________ >> 4) & 1u) << 6) | (((_metile_register_packed__________ >> 7) & 1u) << 7) | (((_metile_register_packed__________ >> 8) & 1u) << 8) | (((_metile_register_packed__________ >> 9) & 1u) << 9));\n int _metile_register_packed___________ = _metile_bounded_thread + 352;\n int _metile_register_index___________ = int((((_metile_register_packed___________ >> 5) & 1u) << 0) | (((_metile_register_packed___________ >> 6) & 1u) << 1) | (((_metile_register_packed___________ >> 0) & 1u) << 2) | (((_metile_register_packed___________ >> 1) & 1u) << 3) | (((_metile_register_packed___________ >> 2) & 1u) << 4) | (((_metile_register_packed___________ >> 3) & 1u) << 5) | (((_metile_register_packed___________ >> 4) & 1u) << 6) | (((_metile_register_packed___________ >> 7) & 1u) << 7) | (((_metile_register_packed___________ >> 8) & 1u) << 8) | (((_metile_register_packed___________ >> 9) & 1u) << 9));\n int _metile_register_packed____________ = _metile_bounded_thread + 384;\n int _metile_register_index____________ = int((((_metile_register_packed____________ >> 5) & 1u) << 0) | (((_metile_register_packed____________ >> 6) & 1u) << 1) | (((_metile_register_packed____________ >> 0) & 1u) << 2) | (((_metile_register_packed____________ >> 1) & 1u) << 3) | (((_metile_register_packed____________ >> 2) & 1u) << 4) | (((_metile_register_packed____________ >> 3) & 1u) << 5) | (((_metile_register_packed____________ >> 4) & 1u) << 6) | (((_metile_register_packed____________ >> 7) & 1u) << 7) | (((_metile_register_packed____________ >> 8) & 1u) << 8) | (((_metile_register_packed____________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________ = _metile_bounded_thread + 416;\n int _metile_register_index_____________ = int((((_metile_register_packed_____________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________ >> 9) & 1u) << 9));\n int _metile_register_packed______________ = _metile_bounded_thread + 448;\n int _metile_register_index______________ = int((((_metile_register_packed______________ >> 5) & 1u) << 0) | (((_metile_register_packed______________ >> 6) & 1u) << 1) | (((_metile_register_packed______________ >> 0) & 1u) << 2) | (((_metile_register_packed______________ >> 1) & 1u) << 3) | (((_metile_register_packed______________ >> 2) & 1u) << 4) | (((_metile_register_packed______________ >> 3) & 1u) << 5) | (((_metile_register_packed______________ >> 4) & 1u) << 6) | (((_metile_register_packed______________ >> 7) & 1u) << 7) | (((_metile_register_packed______________ >> 8) & 1u) << 8) | (((_metile_register_packed______________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________ = _metile_bounded_thread + 480;\n int _metile_register_index_______________ = int((((_metile_register_packed_______________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________ >> 9) & 1u) << 9));\n int _metile_register_packed________________ = _metile_bounded_thread + 512;\n int _metile_register_index________________ = int((((_metile_register_packed________________ >> 5) & 1u) << 0) | (((_metile_register_packed________________ >> 6) & 1u) << 1) | (((_metile_register_packed________________ >> 0) & 1u) << 2) | (((_metile_register_packed________________ >> 1) & 1u) << 3) | (((_metile_register_packed________________ >> 2) & 1u) << 4) | (((_metile_register_packed________________ >> 3) & 1u) << 5) | (((_metile_register_packed________________ >> 4) & 1u) << 6) | (((_metile_register_packed________________ >> 7) & 1u) << 7) | (((_metile_register_packed________________ >> 8) & 1u) << 8) | (((_metile_register_packed________________ >> 9) & 1u) << 9));\n int _metile_register_packed_________________ = _metile_bounded_thread + 544;\n int _metile_register_index_________________ = int((((_metile_register_packed_________________ >> 5) & 1u) << 0) | (((_metile_register_packed_________________ >> 6) & 1u) << 1) | (((_metile_register_packed_________________ >> 0) & 1u) << 2) | (((_metile_register_packed_________________ >> 1) & 1u) << 3) | (((_metile_register_packed_________________ >> 2) & 1u) << 4) | (((_metile_register_packed_________________ >> 3) & 1u) << 5) | (((_metile_register_packed_________________ >> 4) & 1u) << 6) | (((_metile_register_packed_________________ >> 7) & 1u) << 7) | (((_metile_register_packed_________________ >> 8) & 1u) << 8) | (((_metile_register_packed_________________ >> 9) & 1u) << 9));\n int _metile_register_packed__________________ = _metile_bounded_thread + 576;\n int _metile_register_index__________________ = int((((_metile_register_packed__________________ >> 5) & 1u) << 0) | (((_metile_register_packed__________________ >> 6) & 1u) << 1) | (((_metile_register_packed__________________ >> 0) & 1u) << 2) | (((_metile_register_packed__________________ >> 1) & 1u) << 3) | (((_metile_register_packed__________________ >> 2) & 1u) << 4) | (((_metile_register_packed__________________ >> 3) & 1u) << 5) | (((_metile_register_packed__________________ >> 4) & 1u) << 6) | (((_metile_register_packed__________________ >> 7) & 1u) << 7) | (((_metile_register_packed__________________ >> 8) & 1u) << 8) | (((_metile_register_packed__________________ >> 9) & 1u) << 9));\n int _metile_register_packed___________________ = _metile_bounded_thread + 608;\n int _metile_register_index___________________ = int((((_metile_register_packed___________________ >> 5) & 1u) << 0) | (((_metile_register_packed___________________ >> 6) & 1u) << 1) | (((_metile_register_packed___________________ >> 0) & 1u) << 2) | (((_metile_register_packed___________________ >> 1) & 1u) << 3) | (((_metile_register_packed___________________ >> 2) & 1u) << 4) | (((_metile_register_packed___________________ >> 3) & 1u) << 5) | (((_metile_register_packed___________________ >> 4) & 1u) << 6) | (((_metile_register_packed___________________ >> 7) & 1u) << 7) | (((_metile_register_packed___________________ >> 8) & 1u) << 8) | (((_metile_register_packed___________________ >> 9) & 1u) << 9));\n int _metile_register_packed____________________ = _metile_bounded_thread + 640;\n int _metile_register_index____________________ = int((((_metile_register_packed____________________ >> 5) & 1u) << 0) | (((_metile_register_packed____________________ >> 6) & 1u) << 1) | (((_metile_register_packed____________________ >> 0) & 1u) << 2) | (((_metile_register_packed____________________ >> 1) & 1u) << 3) | (((_metile_register_packed____________________ >> 2) & 1u) << 4) | (((_metile_register_packed____________________ >> 3) & 1u) << 5) | (((_metile_register_packed____________________ >> 4) & 1u) << 6) | (((_metile_register_packed____________________ >> 7) & 1u) << 7) | (((_metile_register_packed____________________ >> 8) & 1u) << 8) | (((_metile_register_packed____________________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________________ = _metile_bounded_thread + 672;\n int _metile_register_index_____________________ = int((((_metile_register_packed_____________________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________________ >> 9) & 1u) << 9));\n int _metile_register_packed______________________ = _metile_bounded_thread + 704;\n int _metile_register_index______________________ = int((((_metile_register_packed______________________ >> 5) & 1u) << 0) | (((_metile_register_packed______________________ >> 6) & 1u) << 1) | (((_metile_register_packed______________________ >> 0) & 1u) << 2) | (((_metile_register_packed______________________ >> 1) & 1u) << 3) | (((_metile_register_packed______________________ >> 2) & 1u) << 4) | (((_metile_register_packed______________________ >> 3) & 1u) << 5) | (((_metile_register_packed______________________ >> 4) & 1u) << 6) | (((_metile_register_packed______________________ >> 7) & 1u) << 7) | (((_metile_register_packed______________________ >> 8) & 1u) << 8) | (((_metile_register_packed______________________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________________ = _metile_bounded_thread + 736;\n int _metile_register_index_______________________ = int((((_metile_register_packed_______________________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________________ >> 9) & 1u) << 9));\n int _metile_register_packed________________________ = _metile_bounded_thread + 768;\n int _metile_register_index________________________ = int((((_metile_register_packed________________________ >> 5) & 1u) << 0) | (((_metile_register_packed________________________ >> 6) & 1u) << 1) | (((_metile_register_packed________________________ >> 0) & 1u) << 2) | (((_metile_register_packed________________________ >> 1) & 1u) << 3) | (((_metile_register_packed________________________ >> 2) & 1u) << 4) | (((_metile_register_packed________________________ >> 3) & 1u) << 5) | (((_metile_register_packed________________________ >> 4) & 1u) << 6) | (((_metile_register_packed________________________ >> 7) & 1u) << 7) | (((_metile_register_packed________________________ >> 8) & 1u) << 8) | (((_metile_register_packed________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_________________________ = _metile_bounded_thread + 800;\n int _metile_register_index_________________________ = int((((_metile_register_packed_________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_________________________ >> 9) & 1u) << 9));\n int _metile_register_packed__________________________ = _metile_bounded_thread + 832;\n int _metile_register_index__________________________ = int((((_metile_register_packed__________________________ >> 5) & 1u) << 0) | (((_metile_register_packed__________________________ >> 6) & 1u) << 1) | (((_metile_register_packed__________________________ >> 0) & 1u) << 2) | (((_metile_register_packed__________________________ >> 1) & 1u) << 3) | (((_metile_register_packed__________________________ >> 2) & 1u) << 4) | (((_metile_register_packed__________________________ >> 3) & 1u) << 5) | (((_metile_register_packed__________________________ >> 4) & 1u) << 6) | (((_metile_register_packed__________________________ >> 7) & 1u) << 7) | (((_metile_register_packed__________________________ >> 8) & 1u) << 8) | (((_metile_register_packed__________________________ >> 9) & 1u) << 9));\n int _metile_register_packed___________________________ = _metile_bounded_thread + 864;\n int _metile_register_index___________________________ = int((((_metile_register_packed___________________________ >> 5) & 1u) << 0) | (((_metile_register_packed___________________________ >> 6) & 1u) << 1) | (((_metile_register_packed___________________________ >> 0) & 1u) << 2) | (((_metile_register_packed___________________________ >> 1) & 1u) << 3) | (((_metile_register_packed___________________________ >> 2) & 1u) << 4) | (((_metile_register_packed___________________________ >> 3) & 1u) << 5) | (((_metile_register_packed___________________________ >> 4) & 1u) << 6) | (((_metile_register_packed___________________________ >> 7) & 1u) << 7) | (((_metile_register_packed___________________________ >> 8) & 1u) << 8) | (((_metile_register_packed___________________________ >> 9) & 1u) << 9));\n int _metile_register_packed____________________________ = _metile_bounded_thread + 896;\n int _metile_register_index____________________________ = int((((_metile_register_packed____________________________ >> 5) & 1u) << 0) | (((_metile_register_packed____________________________ >> 6) & 1u) << 1) | (((_metile_register_packed____________________________ >> 0) & 1u) << 2) | (((_metile_register_packed____________________________ >> 1) & 1u) << 3) | (((_metile_register_packed____________________________ >> 2) & 1u) << 4) | (((_metile_register_packed____________________________ >> 3) & 1u) << 5) | (((_metile_register_packed____________________________ >> 4) & 1u) << 6) | (((_metile_register_packed____________________________ >> 7) & 1u) << 7) | (((_metile_register_packed____________________________ >> 8) & 1u) << 8) | (((_metile_register_packed____________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_____________________________ = _metile_bounded_thread + 928;\n int _metile_register_index_____________________________ = int((((_metile_register_packed_____________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_____________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_____________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_____________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_____________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_____________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_____________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_____________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_____________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_____________________________ >> 9) & 1u) << 9));\n int _metile_register_packed______________________________ = _metile_bounded_thread + 960;\n int _metile_register_index______________________________ = int((((_metile_register_packed______________________________ >> 5) & 1u) << 0) | (((_metile_register_packed______________________________ >> 6) & 1u) << 1) | (((_metile_register_packed______________________________ >> 0) & 1u) << 2) | (((_metile_register_packed______________________________ >> 1) & 1u) << 3) | (((_metile_register_packed______________________________ >> 2) & 1u) << 4) | (((_metile_register_packed______________________________ >> 3) & 1u) << 5) | (((_metile_register_packed______________________________ >> 4) & 1u) << 6) | (((_metile_register_packed______________________________ >> 7) & 1u) << 7) | (((_metile_register_packed______________________________ >> 8) & 1u) << 8) | (((_metile_register_packed______________________________ >> 9) & 1u) << 9));\n int _metile_register_packed_______________________________ = _metile_bounded_thread + 992;\n int _metile_register_index_______________________________ = int((((_metile_register_packed_______________________________ >> 5) & 1u) << 0) | (((_metile_register_packed_______________________________ >> 6) & 1u) << 1) | (((_metile_register_packed_______________________________ >> 0) & 1u) << 2) | (((_metile_register_packed_______________________________ >> 1) & 1u) << 3) | (((_metile_register_packed_______________________________ >> 2) & 1u) << 4) | (((_metile_register_packed_______________________________ >> 3) & 1u) << 5) | (((_metile_register_packed_______________________________ >> 4) & 1u) << 6) | (((_metile_register_packed_______________________________ >> 7) & 1u) << 7) | (((_metile_register_packed_______________________________ >> 8) & 1u) << 8) | (((_metile_register_packed_______________________________ >> 9) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v16_r4 = _metile_register_index____ >= 0;\n bool _metile_v16_r5 = _metile_register_index_____ >= 0;\n bool _metile_v16_r6 = _metile_register_index______ >= 0;\n bool _metile_v16_r7 = _metile_register_index_______ >= 0;\n bool _metile_v16_r8 = _metile_register_index________ >= 0;\n bool _metile_v16_r9 = _metile_register_index_________ >= 0;\n bool _metile_v16_r10 = _metile_register_index__________ >= 0;\n bool _metile_v16_r11 = _metile_register_index___________ >= 0;\n bool _metile_v16_r12 = _metile_register_index____________ >= 0;\n bool _metile_v16_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v16_r14 = _metile_register_index______________ >= 0;\n bool _metile_v16_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v16_r16 = _metile_register_index________________ >= 0;\n bool _metile_v16_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v16_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v16_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v16_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v16_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v16_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v16_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v16_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v16_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v16_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v16_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v16_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v16_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v16_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v16_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v17_r4 = _metile_register_index____ < 1024;\n bool _metile_v17_r5 = _metile_register_index_____ < 1024;\n bool _metile_v17_r6 = _metile_register_index______ < 1024;\n bool _metile_v17_r7 = _metile_register_index_______ < 1024;\n bool _metile_v17_r8 = _metile_register_index________ < 1024;\n bool _metile_v17_r9 = _metile_register_index_________ < 1024;\n bool _metile_v17_r10 = _metile_register_index__________ < 1024;\n bool _metile_v17_r11 = _metile_register_index___________ < 1024;\n bool _metile_v17_r12 = _metile_register_index____________ < 1024;\n bool _metile_v17_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v17_r14 = _metile_register_index______________ < 1024;\n bool _metile_v17_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v17_r16 = _metile_register_index________________ < 1024;\n bool _metile_v17_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v17_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v17_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v17_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v17_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v17_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v17_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v17_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v17_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v17_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v17_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v17_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v17_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v17_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v17_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n bool _metile_v18_r4 = _metile_v16_r4 & _metile_v17_r4;\n bool _metile_v18_r5 = _metile_v16_r5 & _metile_v17_r5;\n bool _metile_v18_r6 = _metile_v16_r6 & _metile_v17_r6;\n bool _metile_v18_r7 = _metile_v16_r7 & _metile_v17_r7;\n bool _metile_v18_r8 = _metile_v16_r8 & _metile_v17_r8;\n bool _metile_v18_r9 = _metile_v16_r9 & _metile_v17_r9;\n bool _metile_v18_r10 = _metile_v16_r10 & _metile_v17_r10;\n bool _metile_v18_r11 = _metile_v16_r11 & _metile_v17_r11;\n bool _metile_v18_r12 = _metile_v16_r12 & _metile_v17_r12;\n bool _metile_v18_r13 = _metile_v16_r13 & _metile_v17_r13;\n bool _metile_v18_r14 = _metile_v16_r14 & _metile_v17_r14;\n bool _metile_v18_r15 = _metile_v16_r15 & _metile_v17_r15;\n bool _metile_v18_r16 = _metile_v16_r16 & _metile_v17_r16;\n bool _metile_v18_r17 = _metile_v16_r17 & _metile_v17_r17;\n bool _metile_v18_r18 = _metile_v16_r18 & _metile_v17_r18;\n bool _metile_v18_r19 = _metile_v16_r19 & _metile_v17_r19;\n bool _metile_v18_r20 = _metile_v16_r20 & _metile_v17_r20;\n bool _metile_v18_r21 = _metile_v16_r21 & _metile_v17_r21;\n bool _metile_v18_r22 = _metile_v16_r22 & _metile_v17_r22;\n bool _metile_v18_r23 = _metile_v16_r23 & _metile_v17_r23;\n bool _metile_v18_r24 = _metile_v16_r24 & _metile_v17_r24;\n bool _metile_v18_r25 = _metile_v16_r25 & _metile_v17_r25;\n bool _metile_v18_r26 = _metile_v16_r26 & _metile_v17_r26;\n bool _metile_v18_r27 = _metile_v16_r27 & _metile_v17_r27;\n bool _metile_v18_r28 = _metile_v16_r28 & _metile_v17_r28;\n bool _metile_v18_r29 = _metile_v16_r29 & _metile_v17_r29;\n bool _metile_v18_r30 = _metile_v16_r30 & _metile_v17_r30;\n bool _metile_v18_r31 = _metile_v16_r31 & _metile_v17_r31;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n int _off__metile_v19_r4 = v2 + _metile_register_index____;\n int _off__metile_v19_r5 = v2 + _metile_register_index_____;\n int _off__metile_v19_r6 = v2 + _metile_register_index______;\n int _off__metile_v19_r7 = v2 + _metile_register_index_______;\n int _off__metile_v19_r8 = v2 + _metile_register_index________;\n int _off__metile_v19_r9 = v2 + _metile_register_index_________;\n int _off__metile_v19_r10 = v2 + _metile_register_index__________;\n int _off__metile_v19_r11 = v2 + _metile_register_index___________;\n int _off__metile_v19_r12 = v2 + _metile_register_index____________;\n int _off__metile_v19_r13 = v2 + _metile_register_index_____________;\n int _off__metile_v19_r14 = v2 + _metile_register_index______________;\n int _off__metile_v19_r15 = v2 + _metile_register_index_______________;\n int _off__metile_v19_r16 = v2 + _metile_register_index________________;\n int _off__metile_v19_r17 = v2 + _metile_register_index_________________;\n int _off__metile_v19_r18 = v2 + _metile_register_index__________________;\n int _off__metile_v19_r19 = v2 + _metile_register_index___________________;\n int _off__metile_v19_r20 = v2 + _metile_register_index____________________;\n int _off__metile_v19_r21 = v2 + _metile_register_index_____________________;\n int _off__metile_v19_r22 = v2 + _metile_register_index______________________;\n int _off__metile_v19_r23 = v2 + _metile_register_index_______________________;\n int _off__metile_v19_r24 = v2 + _metile_register_index________________________;\n int _off__metile_v19_r25 = v2 + _metile_register_index_________________________;\n int _off__metile_v19_r26 = v2 + _metile_register_index__________________________;\n int _off__metile_v19_r27 = v2 + _metile_register_index___________________________;\n int _off__metile_v19_r28 = v2 + _metile_register_index____________________________;\n int _off__metile_v19_r29 = v2 + _metile_register_index_____________________________;\n int _off__metile_v19_r30 = v2 + _metile_register_index______________________________;\n int _off__metile_v19_r31 = v2 + _metile_register_index_______________________________;\n float4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = float4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n float _metile_v20_r0 = _metile_vector_load[0];\n float _metile_v20_r1 = _metile_vector_load[1];\n float _metile_v20_r2 = _metile_vector_load[2];\n float _metile_v20_r3 = _metile_vector_load[3];\n float4 _metile_vector_load_;\n if ((_metile_v18_r4) && (_metile_v18_r5) && (_metile_v18_r6) && (_metile_v18_r7) && (long(_off__metile_v19_r5) == long(_off__metile_v19_r4) + 1) && (long(_off__metile_v19_r6) == long(_off__metile_v19_r4) + 2) && (long(_off__metile_v19_r7) == long(_off__metile_v19_r4) + 3)) {\n _metile_vector_load_ = float4(*reinterpret_cast(X + _off__metile_v19_r4));\n } else {\n _metile_vector_load_[0] = _metile_v18_r4 ? X[_off__metile_v19_r4] : static_cast(0);\n _metile_vector_load_[1] = _metile_v18_r5 ? X[_off__metile_v19_r5] : static_cast(0);\n _metile_vector_load_[2] = _metile_v18_r6 ? X[_off__metile_v19_r6] : static_cast(0);\n _metile_vector_load_[3] = _metile_v18_r7 ? X[_off__metile_v19_r7] : static_cast(0);\n }\n float _metile_v20_r4 = _metile_vector_load_[0];\n float _metile_v20_r5 = _metile_vector_load_[1];\n float _metile_v20_r6 = _metile_vector_load_[2];\n float _metile_v20_r7 = _metile_vector_load_[3];\n float4 _metile_vector_load__;\n if ((_metile_v18_r8) && (_metile_v18_r9) && (_metile_v18_r10) && (_metile_v18_r11) && (long(_off__metile_v19_r9) == long(_off__metile_v19_r8) + 1) && (long(_off__metile_v19_r10) == long(_off__metile_v19_r8) + 2) && (long(_off__metile_v19_r11) == long(_off__metile_v19_r8) + 3)) {\n _metile_vector_load__ = float4(*reinterpret_cast(X + _off__metile_v19_r8));\n } else {\n _metile_vector_load__[0] = _metile_v18_r8 ? X[_off__metile_v19_r8] : static_cast(0);\n _metile_vector_load__[1] = _metile_v18_r9 ? X[_off__metile_v19_r9] : static_cast(0);\n _metile_vector_load__[2] = _metile_v18_r10 ? X[_off__metile_v19_r10] : static_cast(0);\n _metile_vector_load__[3] = _metile_v18_r11 ? X[_off__metile_v19_r11] : static_cast(0);\n }\n float _metile_v20_r8 = _metile_vector_load__[0];\n float _metile_v20_r9 = _metile_vector_load__[1];\n float _metile_v20_r10 = _metile_vector_load__[2];\n float _metile_v20_r11 = _metile_vector_load__[3];\n float4 _metile_vector_load___;\n if ((_metile_v18_r12) && (_metile_v18_r13) && (_metile_v18_r14) && (_metile_v18_r15) && (long(_off__metile_v19_r13) == long(_off__metile_v19_r12) + 1) && (long(_off__metile_v19_r14) == long(_off__metile_v19_r12) + 2) && (long(_off__metile_v19_r15) == long(_off__metile_v19_r12) + 3)) {\n _metile_vector_load___ = float4(*reinterpret_cast(X + _off__metile_v19_r12));\n } else {\n _metile_vector_load___[0] = _metile_v18_r12 ? X[_off__metile_v19_r12] : static_cast(0);\n _metile_vector_load___[1] = _metile_v18_r13 ? X[_off__metile_v19_r13] : static_cast(0);\n _metile_vector_load___[2] = _metile_v18_r14 ? X[_off__metile_v19_r14] : static_cast(0);\n _metile_vector_load___[3] = _metile_v18_r15 ? X[_off__metile_v19_r15] : static_cast(0);\n }\n float _metile_v20_r12 = _metile_vector_load___[0];\n float _metile_v20_r13 = _metile_vector_load___[1];\n float _metile_v20_r14 = _metile_vector_load___[2];\n float _metile_v20_r15 = _metile_vector_load___[3];\n float4 _metile_vector_load____;\n if ((_metile_v18_r16) && (_metile_v18_r17) && (_metile_v18_r18) && (_metile_v18_r19) && (long(_off__metile_v19_r17) == long(_off__metile_v19_r16) + 1) && (long(_off__metile_v19_r18) == long(_off__metile_v19_r16) + 2) && (long(_off__metile_v19_r19) == long(_off__metile_v19_r16) + 3)) {\n _metile_vector_load____ = float4(*reinterpret_cast(X + _off__metile_v19_r16));\n } else {\n _metile_vector_load____[0] = _metile_v18_r16 ? X[_off__metile_v19_r16] : static_cast(0);\n _metile_vector_load____[1] = _metile_v18_r17 ? X[_off__metile_v19_r17] : static_cast(0);\n _metile_vector_load____[2] = _metile_v18_r18 ? X[_off__metile_v19_r18] : static_cast(0);\n _metile_vector_load____[3] = _metile_v18_r19 ? X[_off__metile_v19_r19] : static_cast(0);\n }\n float _metile_v20_r16 = _metile_vector_load____[0];\n float _metile_v20_r17 = _metile_vector_load____[1];\n float _metile_v20_r18 = _metile_vector_load____[2];\n float _metile_v20_r19 = _metile_vector_load____[3];\n float4 _metile_vector_load_____;\n if ((_metile_v18_r20) && (_metile_v18_r21) && (_metile_v18_r22) && (_metile_v18_r23) && (long(_off__metile_v19_r21) == long(_off__metile_v19_r20) + 1) && (long(_off__metile_v19_r22) == long(_off__metile_v19_r20) + 2) && (long(_off__metile_v19_r23) == long(_off__metile_v19_r20) + 3)) {\n _metile_vector_load_____ = float4(*reinterpret_cast(X + _off__metile_v19_r20));\n } else {\n _metile_vector_load_____[0] = _metile_v18_r20 ? X[_off__metile_v19_r20] : static_cast(0);\n _metile_vector_load_____[1] = _metile_v18_r21 ? X[_off__metile_v19_r21] : static_cast(0);\n _metile_vector_load_____[2] = _metile_v18_r22 ? X[_off__metile_v19_r22] : static_cast(0);\n _metile_vector_load_____[3] = _metile_v18_r23 ? X[_off__metile_v19_r23] : static_cast(0);\n }\n float _metile_v20_r20 = _metile_vector_load_____[0];\n float _metile_v20_r21 = _metile_vector_load_____[1];\n float _metile_v20_r22 = _metile_vector_load_____[2];\n float _metile_v20_r23 = _metile_vector_load_____[3];\n float4 _metile_vector_load______;\n if ((_metile_v18_r24) && (_metile_v18_r25) && (_metile_v18_r26) && (_metile_v18_r27) && (long(_off__metile_v19_r25) == long(_off__metile_v19_r24) + 1) && (long(_off__metile_v19_r26) == long(_off__metile_v19_r24) + 2) && (long(_off__metile_v19_r27) == long(_off__metile_v19_r24) + 3)) {\n _metile_vector_load______ = float4(*reinterpret_cast(X + _off__metile_v19_r24));\n } else {\n _metile_vector_load______[0] = _metile_v18_r24 ? X[_off__metile_v19_r24] : static_cast(0);\n _metile_vector_load______[1] = _metile_v18_r25 ? X[_off__metile_v19_r25] : static_cast(0);\n _metile_vector_load______[2] = _metile_v18_r26 ? X[_off__metile_v19_r26] : static_cast(0);\n _metile_vector_load______[3] = _metile_v18_r27 ? X[_off__metile_v19_r27] : static_cast(0);\n }\n float _metile_v20_r24 = _metile_vector_load______[0];\n float _metile_v20_r25 = _metile_vector_load______[1];\n float _metile_v20_r26 = _metile_vector_load______[2];\n float _metile_v20_r27 = _metile_vector_load______[3];\n float4 _metile_vector_load_______;\n if ((_metile_v18_r28) && (_metile_v18_r29) && (_metile_v18_r30) && (_metile_v18_r31) && (long(_off__metile_v19_r29) == long(_off__metile_v19_r28) + 1) && (long(_off__metile_v19_r30) == long(_off__metile_v19_r28) + 2) && (long(_off__metile_v19_r31) == long(_off__metile_v19_r28) + 3)) {\n _metile_vector_load_______ = float4(*reinterpret_cast(X + _off__metile_v19_r28));\n } else {\n _metile_vector_load_______[0] = _metile_v18_r28 ? X[_off__metile_v19_r28] : static_cast(0);\n _metile_vector_load_______[1] = _metile_v18_r29 ? X[_off__metile_v19_r29] : static_cast(0);\n _metile_vector_load_______[2] = _metile_v18_r30 ? X[_off__metile_v19_r30] : static_cast(0);\n _metile_vector_load_______[3] = _metile_v18_r31 ? X[_off__metile_v19_r31] : static_cast(0);\n }\n float _metile_v20_r28 = _metile_vector_load_______[0];\n float _metile_v20_r29 = _metile_vector_load_______[1];\n float _metile_v20_r30 = _metile_vector_load_______[2];\n float _metile_v20_r31 = _metile_vector_load_______[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v21_r4 = static_cast(_metile_v20_r4);\n float _metile_v21_r5 = static_cast(_metile_v20_r5);\n float _metile_v21_r6 = static_cast(_metile_v20_r6);\n float _metile_v21_r7 = static_cast(_metile_v20_r7);\n float _metile_v21_r8 = static_cast(_metile_v20_r8);\n float _metile_v21_r9 = static_cast(_metile_v20_r9);\n float _metile_v21_r10 = static_cast(_metile_v20_r10);\n float _metile_v21_r11 = static_cast(_metile_v20_r11);\n float _metile_v21_r12 = static_cast(_metile_v20_r12);\n float _metile_v21_r13 = static_cast(_metile_v20_r13);\n float _metile_v21_r14 = static_cast(_metile_v20_r14);\n float _metile_v21_r15 = static_cast(_metile_v20_r15);\n float _metile_v21_r16 = static_cast(_metile_v20_r16);\n float _metile_v21_r17 = static_cast(_metile_v20_r17);\n float _metile_v21_r18 = static_cast(_metile_v20_r18);\n float _metile_v21_r19 = static_cast(_metile_v20_r19);\n float _metile_v21_r20 = static_cast(_metile_v20_r20);\n float _metile_v21_r21 = static_cast(_metile_v20_r21);\n float _metile_v21_r22 = static_cast(_metile_v20_r22);\n float _metile_v21_r23 = static_cast(_metile_v20_r23);\n float _metile_v21_r24 = static_cast(_metile_v20_r24);\n float _metile_v21_r25 = static_cast(_metile_v20_r25);\n float _metile_v21_r26 = static_cast(_metile_v20_r26);\n float _metile_v21_r27 = static_cast(_metile_v20_r27);\n float _metile_v21_r28 = static_cast(_metile_v20_r28);\n float _metile_v21_r29 = static_cast(_metile_v20_r29);\n float _metile_v21_r30 = static_cast(_metile_v20_r30);\n float _metile_v21_r31 = static_cast(_metile_v20_r31);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_v22_r4 = _metile_v21_r4 * _metile_v21_r4;\n float _metile_v22_r5 = _metile_v21_r5 * _metile_v21_r5;\n float _metile_v22_r6 = _metile_v21_r6 * _metile_v21_r6;\n float _metile_v22_r7 = _metile_v21_r7 * _metile_v21_r7;\n float _metile_v22_r8 = _metile_v21_r8 * _metile_v21_r8;\n float _metile_v22_r9 = _metile_v21_r9 * _metile_v21_r9;\n float _metile_v22_r10 = _metile_v21_r10 * _metile_v21_r10;\n float _metile_v22_r11 = _metile_v21_r11 * _metile_v21_r11;\n float _metile_v22_r12 = _metile_v21_r12 * _metile_v21_r12;\n float _metile_v22_r13 = _metile_v21_r13 * _metile_v21_r13;\n float _metile_v22_r14 = _metile_v21_r14 * _metile_v21_r14;\n float _metile_v22_r15 = _metile_v21_r15 * _metile_v21_r15;\n float _metile_v22_r16 = _metile_v21_r16 * _metile_v21_r16;\n float _metile_v22_r17 = _metile_v21_r17 * _metile_v21_r17;\n float _metile_v22_r18 = _metile_v21_r18 * _metile_v21_r18;\n float _metile_v22_r19 = _metile_v21_r19 * _metile_v21_r19;\n float _metile_v22_r20 = _metile_v21_r20 * _metile_v21_r20;\n float _metile_v22_r21 = _metile_v21_r21 * _metile_v21_r21;\n float _metile_v22_r22 = _metile_v21_r22 * _metile_v21_r22;\n float _metile_v22_r23 = _metile_v21_r23 * _metile_v21_r23;\n float _metile_v22_r24 = _metile_v21_r24 * _metile_v21_r24;\n float _metile_v22_r25 = _metile_v21_r25 * _metile_v21_r25;\n float _metile_v22_r26 = _metile_v21_r26 * _metile_v21_r26;\n float _metile_v22_r27 = _metile_v21_r27 * _metile_v21_r27;\n float _metile_v22_r28 = _metile_v21_r28 * _metile_v21_r28;\n float _metile_v22_r29 = _metile_v21_r29 * _metile_v21_r29;\n float _metile_v22_r30 = _metile_v21_r30 * _metile_v21_r30;\n float _metile_v22_r31 = _metile_v21_r31 * _metile_v21_r31;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_v22_r4 + _metile_v22_r5;\n float _metile_register_sum___ = _metile_v22_r6 + _metile_v22_r7;\n float _metile_register_sum____ = _metile_v22_r8 + _metile_v22_r9;\n float _metile_register_sum_____ = _metile_v22_r10 + _metile_v22_r11;\n float _metile_register_sum______ = _metile_v22_r12 + _metile_v22_r13;\n float _metile_register_sum_______ = _metile_v22_r14 + _metile_v22_r15;\n float _metile_register_sum________ = _metile_v22_r16 + _metile_v22_r17;\n float _metile_register_sum_________ = _metile_v22_r18 + _metile_v22_r19;\n float _metile_register_sum__________ = _metile_v22_r20 + _metile_v22_r21;\n float _metile_register_sum___________ = _metile_v22_r22 + _metile_v22_r23;\n float _metile_register_sum____________ = _metile_v22_r24 + _metile_v22_r25;\n float _metile_register_sum_____________ = _metile_v22_r26 + _metile_v22_r27;\n float _metile_register_sum______________ = _metile_v22_r28 + _metile_v22_r29;\n float _metile_register_sum_______________ = _metile_v22_r30 + _metile_v22_r31;\n float _metile_register_sum________________ = _metile_register_sum + _metile_register_sum_;\n float _metile_register_sum_________________ = _metile_register_sum__ + _metile_register_sum___;\n float _metile_register_sum__________________ = _metile_register_sum____ + _metile_register_sum_____;\n float _metile_register_sum___________________ = _metile_register_sum______ + _metile_register_sum_______;\n float _metile_register_sum____________________ = _metile_register_sum________ + _metile_register_sum_________;\n float _metile_register_sum_____________________ = _metile_register_sum__________ + _metile_register_sum___________;\n float _metile_register_sum______________________ = _metile_register_sum____________ + _metile_register_sum_____________;\n float _metile_register_sum_______________________ = _metile_register_sum______________ + _metile_register_sum_______________;\n float _metile_register_sum________________________ = _metile_register_sum________________ + _metile_register_sum_________________;\n float _metile_register_sum_________________________ = _metile_register_sum__________________ + _metile_register_sum___________________;\n float _metile_register_sum__________________________ = _metile_register_sum____________________ + _metile_register_sum_____________________;\n float _metile_register_sum___________________________ = _metile_register_sum______________________ + _metile_register_sum_______________________;\n float _metile_register_sum____________________________ = _metile_register_sum________________________ + _metile_register_sum_________________________;\n float _metile_register_sum_____________________________ = _metile_register_sum__________________________ + _metile_register_sum___________________________;\n float _metile_register_sum______________________________ = _metile_register_sum____________________________ + _metile_register_sum_____________________________;\n float v23 = simd_sum(_metile_register_sum______________________________);\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v32_r4 = _metile_register_index____ >= 0;\n bool _metile_v32_r5 = _metile_register_index_____ >= 0;\n bool _metile_v32_r6 = _metile_register_index______ >= 0;\n bool _metile_v32_r7 = _metile_register_index_______ >= 0;\n bool _metile_v32_r8 = _metile_register_index________ >= 0;\n bool _metile_v32_r9 = _metile_register_index_________ >= 0;\n bool _metile_v32_r10 = _metile_register_index__________ >= 0;\n bool _metile_v32_r11 = _metile_register_index___________ >= 0;\n bool _metile_v32_r12 = _metile_register_index____________ >= 0;\n bool _metile_v32_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v32_r14 = _metile_register_index______________ >= 0;\n bool _metile_v32_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v32_r16 = _metile_register_index________________ >= 0;\n bool _metile_v32_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v32_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v32_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v32_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v32_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v32_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v32_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v32_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v32_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v32_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v32_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v32_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v32_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v32_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v32_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v33_r4 = _metile_register_index____ < 1024;\n bool _metile_v33_r5 = _metile_register_index_____ < 1024;\n bool _metile_v33_r6 = _metile_register_index______ < 1024;\n bool _metile_v33_r7 = _metile_register_index_______ < 1024;\n bool _metile_v33_r8 = _metile_register_index________ < 1024;\n bool _metile_v33_r9 = _metile_register_index_________ < 1024;\n bool _metile_v33_r10 = _metile_register_index__________ < 1024;\n bool _metile_v33_r11 = _metile_register_index___________ < 1024;\n bool _metile_v33_r12 = _metile_register_index____________ < 1024;\n bool _metile_v33_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v33_r14 = _metile_register_index______________ < 1024;\n bool _metile_v33_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v33_r16 = _metile_register_index________________ < 1024;\n bool _metile_v33_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v33_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v33_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v33_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v33_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v33_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v33_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v33_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v33_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v33_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v33_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v33_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v33_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v33_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v33_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n bool _metile_v34_r4 = _metile_v32_r4 & _metile_v33_r4;\n bool _metile_v34_r5 = _metile_v32_r5 & _metile_v33_r5;\n bool _metile_v34_r6 = _metile_v32_r6 & _metile_v33_r6;\n bool _metile_v34_r7 = _metile_v32_r7 & _metile_v33_r7;\n bool _metile_v34_r8 = _metile_v32_r8 & _metile_v33_r8;\n bool _metile_v34_r9 = _metile_v32_r9 & _metile_v33_r9;\n bool _metile_v34_r10 = _metile_v32_r10 & _metile_v33_r10;\n bool _metile_v34_r11 = _metile_v32_r11 & _metile_v33_r11;\n bool _metile_v34_r12 = _metile_v32_r12 & _metile_v33_r12;\n bool _metile_v34_r13 = _metile_v32_r13 & _metile_v33_r13;\n bool _metile_v34_r14 = _metile_v32_r14 & _metile_v33_r14;\n bool _metile_v34_r15 = _metile_v32_r15 & _metile_v33_r15;\n bool _metile_v34_r16 = _metile_v32_r16 & _metile_v33_r16;\n bool _metile_v34_r17 = _metile_v32_r17 & _metile_v33_r17;\n bool _metile_v34_r18 = _metile_v32_r18 & _metile_v33_r18;\n bool _metile_v34_r19 = _metile_v32_r19 & _metile_v33_r19;\n bool _metile_v34_r20 = _metile_v32_r20 & _metile_v33_r20;\n bool _metile_v34_r21 = _metile_v32_r21 & _metile_v33_r21;\n bool _metile_v34_r22 = _metile_v32_r22 & _metile_v33_r22;\n bool _metile_v34_r23 = _metile_v32_r23 & _metile_v33_r23;\n bool _metile_v34_r24 = _metile_v32_r24 & _metile_v33_r24;\n bool _metile_v34_r25 = _metile_v32_r25 & _metile_v33_r25;\n bool _metile_v34_r26 = _metile_v32_r26 & _metile_v33_r26;\n bool _metile_v34_r27 = _metile_v32_r27 & _metile_v33_r27;\n bool _metile_v34_r28 = _metile_v32_r28 & _metile_v33_r28;\n bool _metile_v34_r29 = _metile_v32_r29 & _metile_v33_r29;\n bool _metile_v34_r30 = _metile_v32_r30 & _metile_v33_r30;\n bool _metile_v34_r31 = _metile_v32_r31 & _metile_v33_r31;\n float4 _metile_vector_load________;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load________ = float4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load________[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load________[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load________[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load________[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n float _metile_v36_r0 = _metile_vector_load________[0];\n float _metile_v36_r1 = _metile_vector_load________[1];\n float _metile_v36_r2 = _metile_vector_load________[2];\n float _metile_v36_r3 = _metile_vector_load________[3];\n float4 _metile_vector_load_________;\n if ((_metile_v34_r4) && (_metile_v34_r5) && (_metile_v34_r6) && (_metile_v34_r7) && (long(_metile_register_index_____) == long(_metile_register_index____) + 1) && (long(_metile_register_index______) == long(_metile_register_index____) + 2) && (long(_metile_register_index_______) == long(_metile_register_index____) + 3)) {\n _metile_vector_load_________ = float4(*reinterpret_cast(W + _metile_register_index____));\n } else {\n _metile_vector_load_________[0] = _metile_v34_r4 ? W[_metile_register_index____] : static_cast(0);\n _metile_vector_load_________[1] = _metile_v34_r5 ? W[_metile_register_index_____] : static_cast(0);\n _metile_vector_load_________[2] = _metile_v34_r6 ? W[_metile_register_index______] : static_cast(0);\n _metile_vector_load_________[3] = _metile_v34_r7 ? W[_metile_register_index_______] : static_cast(0);\n }\n float _metile_v36_r4 = _metile_vector_load_________[0];\n float _metile_v36_r5 = _metile_vector_load_________[1];\n float _metile_v36_r6 = _metile_vector_load_________[2];\n float _metile_v36_r7 = _metile_vector_load_________[3];\n float4 _metile_vector_load__________;\n if ((_metile_v34_r8) && (_metile_v34_r9) && (_metile_v34_r10) && (_metile_v34_r11) && (long(_metile_register_index_________) == long(_metile_register_index________) + 1) && (long(_metile_register_index__________) == long(_metile_register_index________) + 2) && (long(_metile_register_index___________) == long(_metile_register_index________) + 3)) {\n _metile_vector_load__________ = float4(*reinterpret_cast(W + _metile_register_index________));\n } else {\n _metile_vector_load__________[0] = _metile_v34_r8 ? W[_metile_register_index________] : static_cast(0);\n _metile_vector_load__________[1] = _metile_v34_r9 ? W[_metile_register_index_________] : static_cast(0);\n _metile_vector_load__________[2] = _metile_v34_r10 ? W[_metile_register_index__________] : static_cast(0);\n _metile_vector_load__________[3] = _metile_v34_r11 ? W[_metile_register_index___________] : static_cast(0);\n }\n float _metile_v36_r8 = _metile_vector_load__________[0];\n float _metile_v36_r9 = _metile_vector_load__________[1];\n float _metile_v36_r10 = _metile_vector_load__________[2];\n float _metile_v36_r11 = _metile_vector_load__________[3];\n float4 _metile_vector_load___________;\n if ((_metile_v34_r12) && (_metile_v34_r13) && (_metile_v34_r14) && (_metile_v34_r15) && (long(_metile_register_index_____________) == long(_metile_register_index____________) + 1) && (long(_metile_register_index______________) == long(_metile_register_index____________) + 2) && (long(_metile_register_index_______________) == long(_metile_register_index____________) + 3)) {\n _metile_vector_load___________ = float4(*reinterpret_cast(W + _metile_register_index____________));\n } else {\n _metile_vector_load___________[0] = _metile_v34_r12 ? W[_metile_register_index____________] : static_cast(0);\n _metile_vector_load___________[1] = _metile_v34_r13 ? W[_metile_register_index_____________] : static_cast(0);\n _metile_vector_load___________[2] = _metile_v34_r14 ? W[_metile_register_index______________] : static_cast(0);\n _metile_vector_load___________[3] = _metile_v34_r15 ? W[_metile_register_index_______________] : static_cast(0);\n }\n float _metile_v36_r12 = _metile_vector_load___________[0];\n float _metile_v36_r13 = _metile_vector_load___________[1];\n float _metile_v36_r14 = _metile_vector_load___________[2];\n float _metile_v36_r15 = _metile_vector_load___________[3];\n float4 _metile_vector_load____________;\n if ((_metile_v34_r16) && (_metile_v34_r17) && (_metile_v34_r18) && (_metile_v34_r19) && (long(_metile_register_index_________________) == long(_metile_register_index________________) + 1) && (long(_metile_register_index__________________) == long(_metile_register_index________________) + 2) && (long(_metile_register_index___________________) == long(_metile_register_index________________) + 3)) {\n _metile_vector_load____________ = float4(*reinterpret_cast(W + _metile_register_index________________));\n } else {\n _metile_vector_load____________[0] = _metile_v34_r16 ? W[_metile_register_index________________] : static_cast(0);\n _metile_vector_load____________[1] = _metile_v34_r17 ? W[_metile_register_index_________________] : static_cast(0);\n _metile_vector_load____________[2] = _metile_v34_r18 ? W[_metile_register_index__________________] : static_cast(0);\n _metile_vector_load____________[3] = _metile_v34_r19 ? W[_metile_register_index___________________] : static_cast(0);\n }\n float _metile_v36_r16 = _metile_vector_load____________[0];\n float _metile_v36_r17 = _metile_vector_load____________[1];\n float _metile_v36_r18 = _metile_vector_load____________[2];\n float _metile_v36_r19 = _metile_vector_load____________[3];\n float4 _metile_vector_load_____________;\n if ((_metile_v34_r20) && (_metile_v34_r21) && (_metile_v34_r22) && (_metile_v34_r23) && (long(_metile_register_index_____________________) == long(_metile_register_index____________________) + 1) && (long(_metile_register_index______________________) == long(_metile_register_index____________________) + 2) && (long(_metile_register_index_______________________) == long(_metile_register_index____________________) + 3)) {\n _metile_vector_load_____________ = float4(*reinterpret_cast(W + _metile_register_index____________________));\n } else {\n _metile_vector_load_____________[0] = _metile_v34_r20 ? W[_metile_register_index____________________] : static_cast(0);\n _metile_vector_load_____________[1] = _metile_v34_r21 ? W[_metile_register_index_____________________] : static_cast(0);\n _metile_vector_load_____________[2] = _metile_v34_r22 ? W[_metile_register_index______________________] : static_cast(0);\n _metile_vector_load_____________[3] = _metile_v34_r23 ? W[_metile_register_index_______________________] : static_cast(0);\n }\n float _metile_v36_r20 = _metile_vector_load_____________[0];\n float _metile_v36_r21 = _metile_vector_load_____________[1];\n float _metile_v36_r22 = _metile_vector_load_____________[2];\n float _metile_v36_r23 = _metile_vector_load_____________[3];\n float4 _metile_vector_load______________;\n if ((_metile_v34_r24) && (_metile_v34_r25) && (_metile_v34_r26) && (_metile_v34_r27) && (long(_metile_register_index_________________________) == long(_metile_register_index________________________) + 1) && (long(_metile_register_index__________________________) == long(_metile_register_index________________________) + 2) && (long(_metile_register_index___________________________) == long(_metile_register_index________________________) + 3)) {\n _metile_vector_load______________ = float4(*reinterpret_cast(W + _metile_register_index________________________));\n } else {\n _metile_vector_load______________[0] = _metile_v34_r24 ? W[_metile_register_index________________________] : static_cast(0);\n _metile_vector_load______________[1] = _metile_v34_r25 ? W[_metile_register_index_________________________] : static_cast(0);\n _metile_vector_load______________[2] = _metile_v34_r26 ? W[_metile_register_index__________________________] : static_cast(0);\n _metile_vector_load______________[3] = _metile_v34_r27 ? W[_metile_register_index___________________________] : static_cast(0);\n }\n float _metile_v36_r24 = _metile_vector_load______________[0];\n float _metile_v36_r25 = _metile_vector_load______________[1];\n float _metile_v36_r26 = _metile_vector_load______________[2];\n float _metile_v36_r27 = _metile_vector_load______________[3];\n float4 _metile_vector_load_______________;\n if ((_metile_v34_r28) && (_metile_v34_r29) && (_metile_v34_r30) && (_metile_v34_r31) && (long(_metile_register_index_____________________________) == long(_metile_register_index____________________________) + 1) && (long(_metile_register_index______________________________) == long(_metile_register_index____________________________) + 2) && (long(_metile_register_index_______________________________) == long(_metile_register_index____________________________) + 3)) {\n _metile_vector_load_______________ = float4(*reinterpret_cast(W + _metile_register_index____________________________));\n } else {\n _metile_vector_load_______________[0] = _metile_v34_r28 ? W[_metile_register_index____________________________] : static_cast(0);\n _metile_vector_load_______________[1] = _metile_v34_r29 ? W[_metile_register_index_____________________________] : static_cast(0);\n _metile_vector_load_______________[2] = _metile_v34_r30 ? W[_metile_register_index______________________________] : static_cast(0);\n _metile_vector_load_______________[3] = _metile_v34_r31 ? W[_metile_register_index_______________________________] : static_cast(0);\n }\n float _metile_v36_r28 = _metile_vector_load_______________[0];\n float _metile_v36_r29 = _metile_vector_load_______________[1];\n float _metile_v36_r30 = _metile_vector_load_______________[2];\n float _metile_v36_r31 = _metile_vector_load_______________[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v37_r4 = static_cast(_metile_v36_r4);\n float _metile_v37_r5 = static_cast(_metile_v36_r5);\n float _metile_v37_r6 = static_cast(_metile_v36_r6);\n float _metile_v37_r7 = static_cast(_metile_v36_r7);\n float _metile_v37_r8 = static_cast(_metile_v36_r8);\n float _metile_v37_r9 = static_cast(_metile_v36_r9);\n float _metile_v37_r10 = static_cast(_metile_v36_r10);\n float _metile_v37_r11 = static_cast(_metile_v36_r11);\n float _metile_v37_r12 = static_cast(_metile_v36_r12);\n float _metile_v37_r13 = static_cast(_metile_v36_r13);\n float _metile_v37_r14 = static_cast(_metile_v36_r14);\n float _metile_v37_r15 = static_cast(_metile_v36_r15);\n float _metile_v37_r16 = static_cast(_metile_v36_r16);\n float _metile_v37_r17 = static_cast(_metile_v36_r17);\n float _metile_v37_r18 = static_cast(_metile_v36_r18);\n float _metile_v37_r19 = static_cast(_metile_v36_r19);\n float _metile_v37_r20 = static_cast(_metile_v36_r20);\n float _metile_v37_r21 = static_cast(_metile_v36_r21);\n float _metile_v37_r22 = static_cast(_metile_v36_r22);\n float _metile_v37_r23 = static_cast(_metile_v36_r23);\n float _metile_v37_r24 = static_cast(_metile_v36_r24);\n float _metile_v37_r25 = static_cast(_metile_v36_r25);\n float _metile_v37_r26 = static_cast(_metile_v36_r26);\n float _metile_v37_r27 = static_cast(_metile_v36_r27);\n float _metile_v37_r28 = static_cast(_metile_v36_r28);\n float _metile_v37_r29 = static_cast(_metile_v36_r29);\n float _metile_v37_r30 = static_cast(_metile_v36_r30);\n float _metile_v37_r31 = static_cast(_metile_v36_r31);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v38_r4 = _metile_v21_r4 * v29;\n float _metile_v38_r5 = _metile_v21_r5 * v29;\n float _metile_v38_r6 = _metile_v21_r6 * v29;\n float _metile_v38_r7 = _metile_v21_r7 * v29;\n float _metile_v38_r8 = _metile_v21_r8 * v29;\n float _metile_v38_r9 = _metile_v21_r9 * v29;\n float _metile_v38_r10 = _metile_v21_r10 * v29;\n float _metile_v38_r11 = _metile_v21_r11 * v29;\n float _metile_v38_r12 = _metile_v21_r12 * v29;\n float _metile_v38_r13 = _metile_v21_r13 * v29;\n float _metile_v38_r14 = _metile_v21_r14 * v29;\n float _metile_v38_r15 = _metile_v21_r15 * v29;\n float _metile_v38_r16 = _metile_v21_r16 * v29;\n float _metile_v38_r17 = _metile_v21_r17 * v29;\n float _metile_v38_r18 = _metile_v21_r18 * v29;\n float _metile_v38_r19 = _metile_v21_r19 * v29;\n float _metile_v38_r20 = _metile_v21_r20 * v29;\n float _metile_v38_r21 = _metile_v21_r21 * v29;\n float _metile_v38_r22 = _metile_v21_r22 * v29;\n float _metile_v38_r23 = _metile_v21_r23 * v29;\n float _metile_v38_r24 = _metile_v21_r24 * v29;\n float _metile_v38_r25 = _metile_v21_r25 * v29;\n float _metile_v38_r26 = _metile_v21_r26 * v29;\n float _metile_v38_r27 = _metile_v21_r27 * v29;\n float _metile_v38_r28 = _metile_v21_r28 * v29;\n float _metile_v38_r29 = _metile_v21_r29 * v29;\n float _metile_v38_r30 = _metile_v21_r30 * v29;\n float _metile_v38_r31 = _metile_v21_r31 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n float _metile_v39_r4 = _metile_v38_r4 * _metile_v37_r4;\n float _metile_v39_r5 = _metile_v38_r5 * _metile_v37_r5;\n float _metile_v39_r6 = _metile_v38_r6 * _metile_v37_r6;\n float _metile_v39_r7 = _metile_v38_r7 * _metile_v37_r7;\n float _metile_v39_r8 = _metile_v38_r8 * _metile_v37_r8;\n float _metile_v39_r9 = _metile_v38_r9 * _metile_v37_r9;\n float _metile_v39_r10 = _metile_v38_r10 * _metile_v37_r10;\n float _metile_v39_r11 = _metile_v38_r11 * _metile_v37_r11;\n float _metile_v39_r12 = _metile_v38_r12 * _metile_v37_r12;\n float _metile_v39_r13 = _metile_v38_r13 * _metile_v37_r13;\n float _metile_v39_r14 = _metile_v38_r14 * _metile_v37_r14;\n float _metile_v39_r15 = _metile_v38_r15 * _metile_v37_r15;\n float _metile_v39_r16 = _metile_v38_r16 * _metile_v37_r16;\n float _metile_v39_r17 = _metile_v38_r17 * _metile_v37_r17;\n float _metile_v39_r18 = _metile_v38_r18 * _metile_v37_r18;\n float _metile_v39_r19 = _metile_v38_r19 * _metile_v37_r19;\n float _metile_v39_r20 = _metile_v38_r20 * _metile_v37_r20;\n float _metile_v39_r21 = _metile_v38_r21 * _metile_v37_r21;\n float _metile_v39_r22 = _metile_v38_r22 * _metile_v37_r22;\n float _metile_v39_r23 = _metile_v38_r23 * _metile_v37_r23;\n float _metile_v39_r24 = _metile_v38_r24 * _metile_v37_r24;\n float _metile_v39_r25 = _metile_v38_r25 * _metile_v37_r25;\n float _metile_v39_r26 = _metile_v38_r26 * _metile_v37_r26;\n float _metile_v39_r27 = _metile_v38_r27 * _metile_v37_r27;\n float _metile_v39_r28 = _metile_v38_r28 * _metile_v37_r28;\n float _metile_v39_r29 = _metile_v38_r29 * _metile_v37_r29;\n float _metile_v39_r30 = _metile_v38_r30 * _metile_v37_r30;\n float _metile_v39_r31 = _metile_v38_r31 * _metile_v37_r31;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v41_r4 = _metile_register_index____ >= 0;\n bool _metile_v41_r5 = _metile_register_index_____ >= 0;\n bool _metile_v41_r6 = _metile_register_index______ >= 0;\n bool _metile_v41_r7 = _metile_register_index_______ >= 0;\n bool _metile_v41_r8 = _metile_register_index________ >= 0;\n bool _metile_v41_r9 = _metile_register_index_________ >= 0;\n bool _metile_v41_r10 = _metile_register_index__________ >= 0;\n bool _metile_v41_r11 = _metile_register_index___________ >= 0;\n bool _metile_v41_r12 = _metile_register_index____________ >= 0;\n bool _metile_v41_r13 = _metile_register_index_____________ >= 0;\n bool _metile_v41_r14 = _metile_register_index______________ >= 0;\n bool _metile_v41_r15 = _metile_register_index_______________ >= 0;\n bool _metile_v41_r16 = _metile_register_index________________ >= 0;\n bool _metile_v41_r17 = _metile_register_index_________________ >= 0;\n bool _metile_v41_r18 = _metile_register_index__________________ >= 0;\n bool _metile_v41_r19 = _metile_register_index___________________ >= 0;\n bool _metile_v41_r20 = _metile_register_index____________________ >= 0;\n bool _metile_v41_r21 = _metile_register_index_____________________ >= 0;\n bool _metile_v41_r22 = _metile_register_index______________________ >= 0;\n bool _metile_v41_r23 = _metile_register_index_______________________ >= 0;\n bool _metile_v41_r24 = _metile_register_index________________________ >= 0;\n bool _metile_v41_r25 = _metile_register_index_________________________ >= 0;\n bool _metile_v41_r26 = _metile_register_index__________________________ >= 0;\n bool _metile_v41_r27 = _metile_register_index___________________________ >= 0;\n bool _metile_v41_r28 = _metile_register_index____________________________ >= 0;\n bool _metile_v41_r29 = _metile_register_index_____________________________ >= 0;\n bool _metile_v41_r30 = _metile_register_index______________________________ >= 0;\n bool _metile_v41_r31 = _metile_register_index_______________________________ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v42_r4 = _metile_register_index____ < 1024;\n bool _metile_v42_r5 = _metile_register_index_____ < 1024;\n bool _metile_v42_r6 = _metile_register_index______ < 1024;\n bool _metile_v42_r7 = _metile_register_index_______ < 1024;\n bool _metile_v42_r8 = _metile_register_index________ < 1024;\n bool _metile_v42_r9 = _metile_register_index_________ < 1024;\n bool _metile_v42_r10 = _metile_register_index__________ < 1024;\n bool _metile_v42_r11 = _metile_register_index___________ < 1024;\n bool _metile_v42_r12 = _metile_register_index____________ < 1024;\n bool _metile_v42_r13 = _metile_register_index_____________ < 1024;\n bool _metile_v42_r14 = _metile_register_index______________ < 1024;\n bool _metile_v42_r15 = _metile_register_index_______________ < 1024;\n bool _metile_v42_r16 = _metile_register_index________________ < 1024;\n bool _metile_v42_r17 = _metile_register_index_________________ < 1024;\n bool _metile_v42_r18 = _metile_register_index__________________ < 1024;\n bool _metile_v42_r19 = _metile_register_index___________________ < 1024;\n bool _metile_v42_r20 = _metile_register_index____________________ < 1024;\n bool _metile_v42_r21 = _metile_register_index_____________________ < 1024;\n bool _metile_v42_r22 = _metile_register_index______________________ < 1024;\n bool _metile_v42_r23 = _metile_register_index_______________________ < 1024;\n bool _metile_v42_r24 = _metile_register_index________________________ < 1024;\n bool _metile_v42_r25 = _metile_register_index_________________________ < 1024;\n bool _metile_v42_r26 = _metile_register_index__________________________ < 1024;\n bool _metile_v42_r27 = _metile_register_index___________________________ < 1024;\n bool _metile_v42_r28 = _metile_register_index____________________________ < 1024;\n bool _metile_v42_r29 = _metile_register_index_____________________________ < 1024;\n bool _metile_v42_r30 = _metile_register_index______________________________ < 1024;\n bool _metile_v42_r31 = _metile_register_index_______________________________ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n bool _metile_v43_r4 = _metile_v41_r4 & _metile_v42_r4;\n bool _metile_v43_r5 = _metile_v41_r5 & _metile_v42_r5;\n bool _metile_v43_r6 = _metile_v41_r6 & _metile_v42_r6;\n bool _metile_v43_r7 = _metile_v41_r7 & _metile_v42_r7;\n bool _metile_v43_r8 = _metile_v41_r8 & _metile_v42_r8;\n bool _metile_v43_r9 = _metile_v41_r9 & _metile_v42_r9;\n bool _metile_v43_r10 = _metile_v41_r10 & _metile_v42_r10;\n bool _metile_v43_r11 = _metile_v41_r11 & _metile_v42_r11;\n bool _metile_v43_r12 = _metile_v41_r12 & _metile_v42_r12;\n bool _metile_v43_r13 = _metile_v41_r13 & _metile_v42_r13;\n bool _metile_v43_r14 = _metile_v41_r14 & _metile_v42_r14;\n bool _metile_v43_r15 = _metile_v41_r15 & _metile_v42_r15;\n bool _metile_v43_r16 = _metile_v41_r16 & _metile_v42_r16;\n bool _metile_v43_r17 = _metile_v41_r17 & _metile_v42_r17;\n bool _metile_v43_r18 = _metile_v41_r18 & _metile_v42_r18;\n bool _metile_v43_r19 = _metile_v41_r19 & _metile_v42_r19;\n bool _metile_v43_r20 = _metile_v41_r20 & _metile_v42_r20;\n bool _metile_v43_r21 = _metile_v41_r21 & _metile_v42_r21;\n bool _metile_v43_r22 = _metile_v41_r22 & _metile_v42_r22;\n bool _metile_v43_r23 = _metile_v41_r23 & _metile_v42_r23;\n bool _metile_v43_r24 = _metile_v41_r24 & _metile_v42_r24;\n bool _metile_v43_r25 = _metile_v41_r25 & _metile_v42_r25;\n bool _metile_v43_r26 = _metile_v41_r26 & _metile_v42_r26;\n bool _metile_v43_r27 = _metile_v41_r27 & _metile_v42_r27;\n bool _metile_v43_r28 = _metile_v41_r28 & _metile_v42_r28;\n bool _metile_v43_r29 = _metile_v41_r29 & _metile_v42_r29;\n bool _metile_v43_r30 = _metile_v41_r30 & _metile_v42_r30;\n bool _metile_v43_r31 = _metile_v41_r31 & _metile_v42_r31;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n int _off__metile_v44_r4 = v9 + _metile_register_index____;\n int _off__metile_v44_r5 = v9 + _metile_register_index_____;\n int _off__metile_v44_r6 = v9 + _metile_register_index______;\n int _off__metile_v44_r7 = v9 + _metile_register_index_______;\n int _off__metile_v44_r8 = v9 + _metile_register_index________;\n int _off__metile_v44_r9 = v9 + _metile_register_index_________;\n int _off__metile_v44_r10 = v9 + _metile_register_index__________;\n int _off__metile_v44_r11 = v9 + _metile_register_index___________;\n int _off__metile_v44_r12 = v9 + _metile_register_index____________;\n int _off__metile_v44_r13 = v9 + _metile_register_index_____________;\n int _off__metile_v44_r14 = v9 + _metile_register_index______________;\n int _off__metile_v44_r15 = v9 + _metile_register_index_______________;\n int _off__metile_v44_r16 = v9 + _metile_register_index________________;\n int _off__metile_v44_r17 = v9 + _metile_register_index_________________;\n int _off__metile_v44_r18 = v9 + _metile_register_index__________________;\n int _off__metile_v44_r19 = v9 + _metile_register_index___________________;\n int _off__metile_v44_r20 = v9 + _metile_register_index____________________;\n int _off__metile_v44_r21 = v9 + _metile_register_index_____________________;\n int _off__metile_v44_r22 = v9 + _metile_register_index______________________;\n int _off__metile_v44_r23 = v9 + _metile_register_index_______________________;\n int _off__metile_v44_r24 = v9 + _metile_register_index________________________;\n int _off__metile_v44_r25 = v9 + _metile_register_index_________________________;\n int _off__metile_v44_r26 = v9 + _metile_register_index__________________________;\n int _off__metile_v44_r27 = v9 + _metile_register_index___________________________;\n int _off__metile_v44_r28 = v9 + _metile_register_index____________________________;\n int _off__metile_v44_r29 = v9 + _metile_register_index_____________________________;\n int _off__metile_v44_r30 = v9 + _metile_register_index______________________________;\n int _off__metile_v44_r31 = v9 + _metile_register_index_______________________________;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_float4(float4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n if ((_metile_v43_r4) && (_metile_v43_r5) && (_metile_v43_r6) && (_metile_v43_r7) && (long(_off__metile_v44_r5) == long(_off__metile_v44_r4) + 1) && (long(_off__metile_v44_r6) == long(_off__metile_v44_r4) + 2) && (long(_off__metile_v44_r7) == long(_off__metile_v44_r4) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r4) = packed_float4(float4(static_cast(_metile_v39_r4), static_cast(_metile_v39_r5), static_cast(_metile_v39_r6), static_cast(_metile_v39_r7)));\n } else {\n if (_metile_v43_r4) { Out[_off__metile_v44_r4] = static_cast(_metile_v39_r4); }\n if (_metile_v43_r5) { Out[_off__metile_v44_r5] = static_cast(_metile_v39_r5); }\n if (_metile_v43_r6) { Out[_off__metile_v44_r6] = static_cast(_metile_v39_r6); }\n if (_metile_v43_r7) { Out[_off__metile_v44_r7] = static_cast(_metile_v39_r7); }\n }\n if ((_metile_v43_r8) && (_metile_v43_r9) && (_metile_v43_r10) && (_metile_v43_r11) && (long(_off__metile_v44_r9) == long(_off__metile_v44_r8) + 1) && (long(_off__metile_v44_r10) == long(_off__metile_v44_r8) + 2) && (long(_off__metile_v44_r11) == long(_off__metile_v44_r8) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r8) = packed_float4(float4(static_cast(_metile_v39_r8), static_cast(_metile_v39_r9), static_cast(_metile_v39_r10), static_cast(_metile_v39_r11)));\n } else {\n if (_metile_v43_r8) { Out[_off__metile_v44_r8] = static_cast(_metile_v39_r8); }\n if (_metile_v43_r9) { Out[_off__metile_v44_r9] = static_cast(_metile_v39_r9); }\n if (_metile_v43_r10) { Out[_off__metile_v44_r10] = static_cast(_metile_v39_r10); }\n if (_metile_v43_r11) { Out[_off__metile_v44_r11] = static_cast(_metile_v39_r11); }\n }\n if ((_metile_v43_r12) && (_metile_v43_r13) && (_metile_v43_r14) && (_metile_v43_r15) && (long(_off__metile_v44_r13) == long(_off__metile_v44_r12) + 1) && (long(_off__metile_v44_r14) == long(_off__metile_v44_r12) + 2) && (long(_off__metile_v44_r15) == long(_off__metile_v44_r12) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r12) = packed_float4(float4(static_cast(_metile_v39_r12), static_cast(_metile_v39_r13), static_cast(_metile_v39_r14), static_cast(_metile_v39_r15)));\n } else {\n if (_metile_v43_r12) { Out[_off__metile_v44_r12] = static_cast(_metile_v39_r12); }\n if (_metile_v43_r13) { Out[_off__metile_v44_r13] = static_cast(_metile_v39_r13); }\n if (_metile_v43_r14) { Out[_off__metile_v44_r14] = static_cast(_metile_v39_r14); }\n if (_metile_v43_r15) { Out[_off__metile_v44_r15] = static_cast(_metile_v39_r15); }\n }\n if ((_metile_v43_r16) && (_metile_v43_r17) && (_metile_v43_r18) && (_metile_v43_r19) && (long(_off__metile_v44_r17) == long(_off__metile_v44_r16) + 1) && (long(_off__metile_v44_r18) == long(_off__metile_v44_r16) + 2) && (long(_off__metile_v44_r19) == long(_off__metile_v44_r16) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r16) = packed_float4(float4(static_cast(_metile_v39_r16), static_cast(_metile_v39_r17), static_cast(_metile_v39_r18), static_cast(_metile_v39_r19)));\n } else {\n if (_metile_v43_r16) { Out[_off__metile_v44_r16] = static_cast(_metile_v39_r16); }\n if (_metile_v43_r17) { Out[_off__metile_v44_r17] = static_cast(_metile_v39_r17); }\n if (_metile_v43_r18) { Out[_off__metile_v44_r18] = static_cast(_metile_v39_r18); }\n if (_metile_v43_r19) { Out[_off__metile_v44_r19] = static_cast(_metile_v39_r19); }\n }\n if ((_metile_v43_r20) && (_metile_v43_r21) && (_metile_v43_r22) && (_metile_v43_r23) && (long(_off__metile_v44_r21) == long(_off__metile_v44_r20) + 1) && (long(_off__metile_v44_r22) == long(_off__metile_v44_r20) + 2) && (long(_off__metile_v44_r23) == long(_off__metile_v44_r20) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r20) = packed_float4(float4(static_cast(_metile_v39_r20), static_cast(_metile_v39_r21), static_cast(_metile_v39_r22), static_cast(_metile_v39_r23)));\n } else {\n if (_metile_v43_r20) { Out[_off__metile_v44_r20] = static_cast(_metile_v39_r20); }\n if (_metile_v43_r21) { Out[_off__metile_v44_r21] = static_cast(_metile_v39_r21); }\n if (_metile_v43_r22) { Out[_off__metile_v44_r22] = static_cast(_metile_v39_r22); }\n if (_metile_v43_r23) { Out[_off__metile_v44_r23] = static_cast(_metile_v39_r23); }\n }\n if ((_metile_v43_r24) && (_metile_v43_r25) && (_metile_v43_r26) && (_metile_v43_r27) && (long(_off__metile_v44_r25) == long(_off__metile_v44_r24) + 1) && (long(_off__metile_v44_r26) == long(_off__metile_v44_r24) + 2) && (long(_off__metile_v44_r27) == long(_off__metile_v44_r24) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r24) = packed_float4(float4(static_cast(_metile_v39_r24), static_cast(_metile_v39_r25), static_cast(_metile_v39_r26), static_cast(_metile_v39_r27)));\n } else {\n if (_metile_v43_r24) { Out[_off__metile_v44_r24] = static_cast(_metile_v39_r24); }\n if (_metile_v43_r25) { Out[_off__metile_v44_r25] = static_cast(_metile_v39_r25); }\n if (_metile_v43_r26) { Out[_off__metile_v44_r26] = static_cast(_metile_v39_r26); }\n if (_metile_v43_r27) { Out[_off__metile_v44_r27] = static_cast(_metile_v39_r27); }\n }\n if ((_metile_v43_r28) && (_metile_v43_r29) && (_metile_v43_r30) && (_metile_v43_r31) && (long(_off__metile_v44_r29) == long(_off__metile_v44_r28) + 1) && (long(_off__metile_v44_r30) == long(_off__metile_v44_r28) + 2) && (long(_off__metile_v44_r31) == long(_off__metile_v44_r28) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r28) = packed_float4(float4(static_cast(_metile_v39_r28), static_cast(_metile_v39_r29), static_cast(_metile_v39_r30), static_cast(_metile_v39_r31)));\n } else {\n if (_metile_v43_r28) { Out[_off__metile_v44_r28] = static_cast(_metile_v39_r28); }\n if (_metile_v43_r29) { Out[_off__metile_v44_r29] = static_cast(_metile_v39_r29); }\n if (_metile_v43_r30) { Out[_off__metile_v44_r30] = static_cast(_metile_v39_r30); }\n if (_metile_v43_r31) { Out[_off__metile_v44_r31] = static_cast(_metile_v39_r31); }\n }\n}", "source_sha256": "c8101f914e715ded38108b0b5ca87ac0fdc945815a7e8480038b36c36f05e689", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 32, 1, 1 ], "is_gemm": false, "prefer_ordered": false, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 32, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "device", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 32 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [], "double_buffered": false, "vectorized_loads": 16, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 5, 6, 0, 1, 2, 3, 4, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 32 }, "elements_per_thread": 32 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 32, "threads": 32, "scratch": null, "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 16, "grouped_stores": 8 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 534, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 220.89600000000002, "control": 219.417, "speedup": 0.993304541503694 }, "gpu_us": { "candidate": 9.375042282044888, "control": 8.124974556267262, "speedup": 0.8666600439582273 } } }, { "frozen_register4": { "pairs": 568, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 220.0, "control": 218.41649999999998, "speedup": 0.9928022727272726 }, "gpu_us": { "candidate": 9.374984074383974, "control": 8.124974556267262, "speedup": 0.8666654249011244 } } }, { "frozen_register4": { "pairs": 551, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 221.125, "control": 219.291, "speedup": 0.9917060486150368 }, "gpu_us": { "candidate": 9.375042282044888, "control": 8.124974556267262, "speedup": 0.8666600439582273 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.992604063182471, "round_speedups": [ 0.993304541503694, 0.9928022727272726, 0.9917060486150368 ], "candidate": 220.67313226137605, "control": 219.04104771784438 }, "gpu_us": { "speedup": 0.8666618376021475, "round_speedups": [ 0.8666600439582273, 0.8666654249011244, 0.8666600439582273 ], "candidate": 9.375022879451095, "control": 8.124974556267262 } } } }, { "name": "float32_256x1024", "dtype": "float32", "batches": 256, "width": 1024, "status": "measured", "variant": { "name": "register2_striped", "elements_per_thread": 2, "layout": "striped" }, "input_sha256": "d91bbc8e56d1e705bcdef1e433ae3b5ce1d9e73a225cd6afc919bf59342546a9", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 511;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 512;\n int _metile_register_index_ = int(_metile_register_packed_);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n threadgroup float _metile_register_reduction[16];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 16u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n}", "source_sha256": "80a3b58c42ac34374f90c87b95d6214a45947a8245bd291ea088e84eea10acdd", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 512, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 512, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 2 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 16, "bytes": 64 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 2 }, "elements_per_thread": 2 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 2, "threads": 512, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 576, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 217.1045, "control": 216.542, "speedup": 0.9974090818016209 }, "gpu_us": { "candidate": 7.874972652643919, "control": 8.04167939350009, "speedup": 1.0211691834637928 } } }, { "frozen_register4": { "pairs": 579, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 215.916, "control": 215.625, "speedup": 0.9986522536541989 }, "gpu_us": { "candidate": 7.874972652643919, "control": 8.083356078714132, "speedup": 1.026461479329741 } } }, { "frozen_register4": { "pairs": 577, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 217.541, "control": 216.042, "speedup": 0.9931093449050984 }, "gpu_us": { "candidate": 7.874972652643919, "control": 8.083297871053219, "speedup": 1.0264540878550679 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9963873941881518, "round_speedups": [ 0.9974090818016209, 0.9986522536541989, 0.9931093449050984 ], "candidate": 216.85274499645857, "control": 216.06934150956891 }, "gpu_us": { "speedup": 1.0246918805868663, "round_speedups": [ 1.0211691834637928, 1.026461479329741, 1.0264540878550679 ], "candidate": 7.874972652643919, "control": 8.06942053700784 } } } }, { "name": "float32_256x1024", "dtype": "float32", "batches": 256, "width": 1024, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "d91bbc8e56d1e705bcdef1e433ae3b5ce1d9e73a225cd6afc919bf59342546a9", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "26dcd97c409e667a170eb1ec796096fa645431253522d88e56e53edb0819b727", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 576, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 215.208, "control": 214.937, "speedup": 0.9987407531318538 }, "gpu_us": { "candidate": 7.9999445006251335, "control": 8.04167939350009, "speedup": 1.0052168978011904 } } }, { "frozen_register4": { "pairs": 581, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 214.417, "control": 215.459, "speedup": 1.004859689297024 }, "gpu_us": { "candidate": 7.958326023072004, "control": 8.04167939350009, "speedup": 1.0104737315594303 } } }, { "frozen_register4": { "pairs": 562, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 213.20850000000002, "control": 214.5625, "speedup": 1.0063505910880663 }, "gpu_us": { "candidate": 8.000002708286047, "control": 8.083297871053219, "speedup": 1.010411891821099 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0033116012060928, "round_speedups": [ 0.9987407531318538, 1.004859689297024, 1.0063505910880663 ], "candidate": 214.2762548856377, "control": 214.98585238975392 }, "gpu_us": { "speedup": 1.0086978283172867, "round_speedups": [ 1.0052168978011904, 1.0104737315594303, 1.010411891821099 ], "candidate": 7.986066916725293, "control": 8.055528355697334 } } } }, { "name": "float32_256x1024", "dtype": "float32", "batches": 256, "width": 1024, "status": "measured", "variant": { "name": "register4_blocked4", "elements_per_thread": 4, "layout": "blocked4" }, "input_sha256": "d91bbc8e56d1e705bcdef1e433ae3b5ce1d9e73a225cd6afc919bf59342546a9", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int((((_metile_bounded_thread >> 8) & 1u) << 0) | (((_metile_bounded_thread >> 9) & 1u) << 1) | (((_metile_bounded_thread >> 0) & 1u) << 2) | (((_metile_bounded_thread >> 1) & 1u) << 3) | (((_metile_bounded_thread >> 2) & 1u) << 4) | (((_metile_bounded_thread >> 3) & 1u) << 5) | (((_metile_bounded_thread >> 4) & 1u) << 6) | (((_metile_bounded_thread >> 5) & 1u) << 7) | (((_metile_bounded_thread >> 6) & 1u) << 8) | (((_metile_bounded_thread >> 7) & 1u) << 9));\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int((((_metile_register_packed_ >> 8) & 1u) << 0) | (((_metile_register_packed_ >> 9) & 1u) << 1) | (((_metile_register_packed_ >> 0) & 1u) << 2) | (((_metile_register_packed_ >> 1) & 1u) << 3) | (((_metile_register_packed_ >> 2) & 1u) << 4) | (((_metile_register_packed_ >> 3) & 1u) << 5) | (((_metile_register_packed_ >> 4) & 1u) << 6) | (((_metile_register_packed_ >> 5) & 1u) << 7) | (((_metile_register_packed_ >> 6) & 1u) << 8) | (((_metile_register_packed_ >> 7) & 1u) << 9));\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int((((_metile_register_packed__ >> 8) & 1u) << 0) | (((_metile_register_packed__ >> 9) & 1u) << 1) | (((_metile_register_packed__ >> 0) & 1u) << 2) | (((_metile_register_packed__ >> 1) & 1u) << 3) | (((_metile_register_packed__ >> 2) & 1u) << 4) | (((_metile_register_packed__ >> 3) & 1u) << 5) | (((_metile_register_packed__ >> 4) & 1u) << 6) | (((_metile_register_packed__ >> 5) & 1u) << 7) | (((_metile_register_packed__ >> 6) & 1u) << 8) | (((_metile_register_packed__ >> 7) & 1u) << 9));\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int((((_metile_register_packed___ >> 8) & 1u) << 0) | (((_metile_register_packed___ >> 9) & 1u) << 1) | (((_metile_register_packed___ >> 0) & 1u) << 2) | (((_metile_register_packed___ >> 1) & 1u) << 3) | (((_metile_register_packed___ >> 2) & 1u) << 4) | (((_metile_register_packed___ >> 3) & 1u) << 5) | (((_metile_register_packed___ >> 4) & 1u) << 6) | (((_metile_register_packed___ >> 5) & 1u) << 7) | (((_metile_register_packed___ >> 6) & 1u) << 8) | (((_metile_register_packed___ >> 7) & 1u) << 9));\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float4 _metile_vector_load;\n if ((_metile_v18_r0) && (_metile_v18_r1) && (_metile_v18_r2) && (_metile_v18_r3) && (long(_off__metile_v19_r1) == long(_off__metile_v19_r0) + 1) && (long(_off__metile_v19_r2) == long(_off__metile_v19_r0) + 2) && (long(_off__metile_v19_r3) == long(_off__metile_v19_r0) + 3)) {\n _metile_vector_load = float4(*reinterpret_cast(X + _off__metile_v19_r0));\n } else {\n _metile_vector_load[0] = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n _metile_vector_load[1] = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n _metile_vector_load[2] = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n _metile_vector_load[3] = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n }\n float _metile_v20_r0 = _metile_vector_load[0];\n float _metile_v20_r1 = _metile_vector_load[1];\n float _metile_v20_r2 = _metile_vector_load[2];\n float _metile_v20_r3 = _metile_vector_load[3];\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float4 _metile_vector_load_;\n if ((_metile_v34_r0) && (_metile_v34_r1) && (_metile_v34_r2) && (_metile_v34_r3) && (long(_metile_register_index_) == long(_metile_register_index) + 1) && (long(_metile_register_index__) == long(_metile_register_index) + 2) && (long(_metile_register_index___) == long(_metile_register_index) + 3)) {\n _metile_vector_load_ = float4(*reinterpret_cast(W + _metile_register_index));\n } else {\n _metile_vector_load_[0] = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n _metile_vector_load_[1] = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n _metile_vector_load_[2] = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n _metile_vector_load_[3] = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n }\n float _metile_v36_r0 = _metile_vector_load_[0];\n float _metile_v36_r1 = _metile_vector_load_[1];\n float _metile_v36_r2 = _metile_vector_load_[2];\n float _metile_v36_r3 = _metile_vector_load_[3];\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if ((_metile_v43_r0) && (_metile_v43_r1) && (_metile_v43_r2) && (_metile_v43_r3) && (long(_off__metile_v44_r1) == long(_off__metile_v44_r0) + 1) && (long(_off__metile_v44_r2) == long(_off__metile_v44_r0) + 2) && (long(_off__metile_v44_r3) == long(_off__metile_v44_r0) + 3)) {\n *reinterpret_cast(Out + _off__metile_v44_r0) = packed_float4(float4(static_cast(_metile_v39_r0), static_cast(_metile_v39_r1), static_cast(_metile_v39_r2), static_cast(_metile_v39_r3)));\n } else {\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = static_cast(_metile_v39_r0); }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = static_cast(_metile_v39_r1); }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = static_cast(_metile_v39_r2); }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = static_cast(_metile_v39_r3); }\n }\n}", "source_sha256": "90092f2d024ec05aca53dadb1c2ad4b583c721cc8dccc7ae0562e9412f81c900", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 2, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "Grouped packed accesses retain independently masked scalar fallbacks; native vector values do not guarantee hardware vector register placement.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 8, 9, 0, 1, 2, 3, 4, 5, 6, 7 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 2, "grouped_stores": 1 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 518, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 217.85399999999998, "control": 217.54149999999998, "speedup": 0.9985655530768313 }, "gpu_us": { "candidate": 8.124974556267262, "control": 8.04167939350009, "speedup": 0.9897482555557148 } } }, { "frozen_register4": { "pairs": 458, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 219.14600000000002, "control": 219.3955, "speedup": 1.0011385103994597 }, "gpu_us": { "candidate": 8.124974556267262, "control": 8.083297871053219, "speedup": 0.9948705457567378 } } }, { "frozen_register4": { "pairs": 516, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 219.89600000000002, "control": 218.5005, "speedup": 0.9936538181685887 }, "gpu_us": { "candidate": 8.083356078714132, "control": 8.083326974883676, "speedup": 0.9999963995362603 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9977811258869027, "round_speedups": [ 0.9985655530768313, 1.0011385103994597, 0.9936538181685887 ], "candidate": 218.96370783608958, "control": 218.47785493306424 }, "gpu_us": { "speedup": 0.9948629363965372, "round_speedups": [ 0.9897482555557148, 0.9948705457567378, 0.9999963995362603 ], "candidate": 8.111077975899041, "control": 8.069410852444204 } } } } ], "selection": { "scope": "one layout/count policy for every dtype, width and batch size", "rule": "minimize training wall/ragged guard failures, then maximize worst aligned batch32/256 GPU speedup, then its geometric mean; ties follow declared variant order", "selected": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "scores": [ { "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "eligible": true, "regression_guard_failures": 0, "minimum_aligned_throughput_gpu_speedup": 1.0086978283172867, "geomean_aligned_throughput_gpu_speedup": 1.045561445420347, "training_gate": { "passed": false, "policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "failed_aligned_throughput_gpu_cases": [ "float16_32x1024", "float16_256x1024", "float32_32x1024", "float32_256x1024" ], "failed_wall_cases": [], "failed_ragged_gpu_cases": [] } }, { "variant": { "name": "register4_blocked4", "elements_per_thread": 4, "layout": "blocked4" }, "eligible": true, "regression_guard_failures": 6, "minimum_aligned_throughput_gpu_speedup": 0.9237474428973753, "geomean_aligned_throughput_gpu_speedup": 0.9718185576864061, "training_gate": { "passed": false, "policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "failed_aligned_throughput_gpu_cases": [ "float16_32x1024", "float16_256x1024", "float32_32x1024", "float32_256x1024" ], "failed_wall_cases": [], "failed_ragged_gpu_cases": [ "float16_1x1009", "float16_32x1009", "float16_256x1009", "float32_1x1009", "float32_32x1009", "float32_256x1009" ] } }, { "variant": { "name": "register8_striped", "elements_per_thread": 8, "layout": "striped" }, "eligible": true, "regression_guard_failures": 2, "minimum_aligned_throughput_gpu_speedup": 0.9882831778336025, "geomean_aligned_throughput_gpu_speedup": 1.0321442986083251, "training_gate": { "passed": false, "policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "failed_aligned_throughput_gpu_cases": [ "float16_32x1024", "float16_256x1024", "float32_32x1024", "float32_256x1024" ], "failed_wall_cases": [], "failed_ragged_gpu_cases": [ "float16_1x1009", "float32_1x1009" ] } }, { "variant": { "name": "register8_blocked4", "elements_per_thread": 8, "layout": "blocked4" }, "eligible": true, "regression_guard_failures": 6, "minimum_aligned_throughput_gpu_speedup": 0.8814602420184451, "geomean_aligned_throughput_gpu_speedup": 0.9208678007594686, "training_gate": { "passed": false, "policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "failed_aligned_throughput_gpu_cases": [ "float16_32x1024", "float16_256x1024", "float32_32x1024", "float32_256x1024" ], "failed_wall_cases": [], "failed_ragged_gpu_cases": [ "float16_1x1009", "float16_32x1009", "float16_256x1009", "float32_1x1009", "float32_32x1009", "float32_256x1009" ] } }, { "variant": { "name": "register16_striped", "elements_per_thread": 16, "layout": "striped" }, "eligible": true, "regression_guard_failures": 4, "minimum_aligned_throughput_gpu_speedup": 0.9542795309833677, "geomean_aligned_throughput_gpu_speedup": 1.00466326240963, "training_gate": { "passed": false, "policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "failed_aligned_throughput_gpu_cases": [ "float16_32x1024", "float16_256x1024", "float32_32x1024", "float32_256x1024" ], "failed_wall_cases": [], "failed_ragged_gpu_cases": [ "float16_1x1009", "float16_32x1009", "float32_1x1009", "float32_32x1009" ] } }, { "variant": { "name": "register16_blocked4", "elements_per_thread": 16, "layout": "blocked4" }, "eligible": true, "regression_guard_failures": 6, "minimum_aligned_throughput_gpu_speedup": 0.766666666588103, "geomean_aligned_throughput_gpu_speedup": 0.8232797524681654, "training_gate": { "passed": false, "policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "failed_aligned_throughput_gpu_cases": [ "float16_32x1024", "float16_256x1024", "float32_32x1024", "float32_256x1024" ], "failed_wall_cases": [], "failed_ragged_gpu_cases": [ "float16_1x1009", "float16_32x1009", "float16_256x1009", "float32_1x1009", "float32_32x1009", "float32_256x1009" ] } }, { "variant": { "name": "register32_striped", "elements_per_thread": 32, "layout": "striped" }, "eligible": true, "regression_guard_failures": 4, "minimum_aligned_throughput_gpu_speedup": 0.8381200151101741, "geomean_aligned_throughput_gpu_speedup": 0.9307341209660918, "training_gate": { "passed": false, "policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "failed_aligned_throughput_gpu_cases": [ "float16_32x1024", "float16_256x1024", "float32_32x1024", "float32_256x1024" ], "failed_wall_cases": [], "failed_ragged_gpu_cases": [ "float16_1x1009", "float16_32x1009", "float32_1x1009", "float32_32x1009" ] } }, { "variant": { "name": "register32_blocked4", "elements_per_thread": 32, "layout": "blocked4" }, "eligible": true, "regression_guard_failures": 8, "minimum_aligned_throughput_gpu_speedup": 0.5679061317298304, "geomean_aligned_throughput_gpu_speedup": 0.727493385335174, "training_gate": { "passed": false, "policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "failed_aligned_throughput_gpu_cases": [ "float16_32x1024", "float16_256x1024", "float32_32x1024", "float32_256x1024" ], "failed_wall_cases": [ "float16_1x1009", "float32_1x1009" ], "failed_ragged_gpu_cases": [ "float16_1x1009", "float16_32x1009", "float16_256x1009", "float32_1x1009", "float32_32x1009", "float32_256x1009" ] } }, { "variant": { "name": "register2_striped", "elements_per_thread": 2, "layout": "striped" }, "eligible": true, "regression_guard_failures": 1, "minimum_aligned_throughput_gpu_speedup": 1.017094119129839, "geomean_aligned_throughput_gpu_speedup": 1.0256124991977755, "training_gate": { "passed": false, "policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "failed_aligned_throughput_gpu_cases": [ "float16_32x1024", "float16_256x1024", "float32_32x1024", "float32_256x1024" ], "failed_wall_cases": [], "failed_ragged_gpu_cases": [ "float16_256x1009" ] } } ], "heldout_results_used": false } }