{ "kind": "register_tiling_validate", "recorded_at": "2026-10-02T18:46:49.486130+00:00", "process_id": 81907, "platform": "macOS-26.2-arm64-arm-64bit", "device": "Apple M5", "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "mlx_version": "0.32.0", "compiler_implementation_sha256": "f255b038cc297ff6ba053b68cc787f7e16d855c0b665ab82b8d5ea33c463f8be", "benchmark_source_sha256": "47a379ae8881b98ece7df1f415afed0c5f2b189f9459bf34a14198a22d112675", "benchmark_sources": { "rmsnorm_tiling.py": "01f23e4595e5a7f978945c8dde559b64415deea275c407dbb3de692b15605536", "register_rmsnorm.py": "3c6fb7144a3c48de6c74a2626eb7fd05b4c4d41918c7ac43d9dcc93165447c61" }, "baseline_export_sha256": "ddda22c512e09d77a855c6cbbd49b6f1bac26d5db71197d8c05b0e4f0ff257f9", "frozen_baseline": { "kind": "frozen_static_width_register4_baseline", "recorded_at": "2026-10-02T18:25:32.133814+00:00", "root": "/private/tmp/metile-tiling-baseline.AKA1sY", "compiler_implementation_sha256": "81570d03d2db5ba7146d00acd5feb8e3ed9e0a0139d9018a1bf4c0b83703f9cf", "device": "Apple M5", "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "seed": 1741, "epsilon": 1e-05, "gate_policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "cases": [ { "name": "float16_1x1009", "dtype": "float16", "batches": 1, "width": 1009, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "20ffd5db614652b191eacaaeaec1d5949ec0b2eac97fa1cb02c0c6d776e088b5", "correctness": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 376, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 307.896, "control": 307.021, "speedup": 0.9971581313170681 }, "gpu_us": { "candidate": 6.958318408578634, "control": 6.958318408578634, "speedup": 1.0 } } }, { "name": "float16_32x1009", "dtype": "float16", "batches": 32, "width": 1009, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "e6d696cff86bdf9ec8254c3438c13725f24b2b1f6073b44660a256dcea0488a8", "correctness": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 510, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 220.542, "control": 223.35399999999998, "speedup": 1.0127504058183927 }, "gpu_us": { "candidate": 3.1041563488543034, "control": 3.249995643272996, "speedup": 1.0469819422828104 } } }, { "name": "float16_256x1009", "dtype": "float16", "batches": 256, "width": 1009, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "3fe4b7685e23d624bcb19d6442cc8d72636943e6c185f3b0049a2ac1e0b63d81", "correctness": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 564, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 211.60399999999998, "control": 210.562, "speedup": 0.9950757074535455 }, "gpu_us": { "candidate": 5.62501372769475, "control": 5.62501372769475, "speedup": 1.0 } } }, { "name": "float16_1x1024", "dtype": "float16", "batches": 1, "width": 1024, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "3cc059cb43f2d2ee6f0120b1b81a1fb6efa6af199ab539eb734dc561564c6ebe", "correctness": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 617, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.125, "control": 199.125, "speedup": 1.0050473186119875 }, "gpu_us": { "candidate": 1.6666599549353123, "control": 1.6666599549353123, "speedup": 1.0 } } }, { "name": "float16_32x1024", "dtype": "float16", "batches": 32, "width": 1024, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "6e821d0e3f7ad3cc0206f556836dd56fc15c5cc3181cc0547765f5bce1880ac4", "correctness": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 615, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.875, "control": 198.209, "speedup": 0.9966511627906977 }, "gpu_us": { "candidate": 2.083310391753912, "control": 2.083310391753912, "speedup": 1.0 } } }, { "name": "float16_256x1024", "dtype": "float16", "batches": 256, "width": 1024, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "fcaf7de00cd83d1d1e75063d1ab252906b9f1076e1f1c8a88d773ec19ed2a30c", "correctness": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 597, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.375, "control": 204.25, "speedup": 0.999388379204893 }, "gpu_us": { "candidate": 4.958303179591894, "control": 4.958361387252808, "speedup": 1.0000117394315766 } } }, { "name": "float32_1x1009", "dtype": "float32", "batches": 1, "width": 1009, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "72c4fd9244d1e3fe8e922e59cd98ff745af158f79bcd15c587482eb6749d4442", "correctness": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 553, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.042, "control": 201.167, "speedup": 1.010676138704394 }, "gpu_us": { "candidate": 1.7500133253633976, "control": 1.7500133253633976, "speedup": 1.0 } } }, { "name": "float32_32x1009", "dtype": "float32", "batches": 32, "width": 1009, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "41fd264c427e4e182eaad0b6751f90d1477b7e8f193b298a4dc8ccbfebb45ec3", "correctness": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 614, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.20850000000002, "control": 197.2295, "speedup": 0.9950607567283946 }, "gpu_us": { "candidate": 2.41666566580534, "control": 2.41666566580534, "speedup": 1.0 } } }, { "name": "float32_256x1009", "dtype": "float32", "batches": 256, "width": 1009, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "7bf6ce415ddd84786a2d450acbead1c0e25e5540b52b07d28c1e7796b91c7626", "correctness": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 559, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 217.792, "control": 216.334, "speedup": 0.9933055392300911 }, "gpu_us": { "candidate": 8.375034667551517, "control": 8.375034667551517, "speedup": 1.0 } } }, { "name": "float32_1x1024", "dtype": "float32", "batches": 1, "width": 1024, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "ddb1751346f69e81810fa3e5e4fc2fa3d8214ffaace8e689775a59ca252f7042", "correctness": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 615, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.166, "control": 197.292, "speedup": 0.9955895562306349 }, "gpu_us": { "candidate": 1.708336640149355, "control": 1.708336640149355, "speedup": 1.0 } } }, { "name": "float32_32x1024", "dtype": "float32", "batches": 32, "width": 1024, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "0fc05dcd6172e2eebffb6471582bea984c5a888fc3b3a095d91b296908e6567b", "correctness": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 605, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.334, "control": 197.875, "speedup": 0.992680626486199 }, "gpu_us": { "candidate": 2.374988980591297, "control": 2.374988980591297, "speedup": 1.0 } } }, { "name": "float32_256x1024", "dtype": "float32", "batches": 256, "width": 1024, "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "d91bbc8e56d1e705bcdef1e433ae3b5ce1d9e73a225cd6afc919bf59342546a9", "correctness": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_register_index = int(_metile_register_thread);\n int _metile_register_packed_ = _metile_register_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_register_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_register_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] } } }, "compilation": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "initial_same_kernel_pair": { "pairs": 570, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 215.97899999999998, "control": 214.54149999999998, "speedup": 0.9933442603216054 }, "gpu_us": { "candidate": 8.04167939350009, "control": 8.083297871053219, "speedup": 1.0051753465310702 } } } ] }, "gate_policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "precision_comparison": { "class": "same_storage_precision", "same_weight_representation": true, "bitwise_exact": false, "primary_policy": "identical storage dtype, FP32 sum/normalization/weight multiply, final output cast", "primary_mlx_comparator": "mx.compile explicit full-FP32 graph then final output cast", "mlx_fast_caveat": "secondary only: FP16 normalization rounds to storage before weight multiply; checked against its own rounding reference", "mlx_fast_source": "https://github.com/ml-explore/mlx/blob/v0.32.0/mlx/backend/metal/kernels/rms_norm.metal", "relaxed_precision": false }, "configuration": { "seed": 9473, "rounds": 3, "warmup_ms": 100.0, "rep_ms": 250.0 }, "precision": { "primary": "identical storage dtype, FP32 sum/normalization/weight multiply, final output cast; not bitwise exact", "mlx_matched": "mx.compile explicit full-FP32 graph then final output cast; primary matched-policy wall comparison", "mlx_fast": "secondary only: FP16 normalization rounds to storage before weight multiply, checked against its own rounding reference", "mlx_fast_source": "https://github.com/ml-explore/mlx/blob/v0.32.0/mlx/backend/metal/kernels/rms_norm.metal", "relaxed_precision": false }, "measurement": { "gpu": "paired Metal command-buffer timestamps for candidate and exact frozen register4 shader", "wall": "paired per-invocation synchronized wall latency, compile/setup excluded; MLX includes allocation/evaluation", "compilation": "all meTile shaders rebuilt offline with identical -O2 -ffast-math compiler and default Metal language version", "specialization": "both frozen and current kernels use static N and BLOCK=1024; only compiler/ownership changes vary", "ordering": "AB/BA dispatch pairs; variant order rotates across cases; comparator order rotates across rounds" }, "cases": [ { "name": "float16_1x1009", "dtype": "float16", "batches": 1, "width": 1009, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "d6f8c293ba5a765e28fbac2321aa6a0ed3b614a04d397c0083520a5e600ef512", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "mlx_matched": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "mlx_fast": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "ca8204464d79c2fc321323a988388e3cf7608e7f4edfce8846896960ec8dd552", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 661, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.334, "control": 202.792, "speedup": 0.9924535319623753 }, "gpu_us": { "candidate": 1.583306584507227, "control": 1.6249832697212696, "speedup": 1.0263225616705267 } }, "mlx_matched": { "pairs": 584, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 208.41649999999998, "control": 215.72899999999998, "speedup": 1.0350859936713264 } }, "mlx_fast": { "pairs": 613, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.708, "control": 198.5, "speedup": 0.9840958216828286 } } }, { "mlx_matched": { "pairs": 603, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.916, "control": 202.5, "speedup": 1.0028922918441332 } }, "mlx_fast": { "pairs": 571, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 207.167, "control": 203.584, "speedup": 0.9827047744090517 } }, "frozen_register4": { "pairs": 614, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.89600000000002, "control": 200.4995, "speedup": 1.0030190699163566 }, "gpu_us": { "candidate": 1.5416298992931843, "control": 1.5833647921681404, "speedup": 1.0270719275061355 } } }, { "mlx_fast": { "pairs": 613, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.833, "control": 199.041, "speedup": 0.9813048172634631 } }, "frozen_register4": { "pairs": 606, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.39600000000002, "control": 199.5, "speedup": 1.000521575156974 }, "gpu_us": { "candidate": 1.5416298992931843, "control": 1.5833647921681404, "speedup": 1.0270719275061355 } }, "mlx_matched": { "pairs": 603, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.25, "control": 203.041, "speedup": 1.0139375780274658 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9986545306773581, "round_speedups": [ 0.9924535319623753, 1.0030190699163566, 1.000521575156974 ], "candidate": 201.19648732519417, "control": 200.92578362367482 }, "gpu_us": { "speedup": 1.0268220781198916, "round_speedups": [ 1.0263225616705267, 1.0270719275061355, 1.0270719275061355 ], "candidate": 1.5553987863808048, "control": 1.5971178141366953 } }, "mlx_fast": { "wall_us": { "speedup": 0.9827011438783095, "round_speedups": [ 0.9840958216828286, 0.9827047744090517, 0.9813048172634631 ], "candidate": 203.8891450582082, "control": 200.36209607307183 } }, "mlx_matched": { "wall_us": { "speedup": 1.0172178708691655, "round_speedups": [ 1.0350859936713264, 1.0028922918441332, 1.0139375780274658 ], "candidate": 203.49720678092729, "control": 207.00099540951706 } } } }, { "name": "float16_32x1009", "dtype": "float16", "batches": 32, "width": 1009, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "5554a685ddab4162e5b9163d96de7079c0ff02cbf1ec96a83174161b0218b361", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "mlx_matched": { "passed": true, "max_absolute_error": 0.000244140625, "rtol": 0.001, "atol": 0.002 }, "mlx_fast": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "ca8204464d79c2fc321323a988388e3cf7608e7f4edfce8846896960ec8dd552", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 611, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.042, "control": 201.083, "speedup": 1.0052039071794923 }, "gpu_us": { "candidate": 1.9583385437726974, "control": 2.00001522898674, "speedup": 1.0212816549756272 } }, "mlx_matched": { "pairs": 596, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.16649999999998, "control": 209.02100000000002, "speedup": 1.039044771370979 } }, "mlx_fast": { "pairs": 615, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.0, "control": 199.458, "speedup": 0.9923283582089553 } } }, { "mlx_matched": { "pairs": 594, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.4375, "control": 209.959, "speedup": 1.0371546773695586 } }, "mlx_fast": { "pairs": 581, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.083, "control": 199.416, "speedup": 0.9868024524576535 } }, "frozen_register4": { "pairs": 570, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.04149999999998, "control": 200.66649999999998, "speedup": 0.9981347134795552 }, "gpu_us": { "candidate": 1.9583385437726974, "control": 2.00001522898674, "speedup": 1.0212816549756272 } } }, { "mlx_fast": { "pairs": 611, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.375, "control": 200.0, "speedup": 0.9882643607164917 } }, "frozen_register4": { "pairs": 617, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.083, "control": 198.75, "speedup": 0.9983273308117719 }, "gpu_us": { "candidate": 1.9999570213258266, "control": 2.00001522898674, "speedup": 1.0000291044558922 } }, "mlx_matched": { "pairs": 596, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.91649999999998, "control": 208.97899999999998, "speedup": 1.0349773297377876 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.000549923036294, "round_speedups": [ 1.0052039071794923, 0.9981347134795552, 0.9983273308117719 ], "candidate": 200.05390209308064, "control": 200.163916342342 }, "gpu_us": { "speedup": 1.0141477554843903, "round_speedups": [ 1.0212816549756272, 1.0212816549756272, 1.0000291044558922 ], "candidate": 1.9721142389468358, "control": 2.00001522898674 } }, "mlx_fast": { "wall_us": { "speedup": 0.9891289632448561, "round_speedups": [ 0.9923283582089553, 0.9868024524576535, 0.9882643607164917 ], "candidate": 201.81846557142825, "control": 199.62448961433446 } }, "mlx_matched": { "wall_us": { "speedup": 1.0370575944178335, "round_speedups": [ 1.039044771370979, 1.0371546773695586, 1.0349773297377876 ], "candidate": 201.83949223222274, "control": 209.31917827286574 } } } }, { "name": "float16_256x1009", "dtype": "float16", "batches": 256, "width": 1009, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "b1fe01c17c282dc265d750302d65238bff0f311379c37b5e9650cafe40ad9a8a", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 }, "mlx_matched": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "mlx_fast": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "ca8204464d79c2fc321323a988388e3cf7608e7f4edfce8846896960ec8dd552", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "a68e9e4f834e94b5bfd3ec1a01f1b3ae09cce18903d445219b80842121a1154b", "rounds": [ { "frozen_register4": { "pairs": 586, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 207.9375, "control": 210.7295, "speedup": 1.0134271115118725 }, "gpu_us": { "candidate": 5.4166303016245365, "control": 5.583337042480707, "speedup": 1.0307768357028488 } }, "mlx_matched": { "pairs": 552, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 208.47899999999998, "control": 232.458, "speedup": 1.1150187788698143 } }, "mlx_fast": { "pairs": 573, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 210.542, "control": 209.333, "speedup": 0.9942576778030037 } } }, { "mlx_matched": { "pairs": 555, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 212.25, "control": 229.958, "speedup": 1.0834299175500588 } }, "mlx_fast": { "pairs": 584, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 210.02100000000002, "control": 211.41649999999998, "speedup": 1.0066445736378742 } }, "frozen_register4": { "pairs": 588, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 209.437, "control": 210.292, "speedup": 1.0040823732196316 }, "gpu_us": { "candidate": 5.41668850928545, "control": 5.583337042480707, "speedup": 1.0307657589890176 } } }, { "mlx_fast": { "pairs": 521, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 213.375, "control": 215.792, "speedup": 1.011327475102519 } }, "frozen_register4": { "pairs": 595, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 206.25, "control": 207.333, "speedup": 1.005250909090909 }, "gpu_us": { "candidate": 5.41668850928545, "control": 5.583337042480707, "speedup": 1.0307657589890176 } }, "mlx_matched": { "pairs": 555, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 210.334, "control": 234.042, "speedup": 1.112715966034973 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.007578237524518, "round_speedups": [ 1.0134271115118725, 1.0040823732196316, 1.005250909090909 ], "candidate": 207.87075555470096, "control": 209.44604951469557 }, "gpu_us": { "speedup": 1.0307694512137358, "round_speedups": [ 1.0307768357028488, 1.0307657589890176, 1.0307657589890176 ], "candidate": 5.4166691066623125, "control": 5.583337042480708 } }, "mlx_fast": { "wall_us": { "speedup": 1.0040506895225136, "round_speedups": [ 0.9942576778030037, 1.0066445736378742, 1.011327475102519 ], "candidate": 211.30754291967227, "control": 212.16348416980523 } }, "mlx_matched": { "wall_us": { "speedup": 1.103627317408676, "round_speedups": [ 1.1150187788698143, 1.0834299175500588, 1.112715966034973 ], "candidate": 210.3486997089402, "control": 232.14657118018056 } } } }, { "name": "float16_1x1024", "dtype": "float16", "batches": 1, "width": 1024, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "5788b26fccc0f4c16bf5fa37806b50aeedce80dec44ee6bc5cfeb17488931f02", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "mlx_matched": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 }, "mlx_fast": { "passed": true, "max_absolute_error": 0.0, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "a30e8c10d04f7806837b7362bac4a0f599f0d6d17735fc2e88198ca5dcb4e73d", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 583, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.084, "control": 200.25, "speedup": 1.0008296515463506 }, "gpu_us": { "candidate": 1.500011421740055, "control": 1.625041477382183, "speedup": 1.0833527357392316 } }, "mlx_matched": { "pairs": 600, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.75, "control": 203.7705, "speedup": 1.0100148698884759 } }, "mlx_fast": { "pairs": 612, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.042, "control": 197.875, "speedup": 0.979375575375417 } } }, { "mlx_matched": { "pairs": 606, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.66649999999998, "control": 203.9795, "speedup": 1.016509980490017 } }, "mlx_fast": { "pairs": 615, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.833, "control": 198.458, "speedup": 0.9881742542311274 } }, "frozen_register4": { "pairs": 622, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.58350000000002, "control": 198.5, "speedup": 1.0046385452226527 }, "gpu_us": { "candidate": 1.500011421740055, "control": 1.5416881069540977, "speedup": 1.0277842452464105 } } }, { "mlx_fast": { "pairs": 610, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.14600000000002, "control": 200.91649999999998, "speedup": 0.9939177624093476 } }, "frozen_register4": { "pairs": 601, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.583, "control": 199.125, "speedup": 0.9977052153740549 }, "gpu_us": { "candidate": 1.5416881069540977, "control": 1.6249832697212696, "speedup": 1.054028543381409 } }, "mlx_matched": { "pairs": 601, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.209, "control": 206.5, "speedup": 1.026296040435567 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0010537902540992, "round_speedups": [ 1.0008296515463506, 1.0046385452226527, 0.9977052153740549 ], "candidate": 199.0805631393305, "control": 199.2903522965474 }, "gpu_us": { "speedup": 1.0548112120686093, "round_speedups": [ 1.0833527357392316, 1.0277842452464105, 1.054028543381409 ], "candidate": 1.5137769383809812, "control": 1.596748887175151 } }, "mlx_fast": { "wall_us": { "speedup": 0.9871377304620963, "round_speedups": [ 0.979375575375417, 0.9881742542311274, 0.9939177624093476 ], "candidate": 201.67278492557574, "control": 199.07881520740344 } }, "mlx_matched": { "wall_us": { "speedup": 1.0175849832804682, "round_speedups": [ 1.0100148698884759, 1.016509980490017, 1.026296040435567 ], "candidate": 201.20801378016907, "control": 204.74625333838964 } } } }, { "name": "float16_32x1024", "dtype": "float16", "batches": 32, "width": 1024, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "41392812a0c995fa7df504bbe6893544cd787281bc6904b2d6f3ef4015a1ce2b", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 }, "mlx_matched": { "passed": true, "max_absolute_error": 0.00048828125, "rtol": 0.001, "atol": 0.002 }, "mlx_fast": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "a30e8c10d04f7806837b7362bac4a0f599f0d6d17735fc2e88198ca5dcb4e73d", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 605, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.167, "control": 201.375, "speedup": 0.9960824466901126 }, "gpu_us": { "candidate": 1.7916900105774403, "control": 1.9166618585586548, "speedup": 1.069750820311231 } }, "mlx_matched": { "pairs": 597, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.334, "control": 208.5, "speedup": 1.0304743641701346 } }, "mlx_fast": { "pairs": 610, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.91649999999998, "control": 198.66649999999998, "speedup": 0.9790554242755025 } } }, { "mlx_matched": { "pairs": 594, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.54149999999998, "control": 208.89600000000002, "speedup": 1.0364912437388827 } }, "mlx_fast": { "pairs": 613, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.542, "control": 198.916, "speedup": 0.982097540263254 } }, "frozen_register4": { "pairs": 612, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.208, "control": 200.125, "speedup": 0.9995854311516024 }, "gpu_us": { "candidate": 1.7500133253633976, "control": 1.9166618585586548, "speedup": 1.0952270081490105 } } }, { "mlx_fast": { "pairs": 613, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.625, "control": 199.958, "speedup": 0.9917321760694359 } }, "frozen_register4": { "pairs": 615, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.916, "control": 200.0, "speedup": 1.0004201764741192 }, "gpu_us": { "candidate": 1.7916318029165268, "control": 1.9166618585586548, "speedup": 1.0697855750487328 } }, "mlx_matched": { "pairs": 588, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.125, "control": 207.0625, "speedup": 1.0295214418893723 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.99869424870164, "round_speedups": [ 0.9960824466901126, 0.9995854311516024, 1.0004201764741192 ], "candidate": 200.7611843941461, "control": 200.4990402169631 }, "gpu_us": { "speedup": 1.0781880239364319, "round_speedups": [ 1.069750820311231, 1.0952270081490105, 1.0697855750487328 ], "candidate": 1.7776694008907468, "control": 1.9166618585586548 } }, "mlx_fast": { "wall_us": { "speedup": 0.9842802442466907, "round_speedups": [ 0.9790554242755025, 0.982097540263254, 0.9917321760694359 ], "candidate": 202.36043878409478, "control": 199.17938211227624 } }, "mlx_matched": { "wall_us": { "speedup": 1.0321577437859828, "round_speedups": [ 1.0304743641701346, 1.0364912437388827, 1.0295214418893723 ], "candidate": 201.66621022957594, "control": 208.15134054842883 } } } }, { "name": "float16_256x1024", "dtype": "float16", "batches": 256, "width": 1024, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "6ef50c4533756dc08e97d195665eb272011778737bdac2b66d413cacbb0539ab", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 }, "frozen_register4": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 }, "mlx_matched": { "passed": true, "max_absolute_error": 0.001953125, "rtol": 0.001, "atol": 0.002 }, "mlx_fast": { "passed": true, "max_absolute_error": 0.0009765625, "rtol": 0.001, "atol": 0.002 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const half* X [[buffer(0)]],\n device const half* W [[buffer(1)]],\n device half* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n half _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n half _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n half _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n half _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n half _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n half _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n half _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n half _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "a30e8c10d04f7806837b7362bac4a0f599f0d6d17735fc2e88198ca5dcb4e73d", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f16", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "3148c2961de2347273056c545e2ddcdf1cb7eea6896e237430c4c8eb6d1e54be", "rounds": [ { "frozen_register4": { "pairs": 598, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 203.5625, "control": 204.0625, "speedup": 1.0024562480810562 }, "gpu_us": { "candidate": 4.583329427987337, "control": 4.9166264943778515, "speedup": 1.0727194219021856 } }, "mlx_matched": { "pairs": 561, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 209.875, "control": 231.0, "speedup": 1.1006551518761167 } }, "mlx_fast": { "pairs": 594, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 205.708, "control": 205.958, "speedup": 1.0012153149124001 } } }, { "mlx_matched": { "pairs": 560, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 207.062, "control": 230.97899999999998, "speedup": 1.115506466662159 } }, "mlx_fast": { "pairs": 531, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 206.916, "control": 210.541, "speedup": 1.0175191865297994 } }, "frozen_register4": { "pairs": 569, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 207.583, "control": 208.0, "speedup": 1.0020088350202088 }, "gpu_us": { "candidate": 4.583329427987337, "control": 4.958303179591894, "speedup": 1.0818125246059866 } } }, { "mlx_fast": { "pairs": 559, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 218.667, "control": 223.916, "speedup": 1.0240045365784503 } }, "frozen_register4": { "pairs": 649, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 208.583, "control": 208.875, "speedup": 1.001399922333076 }, "gpu_us": { "candidate": 4.583329427987337, "control": 4.916684702038765, "speedup": 1.072732121766297 } }, "mlx_matched": { "pairs": 341, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 326.416, "control": 398.125, "speedup": 1.2196859222587129 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0019549082794663, "round_speedups": [ 1.0024562480810562, 1.0020088350202088, 1.001399922333076 ], "candidate": 206.5647237365133, "control": 206.96853882519164 }, "gpu_us": { "speedup": 1.0757461770689332, "round_speedups": [ 1.0727194219021856, 1.0818125246059866, 1.072732121766297 ], "candidate": 4.583329427987338, "control": 4.930499110404918 } }, "mlx_fast": { "wall_us": { "speedup": 1.014200897714709, "round_speedups": [ 1.0012153149124001, 1.0175191865297994, 1.0240045365784503 ], "candidate": 210.3501539660062, "control": 213.3373149867509 } }, "mlx_matched": { "wall_us": { "speedup": 1.1440819259373392, "round_speedups": [ 1.1006551518761167, 1.115506466662159, 1.2196859222587129 ], "candidate": 242.07179137593496, "control": 276.9499612924814 } } } }, { "name": "float32_1x1009", "dtype": "float32", "batches": 1, "width": 1009, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "f13ad154dce82c599466a62d9fefda45da8cffe99a7aba166483d0cf189c8276", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 4.76837158203125e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 4.76837158203125e-07, "rtol": 3e-05, "atol": 2e-05 }, "mlx_matched": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "mlx_fast": { "passed": true, "max_absolute_error": 4.76837158203125e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "c1d33e27fc56debd55c6a508dc39b24b01c51c4f01d8ebe463b73c7d94ad343d", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 575, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 205.292, "control": 204.542, "speedup": 0.9963466671862518 }, "gpu_us": { "candidate": 1.6249832697212696, "control": 1.6666599549353123, "speedup": 1.0256474549557617 } }, "mlx_matched": { "pairs": 610, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.58350000000002, "control": 200.02100000000002, "speedup": 0.9873508948162116 } }, "mlx_fast": { "pairs": 615, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.875, "control": 197.333, "speedup": 0.9775009287925697 } } }, { "mlx_matched": { "pairs": 608, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.458, "control": 200.292, "speedup": 0.994212193112212 } }, "mlx_fast": { "pairs": 611, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.958, "control": 198.583, "speedup": 0.9832886045613445 } }, "frozen_register4": { "pairs": 617, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.792, "control": 198.416, "speedup": 0.9981085757978188 }, "gpu_us": { "candidate": 1.6249832697212696, "control": 1.708336640149355, "speedup": 1.0512949099115234 } } }, { "mlx_fast": { "pairs": 612, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.95850000000002, "control": 199.1455, "speedup": 0.9909782368001353 } }, "frozen_register4": { "pairs": 616, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.8125, "control": 199.10399999999998, "speedup": 1.0014662055957246 }, "gpu_us": { "candidate": 1.6249832697212696, "control": 1.708336640149355, "speedup": 1.0512949099115234 } }, "mlx_matched": { "pairs": 612, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.187, "control": 199.958, "speedup": 0.9938912553992056 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9986382260667312, "round_speedups": [ 0.9963466671862518, 0.9981085757978188, 1.0014662055957246 ], "candidate": 200.94237842509708, "control": 200.66874033206875 }, "gpu_us": { "speedup": 1.042675278524106, "round_speedups": [ 1.0256474549557617, 1.0512949099115234, 1.0512949099115234 ], "candidate": 1.6249832697212696, "control": 1.6943298833536375 } }, "mlx_fast": { "wall_us": { "speedup": 0.9839071137542699, "round_speedups": [ 0.9775009287925697, 0.9832886045613445, 0.9909782368001353 ], "candidate": 201.59665746314528, "control": 198.35238538707154 } }, "mlx_matched": { "wall_us": { "speedup": 0.9918130680804753, "round_speedups": [ 0.9873508948162116, 0.994212193112212, 0.9938912553992056 ], "candidate": 201.74192831428965, "control": 200.09028088186685 } } } }, { "name": "float32_32x1009", "dtype": "float32", "batches": 32, "width": 1009, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "1aa98eaf8559293d68537497ba4b1d6ffffe410fe2a519e1363d883bbed3f406", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "mlx_matched": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "mlx_fast": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "c1d33e27fc56debd55c6a508dc39b24b01c51c4f01d8ebe463b73c7d94ad343d", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 617, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.542, "control": 200.0, "speedup": 1.0073435343655246 }, "gpu_us": { "candidate": 2.333370503038168, "control": 2.41666566580534, "speedup": 1.0356973582458153 } }, "mlx_matched": { "pairs": 404, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 266.2085, "control": 297.16650000000004, "speedup": 1.1162923047160402 } }, "mlx_fast": { "pairs": 391, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 315.0, "control": 314.459, "speedup": 0.9982825396825397 } } }, { "mlx_matched": { "pairs": 591, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.375, "control": 209.458, "speedup": 1.0248709480122324 } }, "mlx_fast": { "pairs": 613, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.458, "control": 199.584, "speedup": 0.9956399844356424 } }, "frozen_register4": { "pairs": 616, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.6045, "control": 198.54149999999998, "speedup": 0.999682786643807 }, "gpu_us": { "candidate": 2.333370503038168, "control": 2.3750471882522106, "speedup": 1.017861151994412 } } }, { "mlx_fast": { "pairs": 611, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.417, "control": 199.625, "speedup": 0.9911030349970459 } }, "frozen_register4": { "pairs": 545, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 213.0, "control": 213.833, "speedup": 1.0039107981220656 }, "gpu_us": { "candidate": 2.7500209398567677, "control": 2.7916976250708103, "speedup": 1.0151550428616785 } }, "mlx_matched": { "pairs": 489, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 233.083, "control": 238.625, "speedup": 1.0237769378290138 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0036408147400986, "round_speedups": [ 1.0073435343655246, 0.999682786643807, 1.0039107981220656 ], "candidate": 203.270190166567, "control": 204.0102592711481 }, "gpu_us": { "speedup": 1.0228640807409126, "round_speedups": [ 1.0356973582458153, 1.017861151994412, 1.0151550428616785 ], "candidate": 2.4647212110595405, "control": 2.5210747958330453 } }, "mlx_fast": { "wall_us": { "speedup": 0.9950040997911351, "round_speedups": [ 0.9982825396825397, 0.9956399844356424, 0.9911030349970459 ], "candidate": 233.42284425756944, "control": 232.25668702118935 } }, "mlx_matched": { "wall_us": { "speedup": 1.0541056758649527, "round_speedups": [ 1.1162923047160402, 1.0248709480122324, 1.0237769378290138 ], "candidate": 233.19546258328512, "control": 245.81266069499395 } } } }, { "name": "float32_256x1009", "dtype": "float32", "batches": 256, "width": 1009, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "04bba57bf1faebf6990e5407c042b12b66a56dc9105d818df66b0027678d4be7", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 1.430511474609375e-06, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 1.430511474609375e-06, "rtol": 3e-05, "atol": 2e-05 }, "mlx_matched": { "passed": true, "max_absolute_error": 1.430511474609375e-06, "rtol": 3e-05, "atol": 2e-05 }, "mlx_fast": { "passed": true, "max_absolute_error": 1.430511474609375e-06, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1009;\n int v9 = v0 * 1009;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1009;\n bool _metile_v17_r1 = _metile_register_index_ < 1009;\n bool _metile_v17_r2 = _metile_register_index__ < 1009;\n bool _metile_v17_r3 = _metile_register_index___ < 1009;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1009.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1009;\n bool _metile_v33_r1 = _metile_register_index_ < 1009;\n bool _metile_v33_r2 = _metile_register_index__ < 1009;\n bool _metile_v33_r3 = _metile_register_index___ < 1009;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1009;\n bool _metile_v42_r1 = _metile_register_index_ < 1009;\n bool _metile_v42_r2 = _metile_register_index__ < 1009;\n bool _metile_v42_r3 = _metile_register_index___ < 1009;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "c1d33e27fc56debd55c6a508dc39b24b01c51c4f01d8ebe463b73c7d94ad343d", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "4e9632bc130a77261d03cc052ec4bc3bb1eb71ca5c68830bd6c0fff11b601559", "rounds": [ { "frozen_register4": { "pairs": 382, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 327.188, "control": 326.47900000000004, "speedup": 0.9978330501118624 }, "gpu_us": { "candidate": 23.270811652764678, "control": 24.708337150514126, "speedup": 1.0617737584403792 } }, "mlx_matched": { "pairs": 546, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 219.66649999999998, "control": 230.52100000000002, "speedup": 1.0494135428023847 } }, "mlx_fast": { "pairs": 568, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 218.20850000000002, "control": 217.8125, "speedup": 0.9981852219322345 } } }, { "mlx_matched": { "pairs": 544, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 218.5005, "control": 230.584, "speedup": 1.055301932947522 } }, "mlx_fast": { "pairs": 557, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 217.459, "control": 219.709, "speedup": 1.0103467780133266 } }, "frozen_register4": { "pairs": 575, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 216.375, "control": 215.792, "speedup": 0.9973056036972848 }, "gpu_us": { "candidate": 8.333299774676561, "control": 8.374976459890604, "speedup": 1.0050012223658018 } } }, { "mlx_fast": { "pairs": 533, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 223.917, "control": 221.834, "speedup": 0.9906974459286253 } }, "frozen_register4": { "pairs": 570, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 218.29149999999998, "control": 217.58350000000002, "speedup": 0.9967566304688915 }, "gpu_us": { "candidate": 8.333299774676561, "control": 8.375034667551517, "speedup": 1.00500820731324 } }, "mlx_matched": { "pairs": 546, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 219.9785, "control": 231.02100000000002, "speedup": 1.0501980875403734 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 0.9972983312609012, "round_speedups": [ 0.9978330501118624, 0.9973056036972848, 0.9967566304688915 ], "candidate": 249.08472245864078, "control": 248.41177805058723 }, "gpu_us": { "speedup": 1.0235822087869486, "round_speedups": [ 1.0617737584403792, 1.0050012223658018, 1.00500820731324 ], "candidate": 11.7349663084546, "control": 12.011702734048384 } }, "mlx_fast": { "wall_us": { "speedup": 0.9997104074951391, "round_speedups": [ 0.9981852219322345, 1.0103467780133266, 0.9906974459286253 ], "candidate": 219.84269489679573, "control": 219.77903010010516 } }, "mlx_matched": { "wall_us": { "speedup": 1.0516346176204714, "round_speedups": [ 1.0494135428023847, 1.055301932947522, 1.0501980875403734 ], "candidate": 219.3809101602034, "control": 230.70855956955634 } } } }, { "name": "float32_1x1024", "dtype": "float32", "batches": 1, "width": 1024, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "15b2d7a1b2f3cb4ff9fb2046e87c3019ad9dcf6f7b2e07869220eab417ab7fc3", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "mlx_matched": { "passed": true, "max_absolute_error": 0.0, "rtol": 3e-05, "atol": 2e-05 }, "mlx_fast": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "26dcd97c409e667a170eb1ec796096fa645431253522d88e56e53edb0819b727", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 621, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.667, "control": 199.5, "speedup": 1.0041929459849899 }, "gpu_us": { "candidate": 1.5416881069540977, "control": 1.7082784324884415, "speedup": 1.108057086762818 } }, "mlx_matched": { "pairs": 605, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.75, "control": 202.5, "speedup": 1.0087173100871731 } }, "mlx_fast": { "pairs": 485, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 237.959, "control": 240.292, "speedup": 1.0098042099689442 } } }, { "mlx_matched": { "pairs": 606, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.1045, "control": 200.0, "speedup": 0.9895870700553426 } }, "mlx_fast": { "pairs": 532, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 204.08350000000002, "control": 203.6455, "speedup": 0.9978538196375503 } }, "frozen_register4": { "pairs": 618, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 198.2705, "control": 198.792, "speedup": 1.002630245044018 }, "gpu_us": { "candidate": 1.500011421740055, "control": 1.6249832697212696, "speedup": 1.083313930927435 } } }, { "mlx_fast": { "pairs": 614, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.2295, "control": 198.375, "speedup": 0.9858147041065053 } }, "frozen_register4": { "pairs": 617, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 199.5, "control": 199.25, "speedup": 0.9987468671679198 }, "gpu_us": { "candidate": 1.500011421740055, "control": 1.6249832697212696, "speedup": 1.083313930927435 } }, "mlx_matched": { "pairs": 608, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.04149999999998, "control": 200.687, "speedup": 0.9932959317763926 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0018540678039114, "round_speedups": [ 1.0041929459849899, 1.002630245044018, 0.9987468671679198 ], "candidate": 198.81184020940648, "control": 199.18045084137518 }, "gpu_us": { "speedup": 1.091499641086997, "round_speedups": [ 1.108057086762818, 1.083313930927435, 1.083313930927435 ], "candidate": 1.5137769383809812, "control": 1.652286984928614 } }, "mlx_fast": { "wall_us": { "speedup": 0.9977761780068037, "round_speedups": [ 1.0098042099689442, 0.9978538196375503, 0.9858147041065053 ], "candidate": 213.79648414000408, "control": 213.32103881650553 } }, "mlx_matched": { "wall_us": { "speedup": 0.9971658134007987, "round_speedups": [ 1.0087173100871731, 0.9895870700553426, 0.9932959317763926 ], "candidate": 201.63103242137893, "control": 201.05957245130713 } } } }, { "name": "float32_32x1024", "dtype": "float32", "batches": 32, "width": 1024, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "416f28be6885381eb5144f423d06fa77f23366329b3a1e34dfe0fe0b166273b8", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "mlx_matched": { "passed": true, "max_absolute_error": 7.152557373046875e-07, "rtol": 3e-05, "atol": 2e-05 }, "mlx_fast": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "26dcd97c409e667a170eb1ec796096fa645431253522d88e56e53edb0819b727", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 609, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.583, "control": 200.5, "speedup": 0.999586206208901 }, "gpu_us": { "candidate": 2.333370503038168, "control": 2.374988980591297, "speedup": 1.0178362062514033 } }, "mlx_matched": { "pairs": 598, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.875, "control": 207.16649999999998, "speedup": 1.0262117647058824 } }, "mlx_fast": { "pairs": 579, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 205.292, "control": 202.041, "speedup": 0.984164020030006 } } }, { "mlx_matched": { "pairs": 597, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.708, "control": 204.958, "speedup": 1.0211750403571358 } }, "mlx_fast": { "pairs": 613, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 202.417, "control": 198.625, "speedup": 0.9812663956090645 } }, "frozen_register4": { "pairs": 612, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 197.8545, "control": 198.08350000000002, "speedup": 1.0011574161820935 }, "gpu_us": { "candidate": 2.333370503038168, "control": 2.374988980591297, "speedup": 1.0178362062514033 } } }, { "mlx_fast": { "pairs": 613, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 201.417, "control": 199.542, "speedup": 0.9906909545867528 } }, "frozen_register4": { "pairs": 609, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.542, "control": 200.584, "speedup": 1.0002094324380928 }, "gpu_us": { "candidate": 2.3333122953772545, "control": 2.374988980591297, "speedup": 1.0178615975652348 } }, "mlx_matched": { "pairs": 600, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 200.70850000000002, "control": 205.89600000000002, "speedup": 1.025845940754876 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0003174763766853, "round_speedups": [ 0.999586206208901, 1.0011574161820935, 1.0002094324380928 ], "candidate": 199.65573927737645, "control": 199.71912525806653 }, "gpu_us": { "speedup": 1.0178446699523014, "round_speedups": [ 1.0178362062514033, 1.0178362062514033, 1.0178615975652348 ], "candidate": 2.333351100323191, "control": 2.374988980591297 } }, "mlx_fast": { "wall_us": { "speedup": 0.9853659160384681, "round_speedups": [ 0.984164020030006, 0.9812663956090645, 0.9906909545867528 ], "candidate": 203.03537452006535, "control": 200.06413780217756 } }, "mlx_matched": { "wall_us": { "speedup": 1.0244083463801386, "round_speedups": [ 1.0262117647058824, 1.0211750403571358, 1.025845940754876 ], "candidate": 201.09641547884874, "control": 206.0048464436607 } } } }, { "name": "float32_256x1024", "dtype": "float32", "batches": 256, "width": 1024, "status": "measured", "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "input_sha256": "f9b5d63567b5ec31f59a97fbe844dc9754feaf90a4a82fae03b23d30e6797d88", "validated_before_timing": true, "correctness": { "candidate": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "frozen_register4": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "mlx_matched": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 }, "mlx_fast": { "passed": true, "max_absolute_error": 9.5367431640625e-07, "rtol": 3e-05, "atol": 2e-05 } }, "compilations": { "candidate": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" }, "frozen_register4": { "path": "offline", "precompiled": true, "offline_compiler_available": true, "metal_compiler": "Apple metal version 32023.864 (metalfe-32023.864)\nTarget: air64-apple-darwin25.2.0\nThread model: posix\nInstalledDir: /private/var/run/com.apple.security.cryptexd/mnt/com.apple.MobileAsset.MetalToolchain-v17.3.7003.10.GzPOjD/Metal.xctoolchain/usr/metal/current/bin", "flags": [ "-O2", "-ffast-math" ], "metal_standard": "compiler_default" } }, "candidate_shader": { "msl_source": "#include \nusing namespace metal;\n\n[[kernel]] void mtile_rmsnorm_register(\n device const float* X [[buffer(0)]],\n device const float* W [[buffer(1)]],\n device float* Out [[buffer(2)]],\n constant float& eps [[buffer(3)]],\n uint3 tgp_id [[threadgroup_position_in_grid]],\n uint lid [[thread_index_in_threadgroup]],\n uint sgid [[simdgroup_index_in_threadgroup]],\n uint slid [[thread_index_in_simdgroup]]\n) {\n const uint tgp_id_x = tgp_id.x;\n const uint tgp_id_y = tgp_id.y;\n const uint tgp_id_z = tgp_id.z;\n int v0 = static_cast(tgp_id_x);\n int v2 = v0 * 1024;\n int v9 = v0 * 1024;\n int _metile_register_thread = static_cast(lid);\n int _metile_bounded_thread = _metile_register_thread & 255;\n int _metile_register_index = int(_metile_bounded_thread);\n int _metile_register_packed_ = _metile_bounded_thread + 256;\n int _metile_register_index_ = int(_metile_register_packed_);\n int _metile_register_packed__ = _metile_bounded_thread + 512;\n int _metile_register_index__ = int(_metile_register_packed__);\n int _metile_register_packed___ = _metile_bounded_thread + 768;\n int _metile_register_index___ = int(_metile_register_packed___);\n bool _metile_v16_r0 = _metile_register_index >= 0;\n bool _metile_v16_r1 = _metile_register_index_ >= 0;\n bool _metile_v16_r2 = _metile_register_index__ >= 0;\n bool _metile_v16_r3 = _metile_register_index___ >= 0;\n bool _metile_v17_r0 = _metile_register_index < 1024;\n bool _metile_v17_r1 = _metile_register_index_ < 1024;\n bool _metile_v17_r2 = _metile_register_index__ < 1024;\n bool _metile_v17_r3 = _metile_register_index___ < 1024;\n bool _metile_v18_r0 = _metile_v16_r0 & _metile_v17_r0;\n bool _metile_v18_r1 = _metile_v16_r1 & _metile_v17_r1;\n bool _metile_v18_r2 = _metile_v16_r2 & _metile_v17_r2;\n bool _metile_v18_r3 = _metile_v16_r3 & _metile_v17_r3;\n int _off__metile_v19_r0 = v2 + _metile_register_index;\n int _off__metile_v19_r1 = v2 + _metile_register_index_;\n int _off__metile_v19_r2 = v2 + _metile_register_index__;\n int _off__metile_v19_r3 = v2 + _metile_register_index___;\n float _metile_v20_r0 = _metile_v18_r0 ? X[_off__metile_v19_r0] : static_cast(0);\n float _metile_v20_r1 = _metile_v18_r1 ? X[_off__metile_v19_r1] : static_cast(0);\n float _metile_v20_r2 = _metile_v18_r2 ? X[_off__metile_v19_r2] : static_cast(0);\n float _metile_v20_r3 = _metile_v18_r3 ? X[_off__metile_v19_r3] : static_cast(0);\n float _metile_v21_r0 = static_cast(_metile_v20_r0);\n float _metile_v21_r1 = static_cast(_metile_v20_r1);\n float _metile_v21_r2 = static_cast(_metile_v20_r2);\n float _metile_v21_r3 = static_cast(_metile_v20_r3);\n float _metile_v22_r0 = _metile_v21_r0 * _metile_v21_r0;\n float _metile_v22_r1 = _metile_v21_r1 * _metile_v21_r1;\n float _metile_v22_r2 = _metile_v21_r2 * _metile_v21_r2;\n float _metile_v22_r3 = _metile_v21_r3 * _metile_v21_r3;\n float _metile_register_sum = _metile_v22_r0 + _metile_v22_r1;\n float _metile_register_sum_ = _metile_v22_r2 + _metile_v22_r3;\n float _metile_register_sum__ = _metile_register_sum + _metile_register_sum_;\n threadgroup float _metile_register_reduction[8];\n float v23;\n {\n float _simd_val = simd_sum(_metile_register_sum__);\n if (slid == 0u) _metile_register_reduction[sgid] = _simd_val;\n threadgroup_barrier(mem_flags::mem_threadgroup);\n float _partial = (slid < 8u) ? _metile_register_reduction[slid] : 0.0f;\n v23 = simd_sum(_partial);\n }\n float v25 = v23 / 1024.0f;\n float v26 = v25 + eps;\n float v27 = sqrt(v26);\n float v29 = 1.0f / v27;\n bool _metile_v32_r0 = _metile_register_index >= 0;\n bool _metile_v32_r1 = _metile_register_index_ >= 0;\n bool _metile_v32_r2 = _metile_register_index__ >= 0;\n bool _metile_v32_r3 = _metile_register_index___ >= 0;\n bool _metile_v33_r0 = _metile_register_index < 1024;\n bool _metile_v33_r1 = _metile_register_index_ < 1024;\n bool _metile_v33_r2 = _metile_register_index__ < 1024;\n bool _metile_v33_r3 = _metile_register_index___ < 1024;\n bool _metile_v34_r0 = _metile_v32_r0 & _metile_v33_r0;\n bool _metile_v34_r1 = _metile_v32_r1 & _metile_v33_r1;\n bool _metile_v34_r2 = _metile_v32_r2 & _metile_v33_r2;\n bool _metile_v34_r3 = _metile_v32_r3 & _metile_v33_r3;\n float _metile_v36_r0 = _metile_v34_r0 ? W[_metile_register_index] : static_cast(0);\n float _metile_v36_r1 = _metile_v34_r1 ? W[_metile_register_index_] : static_cast(0);\n float _metile_v36_r2 = _metile_v34_r2 ? W[_metile_register_index__] : static_cast(0);\n float _metile_v36_r3 = _metile_v34_r3 ? W[_metile_register_index___] : static_cast(0);\n float _metile_v37_r0 = static_cast(_metile_v36_r0);\n float _metile_v37_r1 = static_cast(_metile_v36_r1);\n float _metile_v37_r2 = static_cast(_metile_v36_r2);\n float _metile_v37_r3 = static_cast(_metile_v36_r3);\n float _metile_v38_r0 = _metile_v21_r0 * v29;\n float _metile_v38_r1 = _metile_v21_r1 * v29;\n float _metile_v38_r2 = _metile_v21_r2 * v29;\n float _metile_v38_r3 = _metile_v21_r3 * v29;\n float _metile_v39_r0 = _metile_v38_r0 * _metile_v37_r0;\n float _metile_v39_r1 = _metile_v38_r1 * _metile_v37_r1;\n float _metile_v39_r2 = _metile_v38_r2 * _metile_v37_r2;\n float _metile_v39_r3 = _metile_v38_r3 * _metile_v37_r3;\n bool _metile_v41_r0 = _metile_register_index >= 0;\n bool _metile_v41_r1 = _metile_register_index_ >= 0;\n bool _metile_v41_r2 = _metile_register_index__ >= 0;\n bool _metile_v41_r3 = _metile_register_index___ >= 0;\n bool _metile_v42_r0 = _metile_register_index < 1024;\n bool _metile_v42_r1 = _metile_register_index_ < 1024;\n bool _metile_v42_r2 = _metile_register_index__ < 1024;\n bool _metile_v42_r3 = _metile_register_index___ < 1024;\n bool _metile_v43_r0 = _metile_v41_r0 & _metile_v42_r0;\n bool _metile_v43_r1 = _metile_v41_r1 & _metile_v42_r1;\n bool _metile_v43_r2 = _metile_v41_r2 & _metile_v42_r2;\n bool _metile_v43_r3 = _metile_v41_r3 & _metile_v42_r3;\n int _off__metile_v44_r0 = v9 + _metile_register_index;\n int _off__metile_v44_r1 = v9 + _metile_register_index_;\n int _off__metile_v44_r2 = v9 + _metile_register_index__;\n int _off__metile_v44_r3 = v9 + _metile_register_index___;\n if (_metile_v43_r0) { Out[_off__metile_v44_r0] = _metile_v39_r0; }\n if (_metile_v43_r1) { Out[_off__metile_v44_r1] = _metile_v39_r1; }\n if (_metile_v43_r2) { Out[_off__metile_v44_r2] = _metile_v39_r2; }\n if (_metile_v43_r3) { Out[_off__metile_v44_r3] = _metile_v39_r3; }\n}", "source_sha256": "26dcd97c409e667a170eb1ec796096fa645431253522d88e56e53edb0819b727", "function_name": "mtile_rmsnorm_register", "threadgroup_size": [ 256, 1, 1 ], "is_gemm": false, "prefer_ordered": true, "argument_indices": [ 0, 1, 2, 3 ], "output_indices": [ 2 ], "execution_report": { "plan": { "backend": "elementwise", "threadgroup_size": [ 256, 1, 1 ], "simdgroup_grid": null, "tile_shape": [ 1024 ], "staging": "threadgroup", "vector_width": null, "double_buffer": null, "reasons": [ "Lane geometry follows the traced arange/BLOCK contract." ], "cooperative_layout": "checked register/thread-bit ownership; 4 scalar(s) per thread", "outer_bounds_proven": false }, "passes": [ "split_elementwise_loops", "vectorize_elementwise", "fold_constants" ], "loops": [], "allocations": [ { "name": "_metile_register_reduction", "address_space": "threadgroup", "element_type": "float", "elements": 8, "bytes": 32 } ], "double_buffered": false, "vectorized_loads": 0, "epilogue_regions": 0, "notes": [ "Layout widths describe emitted Metal operations, not final machine instructions.", "Masked tails may use scalar accesses even when aligned interiors are vectorized.", "No software double buffering materialized." ], "value_layouts": [ { "value": "v13", "dtype": "i32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v16", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v17", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v18", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v20", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v21", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v22", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v32", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v33", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v34", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v36", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v37", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v38", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v39", "dtype": "f32", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v41", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v42", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 }, { "value": "v43", "dtype": "bool", "shape": [ 1024 ], "layout": { "bit_order": [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 ], "xor_mask": 0, "elements_per_thread": 4 }, "elements_per_thread": 4 } ], "layout_conversions": [], "pipelines": [], "register_reductions": [ { "value": "v23", "operation": "sum", "dtype": "f32", "elements_per_thread": 4, "threads": 256, "scratch": "_metile_register_reduction", "broadcast": "simdgroup" } ], "layout_optimizations": { "conversions_before": 0, "conversions_after": 0, "identities_removed": 0, "inverse_pairs_cancelled": 0, "chains_composed": 0, "rewrites": [], "skipped": [] }, "grouped_loads": 0, "grouped_stores": 0 } }, "frozen_shader_sha256": "66d1816412ae0147101213872436068e71568b9a6dd24815feca3a6605615119", "rounds": [ { "frozen_register4": { "pairs": 570, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 217.66649999999998, "control": 219.25, "speedup": 1.0072748907158429 }, "gpu_us": { "candidate": 8.000002708286047, "control": 8.000002708286047, "speedup": 1.0 } }, "mlx_matched": { "pairs": 550, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 219.97899999999998, "control": 230.95850000000002, "speedup": 1.0499115824692358 } }, "mlx_fast": { "pairs": 570, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 217.91649999999998, "control": 218.167, "speedup": 1.001149522867704 } } }, { "mlx_matched": { "pairs": 354, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 310.521, "control": 354.35400000000004, "speedup": 1.141159535103906 } }, "mlx_fast": { "pairs": 355, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 333.625, "control": 340.66700000000003, "speedup": 1.0211075309104534 } }, "frozen_register4": { "pairs": 448, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 265.084, "control": 266.9375, "speedup": 1.0069921232514976 }, "gpu_us": { "candidate": 11.708325473591685, "control": 12.333330232650042, "speedup": 1.0533812252202985 } } }, { "mlx_fast": { "pairs": 313, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 319.41700000000003, "control": 325.125, "speedup": 1.0178700570101151 } }, "frozen_register4": { "pairs": 532, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 224.97899999999998, "control": 226.77100000000002, "speedup": 1.0079651878619784 }, "gpu_us": { "candidate": 8.291681297123432, "control": 8.45832983031869, "speedup": 1.02009828009828 } }, "mlx_matched": { "pairs": 548, "order": "alternating AB/BA with per-dispatch synchronization", "wall_us": { "candidate": 219.25, "control": 230.708, "speedup": 1.052259977194983 } } } ], "summary": { "frozen_register4": { "wall_us": { "speedup": 1.0074106510499243, "round_speedups": [ 1.0072748907158429, 1.0069921232514976, 1.0079651878619784 ], "candidate": 235.02047361274296, "control": 236.76212833227504 }, "gpu_us": { "speedup": 1.0242576027751034, "round_speedups": [ 1.0, 1.0533812252202985, 1.02009828009828 ], "candidate": 9.191982183222722, "control": 9.414957635739164 } }, "mlx_fast": { "wall_us": { "speedup": 1.0133378257451338, "round_speedups": [ 1.001149522867704, 1.0211075309104534, 1.0178700570101151 ], "candidate": 285.30030946695274, "control": 289.1055952796557 } }, "mlx_matched": { "wall_us": { "speedup": 1.0802908910767444, "round_speedups": [ 1.0499115824692358, 1.141159535103906, 1.052259977194983 ], "candidate": 246.4926272945746, "control": 266.2837399839039 } } } } ], "frozen_manifest": { "kind": "frozen_register_tiling_selection", "recorded_at": "2026-10-02T18:44:42.366590+00:00", "training_process_id": 81341, "training_seed": 1741, "validation_seed": 9473, "compiler_implementation_sha256": "f255b038cc297ff6ba053b68cc787f7e16d855c0b665ab82b8d5ea33c463f8be", "benchmark_source_sha256": "47a379ae8881b98ece7df1f415afed0c5f2b189f9459bf34a14198a22d112675", "baseline_export_sha256": "ddda22c512e09d77a855c6cbbd49b6f1bac26d5db71197d8c05b0e4f0ff257f9", "tuning_report_sha256": "46e22bc7e34901d8ff4c3532a4c96fa0a171f84264065eb9a8d9c0a94e27dca5", "tuning_report": "/Users/andreslavescu/Documents/projects/meTile/benchmarks/results/m5-rmsnorm-tiling-tuning.json", "gate_policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "precision_comparison": { "class": "same_storage_precision", "same_weight_representation": true, "bitwise_exact": false, "primary_policy": "identical storage dtype, FP32 sum/normalization/weight multiply, final output cast", "primary_mlx_comparator": "mx.compile explicit full-FP32 graph then final output cast", "mlx_fast_caveat": "secondary only: FP16 normalization rounds to storage before weight multiply; checked against its own rounding reference", "mlx_fast_source": "https://github.com/ml-explore/mlx/blob/v0.32.0/mlx/backend/metal/kernels/rms_norm.metal", "relaxed_precision": false }, "cases": [ { "name": "float16_1x1009", "dtype": "float16", "batches": 1, "width": 1009 }, { "name": "float16_32x1009", "dtype": "float16", "batches": 32, "width": 1009 }, { "name": "float16_256x1009", "dtype": "float16", "batches": 256, "width": 1009 }, { "name": "float16_1x1024", "dtype": "float16", "batches": 1, "width": 1024 }, { "name": "float16_32x1024", "dtype": "float16", "batches": 32, "width": 1024 }, { "name": "float16_256x1024", "dtype": "float16", "batches": 256, "width": 1024 }, { "name": "float32_1x1009", "dtype": "float32", "batches": 1, "width": 1009 }, { "name": "float32_32x1009", "dtype": "float32", "batches": 32, "width": 1009 }, { "name": "float32_256x1009", "dtype": "float32", "batches": 256, "width": 1009 }, { "name": "float32_1x1024", "dtype": "float32", "batches": 1, "width": 1024 }, { "name": "float32_32x1024", "dtype": "float32", "batches": 32, "width": 1024 }, { "name": "float32_256x1024", "dtype": "float32", "batches": 256, "width": 1024 } ], "variants": [ { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, { "name": "register4_blocked4", "elements_per_thread": 4, "layout": "blocked4" }, { "name": "register8_striped", "elements_per_thread": 8, "layout": "striped" }, { "name": "register8_blocked4", "elements_per_thread": 8, "layout": "blocked4" }, { "name": "register16_striped", "elements_per_thread": 16, "layout": "striped" }, { "name": "register16_blocked4", "elements_per_thread": 16, "layout": "blocked4" }, { "name": "register32_striped", "elements_per_thread": 32, "layout": "striped" }, { "name": "register32_blocked4", "elements_per_thread": 32, "layout": "blocked4" }, { "name": "register2_striped", "elements_per_thread": 2, "layout": "striped" } ], "selection": { "scope": "one layout/count policy for every dtype, width and batch size", "rule": "minimize training wall/ragged guard failures, then maximize worst aligned batch32/256 GPU speedup, then its geometric mean; ties follow declared variant order", "selected": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "scores": [ { "variant": { "name": "register4_striped", "elements_per_thread": 4, "layout": "striped" }, "eligible": true, "regression_guard_failures": 0, "minimum_aligned_throughput_gpu_speedup": 1.0086978283172867, "geomean_aligned_throughput_gpu_speedup": 1.045561445420347, "training_gate": { "passed": false, "policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "failed_aligned_throughput_gpu_cases": [ "float16_32x1024", "float16_256x1024", "float32_32x1024", "float32_256x1024" ], "failed_wall_cases": [], "failed_ragged_gpu_cases": [] } }, { "variant": { "name": "register4_blocked4", "elements_per_thread": 4, "layout": "blocked4" }, "eligible": true, "regression_guard_failures": 6, "minimum_aligned_throughput_gpu_speedup": 0.9237474428973753, "geomean_aligned_throughput_gpu_speedup": 0.9718185576864061, "training_gate": { "passed": false, "policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "failed_aligned_throughput_gpu_cases": [ "float16_32x1024", "float16_256x1024", "float32_32x1024", "float32_256x1024" ], "failed_wall_cases": [], "failed_ragged_gpu_cases": [ "float16_1x1009", "float16_32x1009", "float16_256x1009", "float32_1x1009", "float32_32x1009", "float32_256x1009" ] } }, { "variant": { "name": "register8_striped", "elements_per_thread": 8, "layout": "striped" }, "eligible": true, "regression_guard_failures": 2, "minimum_aligned_throughput_gpu_speedup": 0.9882831778336025, "geomean_aligned_throughput_gpu_speedup": 1.0321442986083251, "training_gate": { "passed": false, "policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "failed_aligned_throughput_gpu_cases": [ "float16_32x1024", "float16_256x1024", "float32_32x1024", "float32_256x1024" ], "failed_wall_cases": [], "failed_ragged_gpu_cases": [ "float16_1x1009", "float32_1x1009" ] } }, { "variant": { "name": "register8_blocked4", "elements_per_thread": 8, "layout": "blocked4" }, "eligible": true, "regression_guard_failures": 6, "minimum_aligned_throughput_gpu_speedup": 0.8814602420184451, "geomean_aligned_throughput_gpu_speedup": 0.9208678007594686, "training_gate": { "passed": false, "policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "failed_aligned_throughput_gpu_cases": [ "float16_32x1024", "float16_256x1024", "float32_32x1024", "float32_256x1024" ], "failed_wall_cases": [], "failed_ragged_gpu_cases": [ "float16_1x1009", "float16_32x1009", "float16_256x1009", "float32_1x1009", "float32_32x1009", "float32_256x1009" ] } }, { "variant": { "name": "register16_striped", "elements_per_thread": 16, "layout": "striped" }, "eligible": true, "regression_guard_failures": 4, "minimum_aligned_throughput_gpu_speedup": 0.9542795309833677, "geomean_aligned_throughput_gpu_speedup": 1.00466326240963, "training_gate": { "passed": false, "policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "failed_aligned_throughput_gpu_cases": [ "float16_32x1024", "float16_256x1024", "float32_32x1024", "float32_256x1024" ], "failed_wall_cases": [], "failed_ragged_gpu_cases": [ "float16_1x1009", "float16_32x1009", "float32_1x1009", "float32_32x1009" ] } }, { "variant": { "name": "register16_blocked4", "elements_per_thread": 16, "layout": "blocked4" }, "eligible": true, "regression_guard_failures": 6, "minimum_aligned_throughput_gpu_speedup": 0.766666666588103, "geomean_aligned_throughput_gpu_speedup": 0.8232797524681654, "training_gate": { "passed": false, "policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "failed_aligned_throughput_gpu_cases": [ "float16_32x1024", "float16_256x1024", "float32_32x1024", "float32_256x1024" ], "failed_wall_cases": [], "failed_ragged_gpu_cases": [ "float16_1x1009", "float16_32x1009", "float16_256x1009", "float32_1x1009", "float32_32x1009", "float32_256x1009" ] } }, { "variant": { "name": "register32_striped", "elements_per_thread": 32, "layout": "striped" }, "eligible": true, "regression_guard_failures": 4, "minimum_aligned_throughput_gpu_speedup": 0.8381200151101741, "geomean_aligned_throughput_gpu_speedup": 0.9307341209660918, "training_gate": { "passed": false, "policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "failed_aligned_throughput_gpu_cases": [ "float16_32x1024", "float16_256x1024", "float32_32x1024", "float32_256x1024" ], "failed_wall_cases": [], "failed_ragged_gpu_cases": [ "float16_1x1009", "float16_32x1009", "float32_1x1009", "float32_32x1009" ] } }, { "variant": { "name": "register32_blocked4", "elements_per_thread": 32, "layout": "blocked4" }, "eligible": true, "regression_guard_failures": 8, "minimum_aligned_throughput_gpu_speedup": 0.5679061317298304, "geomean_aligned_throughput_gpu_speedup": 0.727493385335174, "training_gate": { "passed": false, "policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "failed_aligned_throughput_gpu_cases": [ "float16_32x1024", "float16_256x1024", "float32_32x1024", "float32_256x1024" ], "failed_wall_cases": [ "float16_1x1009", "float32_1x1009" ], "failed_ragged_gpu_cases": [ "float16_1x1009", "float16_32x1009", "float16_256x1009", "float32_1x1009", "float32_32x1009", "float32_256x1009" ] } }, { "variant": { "name": "register2_striped", "elements_per_thread": 2, "layout": "striped" }, "eligible": true, "regression_guard_failures": 1, "minimum_aligned_throughput_gpu_speedup": 1.017094119129839, "geomean_aligned_throughput_gpu_speedup": 1.0256124991977755, "training_gate": { "passed": false, "policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "failed_aligned_throughput_gpu_cases": [ "float16_32x1024", "float16_256x1024", "float32_32x1024", "float32_256x1024" ], "failed_wall_cases": [], "failed_ragged_gpu_cases": [ "float16_256x1009" ] } } ], "heldout_results_used": false } }, "manifest_sha256": "49b5092adbc64b2a5b3a627bd7ad209d5c05d8a9a2350dd64b49485111bc373a", "promotion_gate": { "passed": false, "policy": { "aligned_throughput_gpu_speedup_minimum": 1.1, "aligned_throughput_batches": [ 32, 256 ], "every_case_wall_latency_ratio_maximum": 1.03, "every_ragged_case_gpu_latency_ratio_maximum": 1.03, "reference": "frozen prechange static-width register4 striped kernel", "promotion": "opt-in unless every heldout guard passes; no automatic default changes" }, "failed_aligned_throughput_gpu_cases": [ "float16_32x1024", "float16_256x1024", "float32_32x1024", "float32_256x1024" ], "failed_wall_cases": [], "failed_ragged_gpu_cases": [] } }